reg2 238 arch/arm/probes/kprobes/test-core.h #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ reg2 239 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg2 241 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg2, val2) \ reg2 243 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \ reg2 246 arch/arm/probes/kprobes/test-core.h #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ reg2 247 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg2 249 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg2, val2) \ reg2 252 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg2 255 arch/arm/probes/kprobes/test-core.h #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ reg2 256 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \ reg2 258 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg2, val2) \ reg2 262 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \ reg2 272 arch/arm/probes/kprobes/test-core.h #define TEST_PR(code1, reg1, val1, code2, reg2, val2, code3) \ reg2 273 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg2 275 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg2, val2) \ reg2 277 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \ reg2 280 arch/arm/probes/kprobes/test-core.h #define TEST_RP(code1, reg1, val1, code2, reg2, val2, code3) \ reg2 281 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg2 283 arch/arm/probes/kprobes/test-core.h TEST_ARG_PTR(reg2, val2) \ reg2 285 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \ reg2 288 arch/arm/probes/kprobes/test-core.h #define TEST_PRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ reg2 289 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg2 291 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg2, val2) \ reg2 294 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg2 297 arch/arm/probes/kprobes/test-core.h #define TEST_RPR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ reg2 298 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg2 300 arch/arm/probes/kprobes/test-core.h TEST_ARG_PTR(reg2, val2) \ reg2 303 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg2 306 arch/arm/probes/kprobes/test-core.h #define TEST_RRP(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ reg2 307 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg2 309 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg2, val2) \ reg2 312 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg2 348 arch/arm/probes/kprobes/test-core.h #define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \ reg2 349 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg2 351 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg2, val2) \ reg2 353 arch/arm/probes/kprobes/test-core.h TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3) \ reg2 392 arch/arm/probes/kprobes/test-core.h #define TEST_RRX(code1, reg1, val1, code2, reg2, val2, code3, codex) \ reg2 393 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg2 395 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg2, val2) \ reg2 397 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 __stringify(reg1) code2 __stringify(reg2) code3) \ reg2 233 arch/arm64/include/asm/alternative.h .macro uao_ldp l, reg1, reg2, addr, post_inc reg2 248 arch/arm64/include/asm/alternative.h .macro uao_stp l, reg1, reg2, addr, post_inc reg2 275 arch/arm64/include/asm/alternative.h .macro uao_ldp l, reg1, reg2, addr, post_inc reg2 278 arch/arm64/include/asm/alternative.h .macro uao_stp l, reg1, reg2, addr, post_inc reg2 646 arch/arm64/include/asm/assembler.h .macro __frame_regs, reg1, reg2, op, num reg2 383 arch/arm64/include/asm/insn.h enum aarch64_insn_register reg2, reg2 434 arch/arm64/include/asm/insn.h enum aarch64_insn_register reg2, reg2 26 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_save_state base, reg1, reg2 reg2 44 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_restore_state base, reg1, reg2 reg2 69 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_switch_to_guest g_ctxt, reg1, reg2, reg3 reg2 85 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_switch_to_host g_ctxt, h_ctxt, reg1, reg2, reg3 reg2 105 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_switch_to_guest g_ctxt, reg1, reg2, reg3 reg2 107 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_switch_to_host g_ctxt, h_ctxt, reg1, reg2, reg3 reg2 628 arch/arm64/kernel/insn.c enum aarch64_insn_register reg2, reg2 682 arch/arm64/kernel/insn.c reg2); reg2 1161 arch/arm64/kernel/insn.c enum aarch64_insn_register reg2, reg2 1198 arch/arm64/kernel/insn.c reg2); reg2 322 arch/mips/include/asm/uasm.h unsigned int reg2, int lid); reg2 105 arch/mips/mm/page.c pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off) reg2 113 arch/mips/mm/page.c uasm_i_daddu(buf, reg1, reg2, T9); reg2 118 arch/mips/mm/page.c UASM_i_ADDU(buf, reg1, reg2, T9); reg2 120 arch/mips/mm/page.c UASM_i_ADDIU(buf, reg1, reg2, off); reg2 598 arch/mips/mm/uasm.c unsigned int reg2, int lid) reg2 601 arch/mips/mm/uasm.c uasm_i_bne(p, reg1, reg2, 0); reg2 19 arch/nios2/include/asm/asm-macros.h .macro ANDI32 reg1, reg2, mask reg2 39 arch/nios2/include/asm/asm-macros.h .macro ORI32 reg1, reg2, mask reg2 58 arch/nios2/include/asm/asm-macros.h .macro XORI32 reg1, reg2, mask reg2 78 arch/nios2/include/asm/asm-macros.h .macro BT reg1, reg2, bit reg2 97 arch/nios2/include/asm/asm-macros.h .macro BTBZ reg1, reg2, bit, label reg2 109 arch/nios2/include/asm/asm-macros.h .macro BTBNZ reg1, reg2, bit, label reg2 121 arch/nios2/include/asm/asm-macros.h .macro BTC reg1, reg2, bit reg2 142 arch/nios2/include/asm/asm-macros.h .macro BTS reg1, reg2, bit reg2 163 arch/nios2/include/asm/asm-macros.h .macro BTR reg1, reg2, bit reg2 185 arch/nios2/include/asm/asm-macros.h .macro BTCBZ reg1, reg2, bit, label reg2 198 arch/nios2/include/asm/asm-macros.h .macro BTCBNZ reg1, reg2, bit, label reg2 211 arch/nios2/include/asm/asm-macros.h .macro BTSBZ reg1, reg2, bit, label reg2 224 arch/nios2/include/asm/asm-macros.h .macro BTSBNZ reg1, reg2, bit, label reg2 237 arch/nios2/include/asm/asm-macros.h .macro BTRBZ reg1, reg2, bit, label reg2 250 arch/nios2/include/asm/asm-macros.h .macro BTRBNZ reg1, reg2, bit, label reg2 262 arch/nios2/include/asm/asm-macros.h .macro TSTBZ reg1, reg2, mask, label reg2 274 arch/nios2/include/asm/asm-macros.h .macro TSTBNZ reg1, reg2, mask, label reg2 29 arch/s390/boot/ipl_parm.c unsigned long reg1, reg2; reg2 40 arch/s390/boot/ipl_parm.c : "=&d" (reg1), "=&a" (reg2), reg2 72 arch/s390/boot/mem_detect.c unsigned long reg1, reg2; reg2 85 arch/s390/boot/mem_detect.c : "=&d" (reg1), "=&a" (reg2), reg2 58 arch/s390/include/asm/ap.h register unsigned long reg2 asm ("2") = 0; reg2 65 arch/s390/include/asm/ap.h : "+d" (reg1), "+d" (reg2) reg2 82 arch/s390/include/asm/ap.h register unsigned long reg2 asm ("2"); reg2 85 arch/s390/include/asm/ap.h : "=d" (reg1), "=d" (reg2) reg2 89 arch/s390/include/asm/ap.h *info = reg2; reg2 177 arch/s390/include/asm/ap.h register struct ap_config_info *reg2 asm ("2") = config; reg2 185 arch/s390/include/asm/ap.h : "d" (reg0), "d" (reg2) reg2 229 arch/s390/include/asm/ap.h register void *reg2 asm ("2") = ind; reg2 236 arch/s390/include/asm/ap.h : "d" (reg0), "d" (reg2) reg2 277 arch/s390/include/asm/ap.h register unsigned long reg2 asm ("2"); reg2 283 arch/s390/include/asm/ap.h : "+d" (reg1), "=d" (reg2) reg2 286 arch/s390/include/asm/ap.h apinfo->val = reg2; reg2 308 arch/s390/include/asm/ap.h register unsigned long reg2 asm ("2") = (unsigned long) msg; reg2 316 arch/s390/include/asm/ap.h : "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3) reg2 346 arch/s390/include/asm/ap.h register unsigned long reg2 asm("2") = 0UL; reg2 356 arch/s390/include/asm/ap.h : "+d" (reg0), "=d" (reg1), "+d" (reg2), reg2 32 arch/s390/include/asm/checksum.h register unsigned long reg2 asm("2") = (unsigned long) buff; reg2 38 arch/s390/include/asm/checksum.h : "+d" (sum), "+d" (reg2), "+d" (reg3) : : "cc", "memory"); reg2 58 arch/s390/include/asm/page.h register void *reg2 asm ("2") = to; reg2 64 arch/s390/include/asm/page.h : "+d" (reg2), "+d" (reg3), "+d" (reg4), "+d" (reg5) reg2 550 arch/s390/include/asm/pgtable.h register unsigned long reg2 asm("2") = old; reg2 556 arch/s390/include/asm/pgtable.h : "+d" (reg2), "+m" (*ptr) reg2 563 arch/s390/include/asm/pgtable.h register unsigned long reg2 asm("2") = old; reg2 569 arch/s390/include/asm/pgtable.h : "+d" (reg2), "+m" (*ptr) reg2 584 arch/s390/include/asm/pgtable.h register unsigned long reg2 asm("2") = old; reg2 590 arch/s390/include/asm/pgtable.h : "+d" (reg2) reg2 277 arch/s390/include/asm/processor.h unsigned int reg1, reg2; reg2 279 arch/s390/include/asm/processor.h asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); reg2 280 arch/s390/include/asm/processor.h return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); reg2 29 arch/s390/kernel/cpcmd.c register unsigned long reg2 asm ("2") = (addr_t) cpcmd_buf; reg2 34 arch/s390/kernel/cpcmd.c : "+d" (reg3) : "d" (reg2) : "cc"); reg2 40 arch/s390/kernel/cpcmd.c register unsigned long reg2 asm ("2") = (addr_t) cpcmd_buf; reg2 51 arch/s390/kernel/cpcmd.c : "d" (reg2), "d" (reg3), "d" (*rlen) : "cc"); reg2 317 arch/s390/kvm/intercept.c int reg1, reg2, rc; reg2 319 arch/s390/kvm/intercept.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg2 322 arch/s390/kvm/intercept.c rc = guest_translate_address(vcpu, vcpu->run->s.regs.gprs[reg2], reg2 323 arch/s390/kvm/intercept.c reg2, &srcaddr, GACC_FETCH); reg2 363 arch/s390/kvm/intercept.c int reg1, reg2, r = 0; reg2 370 arch/s390/kvm/intercept.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg2 372 arch/s390/kvm/intercept.c addr = vcpu->run->s.regs.gprs[reg2]; reg2 378 arch/s390/kvm/intercept.c if (reg1 == reg2 || reg1 & 1 || reg2 & 1) reg2 398 arch/s390/kvm/intercept.c r = write_guest(vcpu, addr, reg2, sctns, PAGE_SIZE); reg2 406 arch/s390/kvm/intercept.c vcpu->run->s.regs.gprs[reg2 + 1] = rc; reg2 250 arch/s390/kvm/priv.c int reg1, reg2; reg2 263 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg2 265 arch/s390/kvm/priv.c gaddr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; reg2 297 arch/s390/kvm/priv.c int reg1, reg2; reg2 310 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg2 312 arch/s390/kvm/priv.c gaddr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; reg2 348 arch/s390/kvm/priv.c int reg1, reg2; reg2 368 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg2 371 arch/s390/kvm/priv.c start = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; reg2 418 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg2] &= ~PAGE_MASK; reg2 420 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg2] &= ~0xfffff000UL; reg2 422 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg2] |= end; reg2 441 arch/s390/kvm/priv.c int reg2; reg2 448 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, NULL, ®2); reg2 449 arch/s390/kvm/priv.c addr = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; reg2 980 arch/s390/kvm/priv.c int reg1, reg2; reg2 984 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg2 989 arch/s390/kvm/priv.c if (reg2) { reg2 990 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg2] &= 0xffffffff00000000UL; reg2 991 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg2] |= reg2 1010 arch/s390/kvm/priv.c int reg1, reg2; reg2 1016 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg2 1041 arch/s390/kvm/priv.c start = vcpu->run->s.regs.gprs[reg2] & PAGE_MASK; reg2 1109 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg2] = end; reg2 1111 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg2] &= ~0xffffffffUL; reg2 1113 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg2] |= end; reg2 146 arch/x86/events/intel/uncore.c struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; reg2 162 arch/x86/events/intel/uncore.c (er->config1 == reg1->config && er->config2 == reg2->config)) { reg2 165 arch/x86/events/intel/uncore.c er->config2 = reg2->config; reg2 354 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &hwc->branch_reg; reg2 373 arch/x86/events/intel/uncore_nhmex.c reg2->config = event->attr.config2; reg2 381 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &hwc->branch_reg; reg2 385 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 1, reg2->config); reg2 445 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &hwc->branch_reg; reg2 458 arch/x86/events/intel/uncore_nhmex.c reg2->config = event->attr.config2; reg2 466 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &hwc->branch_reg; reg2 471 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 2, reg2->config); reg2 672 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; reg2 693 arch/x86/events/intel/uncore_nhmex.c if (reg2->idx != EXTRA_REG_NONE && reg2 694 arch/x86/events/intel/uncore_nhmex.c (uncore_box_is_fake(box) || !reg2->alloc) && reg2 695 arch/x86/events/intel/uncore_nhmex.c !nhmex_mbox_get_shared_reg(box, reg2->idx, reg2->config)) reg2 708 arch/x86/events/intel/uncore_nhmex.c if (reg2->idx != EXTRA_REG_NONE) reg2 709 arch/x86/events/intel/uncore_nhmex.c reg2->alloc = 1; reg2 741 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; reg2 752 arch/x86/events/intel/uncore_nhmex.c if (reg2->alloc) { reg2 753 arch/x86/events/intel/uncore_nhmex.c nhmex_mbox_put_shared_reg(box, reg2->idx); reg2 754 arch/x86/events/intel/uncore_nhmex.c reg2->alloc = 0; reg2 769 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; reg2 806 arch/x86/events/intel/uncore_nhmex.c reg2->idx = EXTRA_REG_NHMEX_M_FILTER; reg2 808 arch/x86/events/intel/uncore_nhmex.c reg2->config = event->attr.config2; reg2 810 arch/x86/events/intel/uncore_nhmex.c reg2->config = ~0ULL; reg2 812 arch/x86/events/intel/uncore_nhmex.c reg2->reg = NHMEX_M0_MSR_PMU_MM_CFG; reg2 814 arch/x86/events/intel/uncore_nhmex.c reg2->reg = NHMEX_M1_MSR_PMU_MM_CFG; reg2 839 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &hwc->branch_reg; reg2 851 arch/x86/events/intel/uncore_nhmex.c if (reg2->idx != EXTRA_REG_NONE) { reg2 852 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg, 0); reg2 853 arch/x86/events/intel/uncore_nhmex.c if (reg2->config != ~0ULL) { reg2 854 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg + 1, reg2 855 arch/x86/events/intel/uncore_nhmex.c reg2->config & NHMEX_M_PMON_ADDR_MATCH_MASK); reg2 856 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg + 2, NHMEX_M_PMON_ADDR_MASK_MASK & reg2 857 arch/x86/events/intel/uncore_nhmex.c (reg2->config >> NHMEX_M_PMON_ADDR_MASK_SHIFT)); reg2 858 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg2->reg, NHMEX_M_PMON_MM_CFG_EN); reg2 982 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &hwc->branch_reg; reg2 1026 arch/x86/events/intel/uncore_nhmex.c er->config2 == reg2->config)) { reg2 1030 arch/x86/events/intel/uncore_nhmex.c er->config2 = reg2->config; reg2 1090 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &event->hw.branch_reg; reg2 1105 arch/x86/events/intel/uncore_nhmex.c reg2->config = event->attr.config2; reg2 1115 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg2 = &hwc->branch_reg; reg2 1137 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MASK(port), reg2->config); reg2 1143 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MASK(port), reg2->config); reg2 1103 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg2 = &hwc->branch_reg; reg2 1109 arch/x86/events/intel/uncore_snbep.c reg2->reg = SNBEP_Q_Py_PCI_PMON_PKT_MASK0; reg2 1110 arch/x86/events/intel/uncore_snbep.c reg2->config = event->attr.config2; reg2 1120 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg2 = &hwc->branch_reg; reg2 1132 arch/x86/events/intel/uncore_snbep.c pci_write_config_dword(filter_pdev, reg2->reg, reg2 1133 arch/x86/events/intel/uncore_snbep.c (u32)reg2->config); reg2 1134 arch/x86/events/intel/uncore_snbep.c pci_write_config_dword(filter_pdev, reg2->reg + 4, reg2 1135 arch/x86/events/intel/uncore_snbep.c (u32)(reg2->config >> 32)); reg2 338 arch/x86/kernel/uprobes.c u8 reg2; reg2 413 arch/x86/kernel/uprobes.c reg2 = 0xff; /* Fetch vex.vvvv */ reg2 415 arch/x86/kernel/uprobes.c reg2 = insn->vex_prefix.bytes[2]; reg2 423 arch/x86/kernel/uprobes.c reg2 = ((reg2 >> 3) & 0x7) ^ 0x7; reg2 430 arch/x86/kernel/uprobes.c if (reg != 6 && reg2 != 6) { reg2 431 arch/x86/kernel/uprobes.c reg2 = 6; reg2 433 arch/x86/kernel/uprobes.c } else if (reg != 7 && reg2 != 7) { reg2 434 arch/x86/kernel/uprobes.c reg2 = 7; reg2 438 arch/x86/kernel/uprobes.c reg2 = 3; reg2 452 arch/x86/kernel/uprobes.c *cursor = 0x80 | (reg << 3) | reg2; reg2 262 drivers/ata/pata_macio.c u32 reg2; /* Bits to set in second timing reg */ reg2 421 drivers/ata/pata_macio.c if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) { reg2 429 drivers/ata/pata_macio.c priv->treg[adev->devno][1] |= t->reg2; reg2 75 drivers/clk/mvebu/armada-37xx-periph.c void __iomem *reg2; reg2 150 drivers/clk/mvebu/armada-37xx-periph.c .reg2 = (void *)_reg2, \ reg2 341 drivers/clk/mvebu/armada-37xx-periph.c div *= get_div(double_div->reg2, double_div->shift2); reg2 644 drivers/clk/mvebu/armada-37xx-periph.c rate->reg2 = reg + (u64)rate->reg2; reg2 110 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c uint32_t reg2; reg2 114 drivers/gpu/drm/amd/display/dc/gpio/hw_ddc.c reg2 = REG_GET_2(gpio.MASK_reg, reg2 105 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg2 113 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c .ack_reg = SRI(reg2, block, reg_num),\ reg2 115 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ reg2 117 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ reg2 186 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg2 194 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c .ack_reg = SRI(reg2, block, reg_num),\ reg2 196 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ reg2 198 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ reg2 188 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg2 196 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c .ack_reg = SRI(reg2, block, reg_num),\ reg2 198 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ reg2 200 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ reg2 184 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg2 192 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c .ack_reg = SRI(reg2, block, reg_num),\ reg2 194 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\ reg2 196 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \ reg2 340 drivers/gpu/drm/mga/mga_drv.h #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \ reg2 344 drivers/gpu/drm/mga/mga_drv.h (DMAREG(reg2) << 16) | \ reg2 181 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); reg2 183 drivers/gpu/drm/nouveau/dispnv04/hw.c pll2 = nvif_rd32(device, reg2); reg2 204 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); reg2 206 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldpll2 = !nv3035 ? nvkm_rd32(device, reg2) : 0; reg2 266 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_wr32(device, reg2, pll2); reg2 123 drivers/gpu/ipu-v3/ipu-dc.c u32 reg1, reg2; reg2 127 drivers/gpu/ipu-v3/ipu-dc.c reg2 = operand >> 12 | opcode << 1 | stop << 9; reg2 130 drivers/gpu/ipu-v3/ipu-dc.c reg2 = operand >> 17 | opcode << 7 | stop << 9; reg2 133 drivers/gpu/ipu-v3/ipu-dc.c reg2 = operand >> 12 | opcode << 4 | stop << 9; reg2 136 drivers/gpu/ipu-v3/ipu-dc.c writel(reg2, priv->dc_tmpl_reg + word * 8 + 4); reg2 358 drivers/hwmon/nct7904.c unsigned int reg1, reg2, reg3; reg2 432 drivers/hwmon/nct7904.c reg2 = TEMP_CH1_W_REG; reg2 437 drivers/hwmon/nct7904.c reg2 = TEMP_CH1_WH_REG; reg2 442 drivers/hwmon/nct7904.c reg2 = TEMP_CH1_C_REG; reg2 447 drivers/hwmon/nct7904.c reg2 = TEMP_CH1_CH_REG; reg2 458 drivers/hwmon/nct7904.c reg2 + channel * 8); reg2 535 drivers/hwmon/nct7904.c unsigned int reg1, reg2, reg3; reg2 542 drivers/hwmon/nct7904.c reg2 = TEMP_CH1_W_REG; reg2 547 drivers/hwmon/nct7904.c reg2 = TEMP_CH1_WH_REG; reg2 552 drivers/hwmon/nct7904.c reg2 = TEMP_CH1_C_REG; reg2 557 drivers/hwmon/nct7904.c reg2 = TEMP_CH1_CH_REG; reg2 567 drivers/hwmon/nct7904.c reg2 + channel * 8, val); reg2 73 drivers/ide/ali14xx.c static struct { u8 reg1, reg2, reg3, reg4; } regTab[4] = { reg2 140 drivers/ide/ali14xx.c outReg(param2, regTab[driveNum].reg2); reg2 341 drivers/iio/light/lm3533-als.c u8 reg, reg2; reg2 348 drivers/iio/light/lm3533-als.c reg2 = lm3533_als_get_threshold_reg(nr, !raising); reg2 351 drivers/iio/light/lm3533-als.c ret = lm3533_read(als->lm3533, reg2, &val2); reg2 724 drivers/iio/light/si1145.c u8 reg1, reg2, shift; reg2 735 drivers/iio/light/si1145.c reg2 = SI1145_PARAM_PS_ADC_COUNTER; reg2 743 drivers/iio/light/si1145.c reg2 = SI1145_PARAM_ALSIR_ADC_COUNTER; reg2 746 drivers/iio/light/si1145.c reg2 = SI1145_PARAM_ALSVIS_ADC_COUNTER; reg2 763 drivers/iio/light/si1145.c ret = si1145_param_set(data, reg2, (~val & 0x07) << 4); reg2 6746 drivers/infiniband/hw/qib/qib_iba7322.c u64 reg, reg1, reg2; reg2 6762 drivers/infiniband/hw/qib/qib_iba7322.c reg2 = qib_read_kreg_port(ppd, krp_senddmabufmask2); reg2 6765 drivers/infiniband/hw/qib/qib_iba7322.c reg, reg1, reg2); reg2 6772 drivers/infiniband/hw/qib/qib_iba7322.c reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2); reg2 6773 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg2); reg2 6777 drivers/infiniband/hw/qib/qib_iba7322.c reg, reg1, reg2); reg2 6780 drivers/infiniband/hw/qib/qib_iba7322.c reg2 = qib_read_kreg_port(ppd, krp_senddmabuf_use2); reg2 6784 drivers/infiniband/hw/qib/qib_iba7322.c reg, reg1, reg2); reg2 324 drivers/input/touchscreen/rohm_bu21023.c u8 reg1, reg2, reg3; reg2 410 drivers/input/touchscreen/rohm_bu21023.c reg2 = (reg_y & 0x7) << 4 | (reg_x & 0x7); reg2 419 drivers/input/touchscreen/rohm_bu21023.c CALIBRATION_REG2, reg2); reg2 67 drivers/mcb/mcb-internal.h __le32 reg2; reg2 48 drivers/mcb/mcb-parse.c __le32 reg2; reg2 55 drivers/mcb/mcb-parse.c reg2 = readl(&gdd->reg2); reg2 62 drivers/mcb/mcb-parse.c mdev->bar = GDD_BAR(reg2); reg2 63 drivers/mcb/mcb-parse.c mdev->group = GDD_GRP(reg2); reg2 64 drivers/mcb/mcb-parse.c mdev->inst = GDD_INS(reg2); reg2 110 drivers/media/dvb-frontends/nxt200x.c u8 reg2 [] = { reg }; reg2 112 drivers/media/dvb-frontends/nxt200x.c struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = reg2, .len = 1 }, reg2 556 drivers/media/dvb-frontends/s5h1409.c u16 reg, reg1, reg2; reg2 572 drivers/media/dvb-frontends/s5h1409.c reg2 = s5h1409_readreg(state, 0xad); reg2 576 drivers/media/dvb-frontends/s5h1409.c (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); reg2 594 drivers/media/dvb-frontends/s5h1409.c u16 reg, reg1, reg2; reg2 603 drivers/media/dvb-frontends/s5h1409.c reg2 = s5h1409_readreg(state, 0xad); reg2 607 drivers/media/dvb-frontends/s5h1409.c (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); reg2 483 drivers/media/dvb-frontends/si21xx.c u8 reg2[2]; reg2 515 drivers/media/dvb-frontends/si21xx.c reg2[0] = reg2 521 drivers/media/dvb-frontends/si21xx.c reg2[1] = 0; reg2 526 drivers/media/dvb-frontends/si21xx.c status |= si21_writeregs(state, TS_CTRL_REG_1, reg2, 0x02); reg2 65 drivers/media/dvb-frontends/tua6100.c u8 reg2[] = { 0x02, 0x00, 0x00 }; reg2 68 drivers/media/dvb-frontends/tua6100.c struct i2c_msg msg2 = { .addr = priv->i2c_address, .flags = 0, .buf = reg2, .len = 3 }; reg2 92 drivers/media/dvb-frontends/tua6100.c reg2[1] = (_R_VAL >> 8) & 0x03; reg2 93 drivers/media/dvb-frontends/tua6100.c reg2[2] = _R_VAL; reg2 95 drivers/media/dvb-frontends/tua6100.c reg2[1] |= 0x1c; reg2 97 drivers/media/dvb-frontends/tua6100.c reg2[1] |= 0x0c; reg2 99 drivers/media/dvb-frontends/tua6100.c reg2[1] |= 0x1c; reg2 322 drivers/media/i2c/ov6650.c uint8_t reg, reg2; reg2 334 drivers/media/i2c/ov6650.c ret = ov6650_reg_read(client, REG_RED, ®2); reg2 337 drivers/media/i2c/ov6650.c priv->red->val = reg2; reg2 860 drivers/media/i2c/ov9650.c u8 reg0, reg1, reg2; reg2 890 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_AECHM, ®2); reg2 893 drivers/media/i2c/ov9650.c exposure = ((reg2 & 0x3f) << 10) | (reg1 << 2) | reg2 241 drivers/media/tuners/tda827x.c unsigned char reg2[2]; reg2 279 drivers/media/tuners/tda827x.c msg.buf = reg2; reg2 281 drivers/media/tuners/tda827x.c reg2[0] = 0x80; reg2 282 drivers/media/tuners/tda827x.c reg2[1] = 0; reg2 285 drivers/media/tuners/tda827x.c reg2[0] = 0x60; reg2 286 drivers/media/tuners/tda827x.c reg2[1] = 0xbf; reg2 289 drivers/media/tuners/tda827x.c reg2[0] = 0x30; reg2 290 drivers/media/tuners/tda827x.c reg2[1] = tuner_reg[4] + 0x80; reg2 294 drivers/media/tuners/tda827x.c reg2[0] = 0x30; reg2 295 drivers/media/tuners/tda827x.c reg2[1] = tuner_reg[4] + 4; reg2 299 drivers/media/tuners/tda827x.c reg2[0] = 0x30; reg2 300 drivers/media/tuners/tda827x.c reg2[1] = tuner_reg[4]; reg2 304 drivers/media/tuners/tda827x.c reg2[0] = 0x30; reg2 305 drivers/media/tuners/tda827x.c reg2[1] = (tuner_reg[4] & 0xfc) + tda827x_table[i].cp; reg2 308 drivers/media/tuners/tda827x.c reg2[0] = 0x60; reg2 309 drivers/media/tuners/tda827x.c reg2[1] = 0x3f; reg2 312 drivers/media/tuners/tda827x.c reg2[0] = 0x80; reg2 313 drivers/media/tuners/tda827x.c reg2[1] = 0x08; /* Vsync en */ reg2 557 drivers/media/usb/dvb-usb-v2/af9015.c unsigned int utmp1, utmp2, reg1, reg2; reg2 575 drivers/media/usb/dvb-usb-v2/af9015.c reg2 = 0xdd0c; reg2 579 drivers/media/usb/dvb-usb-v2/af9015.c reg2 = 0xdd0d; reg2 584 drivers/media/usb/dvb-usb-v2/af9015.c ret = regmap_write(state->regmap, reg2, utmp2); reg2 407 drivers/net/dsa/sja1105/sja1105_dynamic_config.c u8 *reg2 = buf; reg2 420 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg2, &entry->tp_delin, 31, 16, size, op); reg2 421 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg2, &entry->tp_delout, 15, 0, size, op); reg2 1283 drivers/net/ethernet/intel/i40e/i40e_common.c u32 reg2 = 0; reg2 1295 drivers/net/ethernet/intel/i40e/i40e_common.c reg2 = rd32(hw, I40E_GLGEN_RSTAT); reg2 1296 drivers/net/ethernet/intel/i40e/i40e_common.c if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) reg2 1300 drivers/net/ethernet/intel/i40e/i40e_common.c if (reg2 & I40E_GLGEN_RSTAT_DEVSTATE_MASK) { reg2 789 drivers/net/ethernet/marvell/skge.c u32 reg2; reg2 791 drivers/net/ethernet/marvell/skge.c pci_read_config_dword(skge->hw->pdev, PCI_DEV_REG2, ®2); reg2 792 drivers/net/ethernet/marvell/skge.c return 1 << (((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); reg2 4257 drivers/net/ethernet/marvell/sky2.c u16 reg2; reg2 4259 drivers/net/ethernet/marvell/sky2.c reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); reg2 4260 drivers/net/ethernet/marvell/sky2.c return 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); reg2 4461 drivers/net/ethernet/marvell/sky2.c u16 reg2; reg2 4463 drivers/net/ethernet/marvell/sky2.c reg2 = sky2_pci_read16(hw, PCI_DEV_REG2); reg2 4464 drivers/net/ethernet/marvell/sky2.c vpd_size = 1 << ( ((reg2 & PCI_VPD_ROM_SZ) >> 14) + 8); reg2 50 drivers/net/ethernet/netronome/nfp/bpf/verifier.c const struct bpf_reg_state *reg2) reg2 59 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg2->type != SCALAR_VALUE || !tnum_is_const(reg2->var_off)) reg2 61 drivers/net/ethernet/netronome/nfp/bpf/verifier.c imm = reg2->var_off.value; reg2 175 drivers/net/ethernet/netronome/nfp/bpf/verifier.c const struct bpf_reg_state *reg2 = cur_regs(env) + BPF_REG_2; reg2 191 drivers/net/ethernet/netronome/nfp/bpf/verifier.c nfp_record_adjust_head(bpf, nfp_prog, meta, reg2); reg2 204 drivers/net/ethernet/netronome/nfp/bpf/verifier.c !nfp_bpf_stack_arg_ok("map_lookup", env, reg2, reg2 212 drivers/net/ethernet/netronome/nfp/bpf/verifier.c !nfp_bpf_stack_arg_ok("map_update", env, reg2, reg2 222 drivers/net/ethernet/netronome/nfp/bpf/verifier.c !nfp_bpf_stack_arg_ok("map_delete", env, reg2, reg2 305 drivers/net/ethernet/netronome/nfp/bpf/verifier.c meta->arg2.reg = *reg2; reg2 625 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 749 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 831 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 1565 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 5373 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 5457 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 5546 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 5628 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 6456 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 7433 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 7727 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 7819 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 8467 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 8772 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 8854 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 8923 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 9429 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 9473 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 9517 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 9768 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 10365 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 10769 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 10942 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 11157 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 11402 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 11595 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 11721 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg2; reg2 971 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg2; reg2 983 drivers/net/ethernet/qlogic/qla3xxx.c err = ql_mii_read_reg(qdev, PHY_ID_1_REG, ®2); reg2 990 drivers/net/ethernet/qlogic/qla3xxx.c if ((reg1 == 0xffff) || (reg2 == 0xffff)) { reg2 1006 drivers/net/ethernet/qlogic/qla3xxx.c err = ql_mii_read_reg_ex(qdev, PHY_ID_1_REG, ®2, miiAddr); reg2 1018 drivers/net/ethernet/qlogic/qla3xxx.c qdev->phyType = getPhyType(qdev, reg1, reg2); reg2 539 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 reg, reg1, reg2, i, j, owner, class; reg2 542 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg2 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_2); reg2 553 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = reg2; reg2 252 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c u32 cap, reg, val, reg2; reg2 368 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c reg2 = ahw->intr_tbl[i].src; reg2 370 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c reg2 = le32_to_cpu(prsp_sds[i].interrupt_crb); reg2 372 drivers/net/ethernet/qlogic/qlcnic/qlcnic_ctx.c sds_ring->crb_intr_mask = ahw->pci_base0 + reg2; reg2 373 drivers/net/ethernet/socionext/sni_ave.c int reg1, int reg2) reg2 379 drivers/net/ethernet/socionext/sni_ave.c writel(mac_addr[4] | mac_addr[5] << 8, priv->base + reg2); reg2 2610 drivers/net/ethernet/sun/niu.c u16 reg2 = addr[0] << 8 | addr[1]; reg2 2615 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_ADDR2, reg2); reg2 2619 drivers/net/ethernet/sun/niu.c nw64_mac(BMAC_ADDR2, reg2); reg2 2635 drivers/net/ethernet/sun/niu.c u16 reg2 = addr[0] << 8 | addr[1]; reg2 2643 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_ALT_ADDR2(index), reg2); reg2 2647 drivers/net/ethernet/sun/niu.c nw64_mac(BMAC_ALT_ADDR2(index), reg2); reg2 159 drivers/net/phy/adin.c u16 reg2; reg2 664 drivers/net/phy/adin.c if (stat->reg2 == 0) reg2 667 drivers/net/phy/adin.c ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg2); reg2 1024 drivers/net/wireless/ralink/rt2x00/rt2400pci.c u32 reg, reg2; reg2 1045 drivers/net/wireless/ralink/rt2x00/rt2400pci.c reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); reg2 1046 drivers/net/wireless/ralink/rt2x00/rt2400pci.c bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE); reg2 1047 drivers/net/wireless/ralink/rt2x00/rt2400pci.c rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE); reg2 1177 drivers/net/wireless/ralink/rt2x00/rt2500pci.c u32 reg, reg2; reg2 1198 drivers/net/wireless/ralink/rt2x00/rt2500pci.c reg2 = rt2x00mmio_register_read(rt2x00dev, PWRCSR1); reg2 1199 drivers/net/wireless/ralink/rt2x00/rt2500pci.c bbp_state = rt2x00_get_field32(reg2, PWRCSR1_BBP_CURR_STATE); reg2 1200 drivers/net/wireless/ralink/rt2x00/rt2500pci.c rf_state = rt2x00_get_field32(reg2, PWRCSR1_RF_CURR_STATE); reg2 985 drivers/net/wireless/ralink/rt2x00/rt2500usb.c u16 reg2; reg2 1007 drivers/net/wireless/ralink/rt2x00/rt2500usb.c reg2 = rt2500usb_register_read(rt2x00dev, MAC_CSR17); reg2 1008 drivers/net/wireless/ralink/rt2x00/rt2500usb.c bbp_state = rt2x00_get_field16(reg2, MAC_CSR17_BBP_CURR_STATE); reg2 1009 drivers/net/wireless/ralink/rt2x00/rt2500usb.c rf_state = rt2x00_get_field16(reg2, MAC_CSR17_RF_CURR_STATE); reg2 1710 drivers/net/wireless/ralink/rt2x00/rt61pci.c u32 reg, reg2; reg2 1727 drivers/net/wireless/ralink/rt2x00/rt61pci.c reg2 = rt2x00mmio_register_read(rt2x00dev, MAC_CSR12); reg2 1728 drivers/net/wireless/ralink/rt2x00/rt61pci.c state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); reg2 1379 drivers/net/wireless/ralink/rt2x00/rt73usb.c u32 reg, reg2; reg2 1396 drivers/net/wireless/ralink/rt2x00/rt73usb.c reg2 = rt2x00usb_register_read(rt2x00dev, MAC_CSR12); reg2 1397 drivers/net/wireless/ralink/rt2x00/rt73usb.c state = rt2x00_get_field32(reg2, MAC_CSR12_BBP_CURRENT_STATE); reg2 900 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c .fn2 = fn_ ## h, .reg2 = NPCM7XX_GCR_ ## i, .bit2 = j, \ reg2 922 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int fn2, reg2, bit2; reg2 1431 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c if (cfg->reg2) reg2 1432 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c regmap_update_bits(gcr_regmap, cfg->reg2, reg2 1390 drivers/pinctrl/pinctrl-ingenic.c u8 reg1, reg2; reg2 1394 drivers/pinctrl/pinctrl-ingenic.c reg2 = JZ4760_GPIO_PAT0; reg2 1397 drivers/pinctrl/pinctrl-ingenic.c reg2 = JZ4740_GPIO_DIR; reg2 1403 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); reg2 1407 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_set_bit(jzgc, reg2, offset, true); reg2 1413 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); reg2 1417 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_set_bit(jzgc, reg2, offset, false); reg2 1423 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, true); reg2 1427 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_set_bit(jzgc, reg2, offset, true); reg2 1434 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_shadow_set_bit(jzgc, reg2, offset, false); reg2 1438 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_set_bit(jzgc, reg2, offset, false); reg2 260 drivers/power/supply/wm831x_power.c int ret, reg1, reg2; reg2 271 drivers/power/supply/wm831x_power.c reg2 = 0; reg2 280 drivers/power/supply/wm831x_power.c reg2 |= WM831X_CHG_OFF_MSK; reg2 286 drivers/power/supply/wm831x_power.c pdata->trickle_ilim, ®2, reg2 290 drivers/power/supply/wm831x_power.c pdata->vsel, ®2, reg2 294 drivers/power/supply/wm831x_power.c pdata->fast_ilim, ®2, reg2 302 drivers/power/supply/wm831x_power.c pdata->timeout, ®2, reg2 326 drivers/power/supply/wm831x_power.c reg2); reg2 893 drivers/regulator/helpers.c bool regulator_is_equal(struct regulator *reg1, struct regulator *reg2) reg2 895 drivers/regulator/helpers.c return reg1->rdev == reg2->rdev; reg2 26 drivers/rtc/rtc-aspeed.c u32 reg1, reg2; reg2 34 drivers/rtc/rtc-aspeed.c reg2 = readl(rtc->base + RTC_YEAR); reg2 36 drivers/rtc/rtc-aspeed.c } while (reg2 != readl(rtc->base + RTC_YEAR)); reg2 43 drivers/rtc/rtc-aspeed.c cent = (reg2 >> 16) & 0x1f; reg2 44 drivers/rtc/rtc-aspeed.c year = (reg2 >> 8) & 0x7f; reg2 45 drivers/rtc/rtc-aspeed.c tm->tm_mon = ((reg2 >> 0) & 0x0f) - 1; reg2 56 drivers/rtc/rtc-aspeed.c u32 reg1, reg2, ctrl; reg2 65 drivers/rtc/rtc-aspeed.c reg2 = ((cent & 0x1f) << 16) | ((year & 0x7f) << 8) | reg2 72 drivers/rtc/rtc-aspeed.c writel(reg2, rtc->base + RTC_YEAR); reg2 72 drivers/s390/block/dasd_diag.c register unsigned long reg2 asm ("2") = (unsigned long) iob; reg2 88 drivers/s390/block/dasd_diag.c : "d" (cmd), "d" (reg2), "m" (*(addr_type *) iob) reg2 199 drivers/scsi/NCR5380.c unsigned int reg2, u8 bit2, u8 val2, reg2 208 drivers/scsi/NCR5380.c if ((NCR5380_read(reg2) & bit2) == val2) reg2 221 drivers/scsi/NCR5380.c if ((NCR5380_read(reg2) & bit2) == val2) reg2 83 drivers/staging/rts5208/rtsx_card.c u8 reg1 = 0, reg2 = 0; reg2 86 drivers/staging/rts5208/rtsx_card.c rtsx_read_register(chip, 0xFF38, ®2); reg2 88 drivers/staging/rts5208/rtsx_card.c reg1, reg2); reg2 89 drivers/staging/rts5208/rtsx_card.c if ((reg1 & 0xC0) && (reg2 & 0xC0)) { reg2 670 drivers/thermal/ti-soc-thermal/ti-bandgap.c u32 temp1, temp2, reg1, reg2; reg2 690 drivers/thermal/ti-soc-thermal/ti-bandgap.c reg2 = tsr->ctrl_dtemp_2; reg2 696 drivers/thermal/ti-soc-thermal/ti-bandgap.c temp2 = ti_bandgap_readl(bgp, reg2); reg2 403 drivers/video/fbdev/i810/i810_main.c u16 reg2; reg2 406 drivers/video/fbdev/i810/i810_main.c reg2 = i810_readw(BLTCNTL, mmio) & ~0x30; reg2 409 drivers/video/fbdev/i810/i810_main.c reg2 |= par->bltcntl; reg2 411 drivers/video/fbdev/i810/i810_main.c i810_writew(BLTCNTL, mmio, reg2); reg2 7664 drivers/video/fbdev/sis/init301.c unsigned short vclkindex, temp, reg1, reg2; reg2 7668 drivers/video/fbdev/sis/init301.c reg2 = SiS_Pr->CSR2C; reg2 7672 drivers/video/fbdev/sis/init301.c reg2 = SiS_Pr->SiS_VBVCLKData[vclkindex].Part4_B; reg2 7682 drivers/video/fbdev/sis/init301.c SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0b,reg2); reg2 7686 drivers/video/fbdev/sis/init301.c SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0b,reg2); reg2 852 drivers/video/fbdev/sis/sis_main.c u8 idx, reg1, reg2, reg3, reg4; reg2 870 drivers/video/fbdev/sis/sis_main.c reg2 = SiS_GetReg(SISPART1, (idx+1)); /* 31 */ reg2 877 drivers/video/fbdev/sis/sis_main.c (*hcount) = reg2 | ((reg4 & 0x0f) << 8); reg2 890 drivers/video/fbdev/sis/sis_main.c reg2 = SiS_GetReg(SISCR, 0x1c); reg2 892 drivers/video/fbdev/sis/sis_main.c (*vcount) = reg2 | ((reg3 & 0x07) << 8); reg2 205 include/linux/qed/fcoe_common.h __le32 reg2; reg2 407 include/linux/qed/fcoe_common.h __le32 reg2; reg2 1370 include/linux/qed/iscsi_common.h __le32 reg2; reg2 1552 include/linux/qed/iscsi_common.h __le32 reg2; reg2 290 include/linux/regulator/consumer.h bool regulator_is_equal(struct regulator *reg1, struct regulator *reg2); reg2 599 include/linux/regulator/consumer.h regulator_is_equal(struct regulator *reg1, struct regulator *reg2) reg2 328 include/sound/sb.h #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \ reg2 329 include/sound/sb.h ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24)) reg2 350 include/sound/sb.h #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \ reg2 353 include/sound/sb.h .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) } reg2 654 include/sound/soc-dapm.h int reg2; reg2 389 sound/isa/sb/sb_mixer.c int reg2 = (kcontrol->private_value >> 8) & 0xff; reg2 396 sound/isa/sb/sb_mixer.c val2 = snd_sbmixer_read(sb, reg2); reg2 410 sound/isa/sb/sb_mixer.c int reg2 = (kcontrol->private_value >> 8) & 0xff; reg2 418 sound/isa/sb/sb_mixer.c oval2 = snd_sbmixer_read(sb, reg2); reg2 428 sound/isa/sb/sb_mixer.c snd_sbmixer_write(sb, reg2, val2); reg2 198 sound/pci/ak4531_codec.c #define AK4531_INPUT_SW(xname, xindex, reg1, reg2, left_shift, right_shift) \ reg2 202 sound/pci/ak4531_codec.c .private_value = reg1 | (reg2 << 8) | (left_shift << 16) | (right_shift << 24) } reg2 217 sound/pci/ak4531_codec.c int reg2 = (kcontrol->private_value >> 8) & 0xff; reg2 223 sound/pci/ak4531_codec.c ucontrol->value.integer.value[1] = (ak4531->regs[reg2] >> left_shift) & 1; reg2 225 sound/pci/ak4531_codec.c ucontrol->value.integer.value[3] = (ak4531->regs[reg2] >> right_shift) & 1; reg2 234 sound/pci/ak4531_codec.c int reg2 = (kcontrol->private_value >> 8) & 0xff; reg2 242 sound/pci/ak4531_codec.c val2 = ak4531->regs[reg2] & ~((1 << left_shift) | (1 << right_shift)); reg2 247 sound/pci/ak4531_codec.c change = val1 != ak4531->regs[reg1] || val2 != ak4531->regs[reg2]; reg2 249 sound/pci/ak4531_codec.c ak4531->write(ak4531, reg2, ak4531->regs[reg2] = val2); reg2 35 sound/pci/ice1712/wm8766.c .reg2 = WM8766_REG_DACR1, reg2 46 sound/pci/ice1712/wm8766.c .reg2 = WM8766_REG_DACR2, reg2 57 sound/pci/ice1712/wm8766.c .reg2 = WM8766_REG_DACR3, reg2 218 sound/pci/ice1712/wm8766.c val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; reg2 257 sound/pci/ice1712/wm8766.c wm->ctl[n].reg1 == wm->ctl[n].reg2) { reg2 264 sound/pci/ice1712/wm8766.c wm->ctl[n].reg1 != wm->ctl[n].reg2) { reg2 265 sound/pci/ice1712/wm8766.c val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; reg2 269 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, wm->ctl[n].reg2, val); reg2 124 sound/pci/ice1712/wm8766.h u16 reg1, reg2, mask1, mask2, min, max, flags; reg2 138 sound/pci/ice1712/wm8776.c .reg2 = WM8776_REG_DACRVOL, reg2 148 sound/pci/ice1712/wm8776.c .reg2 = WM8776_REG_DACCTRL1, reg2 164 sound/pci/ice1712/wm8776.c .reg2 = WM8776_REG_HPRVOL, reg2 182 sound/pci/ice1712/wm8776.c .reg2 = WM8776_REG_HPRVOL, reg2 209 sound/pci/ice1712/wm8776.c .reg2 = WM8776_REG_PHASESWAP, reg2 225 sound/pci/ice1712/wm8776.c .reg2 = WM8776_REG_ADCRVOL, reg2 235 sound/pci/ice1712/wm8776.c .reg2 = WM8776_REG_ADCMUX, reg2 492 sound/pci/ice1712/wm8776.c val2 = wm->regs[wm->ctl[n].reg2] & wm->ctl[n].mask2; reg2 531 sound/pci/ice1712/wm8776.c wm->ctl[n].reg1 == wm->ctl[n].reg2) { reg2 538 sound/pci/ice1712/wm8776.c wm->ctl[n].reg1 != wm->ctl[n].reg2) { reg2 539 sound/pci/ice1712/wm8776.c val = wm->regs[wm->ctl[n].reg2] & ~wm->ctl[n].mask2; reg2 543 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, wm->ctl[n].reg2, val); reg2 180 sound/pci/ice1712/wm8776.h u16 reg1, reg2, mask1, mask2, min, max, flags; reg2 1561 sound/pci/ymfpci/ymfpci_main.c unsigned int reg2 = YDSXGR_BUF441OUTVOL; reg2 1571 sound/pci/ymfpci/ymfpci_main.c snd_ymfpci_writel(chip, reg2, value); reg2 274 sound/soc/codecs/88pm860x-codec.c unsigned int reg2 = mc->rreg; reg2 279 sound/soc/codecs/88pm860x-codec.c val2[0] = snd_soc_component_read32(component, reg2) & 0x3f; reg2 298 sound/soc/codecs/88pm860x-codec.c unsigned int reg2 = mc->rreg; reg2 316 sound/soc/codecs/88pm860x-codec.c err = snd_soc_component_update_bits(component, reg2, 0x3f, st_table[val2].m); reg2 331 sound/soc/codecs/88pm860x-codec.c unsigned int reg2 = mc->rreg; reg2 337 sound/soc/codecs/88pm860x-codec.c val2 = snd_soc_component_read32(component, reg2) >> shift; reg2 351 sound/soc/codecs/88pm860x-codec.c unsigned int reg2 = mc->rreg; reg2 369 sound/soc/codecs/88pm860x-codec.c err = snd_soc_component_update_bits(component, reg2, val_mask, val2); reg2 691 sound/soc/codecs/cx2072x.c union cx2072x_reg_i2spcm_ctrl_reg2 reg2; reg2 716 sound/soc/codecs/cx2072x.c reg2.r.tx_master = 1; reg2 722 sound/soc/codecs/cx2072x.c reg2.r.tx_master = 0; reg2 802 sound/soc/codecs/cx2072x.c reg2.r.tx_endian_sel = !is_big_endian; reg2 803 sound/soc/codecs/cx2072x.c reg2.r.tx_dstart_dly = has_one_bit_delay; reg2 805 sound/soc/codecs/cx2072x.c reg2.r.tx_dstart_dly = 0; reg2 813 sound/soc/codecs/cx2072x.c reg2.r.tx_slot_1 = 0; reg2 814 sound/soc/codecs/cx2072x.c reg2.r.tx_slot_2 = i2s_right_slot; reg2 840 sound/soc/codecs/cx2072x.c if (reg2.r.tx_master) { reg2 855 sound/soc/codecs/cx2072x.c reg2.ulval); reg2 891 sound/soc/codecs/twl4030.c unsigned int reg2 = mc->rreg; reg2 899 sound/soc/codecs/twl4030.c (twl4030_read(component, reg2) >> shift) & mask; reg2 918 sound/soc/codecs/twl4030.c unsigned int reg2 = mc->rreg; reg2 941 sound/soc/codecs/twl4030.c err = snd_soc_component_update_bits(component, reg2, val_mask, val2); reg2 264 sound/soc/codecs/wm8580.c unsigned int reg2 = mc->rreg; reg2 270 sound/soc/codecs/wm8580.c regmap_update_bits(wm8580->regmap, reg2, 0x100, 0x000); reg2 279 sound/soc/codecs/wm8580.c snd_soc_component_update_bits(component, reg2, 0x100, 0x100); reg2 361 sound/soc/codecs/wm9081.c unsigned int reg2 = snd_soc_component_read32(component, WM9081_ANALOGUE_SPEAKER_2); reg2 365 sound/soc/codecs/wm9081.c ((reg2 & WM9081_SPK_MODE) != 0)) reg2 374 sound/soc/codecs/wm9081.c reg2 &= ~(WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL); reg2 375 sound/soc/codecs/wm9081.c reg2 |= WM9081_SPK_MODE; reg2 378 sound/soc/codecs/wm9081.c reg2 |= WM9081_SPK_INV_MUTE | WM9081_OUT_SPK_CTRL; reg2 379 sound/soc/codecs/wm9081.c reg2 &= ~WM9081_SPK_MODE; reg2 382 sound/soc/codecs/wm9081.c snd_soc_component_write(component, WM9081_ANALOGUE_SPEAKER_2, reg2); reg2 818 sound/soc/codecs/wm9713.c u16 reg, reg2; reg2 838 sound/soc/codecs/wm9713.c reg2 = (pll_div.n << 12) | (pll_div.lf << 11) | (1 << 10) | reg2 842 sound/soc/codecs/wm9713.c reg = reg2 | (0x5 << 4) | (pll_div.k >> 20); reg2 846 sound/soc/codecs/wm9713.c reg = reg2 | (0x4 << 4) | ((pll_div.k >> 16) & 0xf); reg2 850 sound/soc/codecs/wm9713.c reg = reg2 | (0x3 << 4) | ((pll_div.k >> 12) & 0xf); reg2 854 sound/soc/codecs/wm9713.c reg = reg2 | (0x2 << 4) | ((pll_div.k >> 8) & 0xf); reg2 858 sound/soc/codecs/wm9713.c reg = reg2 | (0x1 << 4) | ((pll_div.k >> 4) & 0xf); reg2 861 sound/soc/codecs/wm9713.c reg = reg2 | (0x0 << 4) | (pll_div.k & 0xf); /* K [3:0] */ reg2 1768 sound/soc/soc-dapm.c ret = soc_dapm_update_bits(w->dapm, update->reg2, reg2 3396 sound/soc/soc-dapm.c update.reg2 = mc->rreg; reg2 249 sound/soc/soc-ops.c unsigned int reg2 = mc->rreg; reg2 273 sound/soc/soc-ops.c if (reg == reg2) reg2 277 sound/soc/soc-ops.c ret = snd_soc_read_signed(component, reg2, mask, shift, reg2 309 sound/soc/soc-ops.c unsigned int reg2 = mc->rreg; reg2 334 sound/soc/soc-ops.c if (reg == reg2) { reg2 347 sound/soc/soc-ops.c err = snd_soc_component_update_bits(component, reg2, val_mask, reg2 371 sound/soc/soc-ops.c unsigned int reg2 = mc->rreg; reg2 387 sound/soc/soc-ops.c ret = snd_soc_component_read(component, reg2, &val); reg2 416 sound/soc/soc-ops.c unsigned int reg2 = mc->rreg; reg2 438 sound/soc/soc-ops.c err = snd_soc_component_update_bits(component, reg2, val_mask, reg2 1645 sound/sparc/dbri.c u32 reg2 = sbus_readl(dbri->regs + REG2); reg2 1646 sound/sparc/dbri.c dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2); reg2 1649 sound/sparc/dbri.c if (reg2 & D_PIO2) { reg2 1653 sound/sparc/dbri.c if (reg2 & D_PIO0) { reg2 1657 sound/sparc/dbri.c if (reg2 & D_PIO2) { reg2 1664 sound/sparc/dbri.c if (!(reg2 & (D_PIO0 | D_PIO2))) {