reg1 238 arch/arm/probes/kprobes/test-core.h #define TEST_RR(code1, reg1, val1, code2, reg2, val2, code3) \ reg1 239 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg1 240 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg1, val1) \ reg1 243 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \ reg1 246 arch/arm/probes/kprobes/test-core.h #define TEST_RRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ reg1 247 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg1 248 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg1, val1) \ reg1 252 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg1 255 arch/arm/probes/kprobes/test-core.h #define TEST_RRRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4, reg4, val4) \ reg1 256 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \ reg1 257 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg1, val1) \ reg1 262 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4 #reg4) \ reg1 265 arch/arm/probes/kprobes/test-core.h #define TEST_P(code1, reg1, val1, code2) \ reg1 266 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2) \ reg1 267 arch/arm/probes/kprobes/test-core.h TEST_ARG_PTR(reg1, val1) \ reg1 269 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2) \ reg1 272 arch/arm/probes/kprobes/test-core.h #define TEST_PR(code1, reg1, val1, code2, reg2, val2, code3) \ reg1 273 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg1 274 arch/arm/probes/kprobes/test-core.h TEST_ARG_PTR(reg1, val1) \ reg1 277 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \ reg1 280 arch/arm/probes/kprobes/test-core.h #define TEST_RP(code1, reg1, val1, code2, reg2, val2, code3) \ reg1 281 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg1 282 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg1, val1) \ reg1 285 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3) \ reg1 288 arch/arm/probes/kprobes/test-core.h #define TEST_PRR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ reg1 289 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg1 290 arch/arm/probes/kprobes/test-core.h TEST_ARG_PTR(reg1, val1) \ reg1 294 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg1 297 arch/arm/probes/kprobes/test-core.h #define TEST_RPR(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ reg1 298 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg1 299 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg1, val1) \ reg1 303 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg1 306 arch/arm/probes/kprobes/test-core.h #define TEST_RRP(code1, reg1, val1, code2, reg2, val2, code3, reg3, val3, code4)\ reg1 307 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg1 308 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg1, val1) \ reg1 312 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 #reg1 code2 #reg2 code3 #reg3 code4) \ reg1 315 arch/arm/probes/kprobes/test-core.h #define TEST_BF_P(code1, reg1, val1, code2) \ reg1 316 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2) \ reg1 317 arch/arm/probes/kprobes/test-core.h TEST_ARG_PTR(reg1, val1) \ reg1 319 arch/arm/probes/kprobes/test-core.h TEST_BRANCH_F(code1 #reg1 code2) \ reg1 348 arch/arm/probes/kprobes/test-core.h #define TEST_BF_RR(code1, reg1, val1, code2, reg2, val2, code3) \ reg1 349 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg1 350 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg1, val1) \ reg1 353 arch/arm/probes/kprobes/test-core.h TEST_BRANCH_F(code1 #reg1 code2 #reg2 code3) \ reg1 392 arch/arm/probes/kprobes/test-core.h #define TEST_RRX(code1, reg1, val1, code2, reg2, val2, code3, codex) \ reg1 393 arch/arm/probes/kprobes/test-core.h TESTCASE_START(code1 #reg1 code2 #reg2 code3) \ reg1 394 arch/arm/probes/kprobes/test-core.h TEST_ARG_REG(reg1, val1) \ reg1 397 arch/arm/probes/kprobes/test-core.h TEST_INSTRUCTION(code1 __stringify(reg1) code2 __stringify(reg2) code3) \ reg1 233 arch/arm64/include/asm/alternative.h .macro uao_ldp l, reg1, reg2, addr, post_inc reg1 248 arch/arm64/include/asm/alternative.h .macro uao_stp l, reg1, reg2, addr, post_inc reg1 275 arch/arm64/include/asm/alternative.h .macro uao_ldp l, reg1, reg2, addr, post_inc reg1 278 arch/arm64/include/asm/alternative.h .macro uao_stp l, reg1, reg2, addr, post_inc reg1 646 arch/arm64/include/asm/assembler.h .macro __frame_regs, reg1, reg2, op, num reg1 382 arch/arm64/include/asm/insn.h u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1, reg1 433 arch/arm64/include/asm/insn.h enum aarch64_insn_register reg1, reg1 26 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_save_state base, reg1, reg2 reg1 44 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_restore_state base, reg1, reg2 reg1 69 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_switch_to_guest g_ctxt, reg1, reg2, reg3 reg1 85 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_switch_to_host g_ctxt, h_ctxt, reg1, reg2, reg3 reg1 105 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_switch_to_guest g_ctxt, reg1, reg2, reg3 reg1 107 arch/arm64/include/asm/kvm_ptrauth.h .macro ptrauth_switch_to_host g_ctxt, h_ctxt, reg1, reg2, reg3 reg1 627 arch/arm64/kernel/insn.c u32 aarch64_insn_gen_load_store_pair(enum aarch64_insn_register reg1, reg1 679 arch/arm64/kernel/insn.c reg1); reg1 1160 arch/arm64/kernel/insn.c enum aarch64_insn_register reg1, reg1 1195 arch/arm64/kernel/insn.c reg1); reg1 72 arch/ia64/include/asm/native/inst.h #define THASH(pred, reg0, reg1, clob) \ reg1 73 arch/ia64/include/asm/native/inst.h (pred) thash reg0 = reg1 reg1 195 arch/mips/include/asm/octeon/cvmx-pko.h uint64_t reg1:11; reg1 258 arch/mips/include/asm/octeon/cvmx-pko.h uint64_t reg1:11; reg1 321 arch/mips/include/asm/uasm.h void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, reg1 105 arch/mips/mm/page.c pg_addiu(u32 **buf, unsigned int reg1, unsigned int reg2, unsigned int off) reg1 113 arch/mips/mm/page.c uasm_i_daddu(buf, reg1, reg2, T9); reg1 118 arch/mips/mm/page.c UASM_i_ADDU(buf, reg1, reg2, T9); reg1 120 arch/mips/mm/page.c UASM_i_ADDIU(buf, reg1, reg2, off); reg1 597 arch/mips/mm/uasm.c void uasm_il_bne(u32 **p, struct uasm_reloc **r, unsigned int reg1, reg1 601 arch/mips/mm/uasm.c uasm_i_bne(p, reg1, reg2, 0); reg1 19 arch/nios2/include/asm/asm-macros.h .macro ANDI32 reg1, reg2, mask reg1 39 arch/nios2/include/asm/asm-macros.h .macro ORI32 reg1, reg2, mask reg1 58 arch/nios2/include/asm/asm-macros.h .macro XORI32 reg1, reg2, mask reg1 78 arch/nios2/include/asm/asm-macros.h .macro BT reg1, reg2, bit reg1 97 arch/nios2/include/asm/asm-macros.h .macro BTBZ reg1, reg2, bit, label reg1 109 arch/nios2/include/asm/asm-macros.h .macro BTBNZ reg1, reg2, bit, label reg1 121 arch/nios2/include/asm/asm-macros.h .macro BTC reg1, reg2, bit reg1 142 arch/nios2/include/asm/asm-macros.h .macro BTS reg1, reg2, bit reg1 163 arch/nios2/include/asm/asm-macros.h .macro BTR reg1, reg2, bit reg1 185 arch/nios2/include/asm/asm-macros.h .macro BTCBZ reg1, reg2, bit, label reg1 198 arch/nios2/include/asm/asm-macros.h .macro BTCBNZ reg1, reg2, bit, label reg1 211 arch/nios2/include/asm/asm-macros.h .macro BTSBZ reg1, reg2, bit, label reg1 224 arch/nios2/include/asm/asm-macros.h .macro BTSBNZ reg1, reg2, bit, label reg1 237 arch/nios2/include/asm/asm-macros.h .macro BTRBZ reg1, reg2, bit, label reg1 250 arch/nios2/include/asm/asm-macros.h .macro BTRBNZ reg1, reg2, bit, label reg1 262 arch/nios2/include/asm/asm-macros.h .macro TSTBZ reg1, reg2, mask, label reg1 274 arch/nios2/include/asm/asm-macros.h .macro TSTBNZ reg1, reg2, mask, label reg1 29 arch/s390/boot/ipl_parm.c unsigned long reg1, reg2; reg1 40 arch/s390/boot/ipl_parm.c : "=&d" (reg1), "=&a" (reg2), reg1 72 arch/s390/boot/mem_detect.c unsigned long reg1, reg2; reg1 85 arch/s390/boot/mem_detect.c : "=&d" (reg1), "=&a" (reg2), reg1 57 arch/s390/include/asm/ap.h register unsigned long reg1 asm ("1") = 0; reg1 65 arch/s390/include/asm/ap.h : "+d" (reg1), "+d" (reg2) reg1 68 arch/s390/include/asm/ap.h return reg1 != 0; reg1 81 arch/s390/include/asm/ap.h register struct ap_queue_status reg1 asm ("1"); reg1 85 arch/s390/include/asm/ap.h : "=d" (reg1), "=d" (reg2) reg1 90 arch/s390/include/asm/ap.h return reg1; reg1 119 arch/s390/include/asm/ap.h register struct ap_queue_status reg1 asm ("1"); reg1 123 arch/s390/include/asm/ap.h : "=d" (reg1) reg1 126 arch/s390/include/asm/ap.h return reg1; reg1 138 arch/s390/include/asm/ap.h register struct ap_queue_status reg1 asm ("1"); reg1 142 arch/s390/include/asm/ap.h : "=d" (reg1) reg1 145 arch/s390/include/asm/ap.h return reg1; reg1 176 arch/s390/include/asm/ap.h register unsigned long reg1 asm ("1") = -EOPNOTSUPP; reg1 184 arch/s390/include/asm/ap.h : "+d" (reg1) reg1 188 arch/s390/include/asm/ap.h return reg1; reg1 228 arch/s390/include/asm/ap.h } reg1 asm ("1"); reg1 231 arch/s390/include/asm/ap.h reg1.qirqctrl = qirqctrl; reg1 235 arch/s390/include/asm/ap.h : "+d" (reg1) reg1 239 arch/s390/include/asm/ap.h return reg1.status; reg1 276 arch/s390/include/asm/ap.h } reg1 asm ("1"); reg1 279 arch/s390/include/asm/ap.h reg1.value = apinfo->val; reg1 283 arch/s390/include/asm/ap.h : "+d" (reg1), "=d" (reg2) reg1 287 arch/s390/include/asm/ap.h return reg1.status; reg1 307 arch/s390/include/asm/ap.h register struct ap_queue_status reg1 asm ("1"); reg1 316 arch/s390/include/asm/ap.h : "+d" (reg0), "=d" (reg1), "+d" (reg2), "+d" (reg3) reg1 319 arch/s390/include/asm/ap.h return reg1; reg1 345 arch/s390/include/asm/ap.h register struct ap_queue_status reg1 asm ("1"); reg1 356 arch/s390/include/asm/ap.h : "+d" (reg0), "=d" (reg1), "+d" (reg2), reg1 360 arch/s390/include/asm/ap.h return reg1; reg1 277 arch/s390/include/asm/processor.h unsigned int reg1, reg2; reg1 279 arch/s390/include/asm/processor.h asm volatile("epsw %0,%1" : "=d" (reg1), "=a" (reg2)); reg1 280 arch/s390/include/asm/processor.h return (((unsigned long) reg1) << 32) | ((unsigned long) reg2); reg1 44 arch/s390/include/asm/sigp.h register unsigned long reg1 asm ("1") = parm; reg1 51 arch/s390/include/asm/sigp.h : "=d" (cc), "+d" (reg1) : "d" (addr), "a" (order) : "cc"); reg1 52 arch/s390/include/asm/sigp.h *status = reg1; reg1 116 arch/s390/include/asm/timex.h register unsigned long reg1 asm("1") = (unsigned long) (ptff_block);\ reg1 123 arch/s390/include/asm/timex.h : "=d" (rc), "+m" (*(struct addrtype *) reg1) \ reg1 124 arch/s390/include/asm/timex.h : "d" (reg0), "d" (reg1) : "cc"); \ reg1 317 arch/s390/kvm/intercept.c int reg1, reg2, rc; reg1 319 arch/s390/kvm/intercept.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg1 331 arch/s390/kvm/intercept.c rc = guest_translate_address(vcpu, vcpu->run->s.regs.gprs[reg1], reg1 332 arch/s390/kvm/intercept.c reg1, &dstaddr, GACC_STORE); reg1 363 arch/s390/kvm/intercept.c int reg1, reg2, r = 0; reg1 370 arch/s390/kvm/intercept.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg1 371 arch/s390/kvm/intercept.c code = vcpu->run->s.regs.gprs[reg1]; reg1 378 arch/s390/kvm/intercept.c if (reg1 == reg2 || reg1 & 1 || reg2 & 1) reg1 250 arch/s390/kvm/priv.c int reg1, reg2; reg1 263 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg1 289 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg1] &= ~0xff; reg1 290 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg1] |= key; reg1 297 arch/s390/kvm/priv.c int reg1, reg2; reg1 310 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg1 348 arch/s390/kvm/priv.c int reg1, reg2; reg1 368 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg1 370 arch/s390/kvm/priv.c key = vcpu->run->s.regs.gprs[reg1] & 0xfe; reg1 412 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg1] &= ~0xff00UL; reg1 413 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg1] |= (u64) oldkey << 8; reg1 980 arch/s390/kvm/priv.c int reg1, reg2; reg1 984 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg1 987 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg1] &= 0xffffffff00000000UL; reg1 988 arch/s390/kvm/priv.c vcpu->run->s.regs.gprs[reg1] |= vcpu->arch.sie_block->gpsw.mask >> 32; reg1 1010 arch/s390/kvm/priv.c int reg1, reg2; reg1 1016 arch/s390/kvm/priv.c kvm_s390_get_regs_rre(vcpu, ®1, ®2); reg1 1024 arch/s390/kvm/priv.c if (vcpu->run->s.regs.gprs[reg1] & PFMF_RESERVED) reg1 1028 arch/s390/kvm/priv.c if (vcpu->run->s.regs.gprs[reg1] & PFMF_NQ && reg1 1033 arch/s390/kvm/priv.c if (vcpu->run->s.regs.gprs[reg1] & PFMF_SK && reg1 1035 arch/s390/kvm/priv.c mr = vcpu->run->s.regs.gprs[reg1] & PFMF_MR; reg1 1036 arch/s390/kvm/priv.c mc = vcpu->run->s.regs.gprs[reg1] & PFMF_MC; reg1 1039 arch/s390/kvm/priv.c nq = vcpu->run->s.regs.gprs[reg1] & PFMF_NQ; reg1 1040 arch/s390/kvm/priv.c key = vcpu->run->s.regs.gprs[reg1] & PFMF_KEY; reg1 1044 arch/s390/kvm/priv.c if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { reg1 1049 arch/s390/kvm/priv.c switch (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) { reg1 1079 arch/s390/kvm/priv.c if (vcpu->run->s.regs.gprs[reg1] & PFMF_CF) { reg1 1084 arch/s390/kvm/priv.c if (vcpu->run->s.regs.gprs[reg1] & PFMF_SK) { reg1 1107 arch/s390/kvm/priv.c if (vcpu->run->s.regs.gprs[reg1] & PFMF_FSC) { reg1 1276 arch/s390/kvm/priv.c int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; reg1 1293 arch/s390/kvm/priv.c VCPU_EVENT(vcpu, 4, "LCTL: r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); reg1 1294 arch/s390/kvm/priv.c trace_kvm_s390_handle_lctl(vcpu, 0, reg1, reg3, ga); reg1 1296 arch/s390/kvm/priv.c nr_regs = ((reg3 - reg1) & 0xf) + 1; reg1 1300 arch/s390/kvm/priv.c reg = reg1; reg1 1315 arch/s390/kvm/priv.c int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; reg1 1332 arch/s390/kvm/priv.c VCPU_EVENT(vcpu, 4, "STCTL r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); reg1 1333 arch/s390/kvm/priv.c trace_kvm_s390_handle_stctl(vcpu, 0, reg1, reg3, ga); reg1 1335 arch/s390/kvm/priv.c reg = reg1; reg1 1349 arch/s390/kvm/priv.c int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; reg1 1366 arch/s390/kvm/priv.c VCPU_EVENT(vcpu, 4, "LCTLG: r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); reg1 1367 arch/s390/kvm/priv.c trace_kvm_s390_handle_lctl(vcpu, 1, reg1, reg3, ga); reg1 1369 arch/s390/kvm/priv.c nr_regs = ((reg3 - reg1) & 0xf) + 1; reg1 1373 arch/s390/kvm/priv.c reg = reg1; reg1 1387 arch/s390/kvm/priv.c int reg1 = (vcpu->arch.sie_block->ipa & 0x00f0) >> 4; reg1 1404 arch/s390/kvm/priv.c VCPU_EVENT(vcpu, 4, "STCTG r1:%d, r3:%d, addr: 0x%llx", reg1, reg3, ga); reg1 1405 arch/s390/kvm/priv.c trace_kvm_s390_handle_stctl(vcpu, 1, reg1, reg3, ga); reg1 1407 arch/s390/kvm/priv.c reg = reg1; reg1 287 arch/s390/kvm/trace.h TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr), reg1 288 arch/s390/kvm/trace.h TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr), reg1 293 arch/s390/kvm/trace.h __field(int, reg1) reg1 301 arch/s390/kvm/trace.h __entry->reg1 = reg1; reg1 308 arch/s390/kvm/trace.h __entry->reg1, __entry->reg3, __entry->addr) reg1 312 arch/s390/kvm/trace.h TP_PROTO(VCPU_PROTO_COMMON, int g, int reg1, int reg3, u64 addr), reg1 313 arch/s390/kvm/trace.h TP_ARGS(VCPU_ARGS_COMMON, g, reg1, reg3, addr), reg1 318 arch/s390/kvm/trace.h __field(int, reg1) reg1 326 arch/s390/kvm/trace.h __entry->reg1 = reg1; reg1 333 arch/s390/kvm/trace.h __entry->reg1, __entry->reg3, __entry->addr) reg1 145 arch/x86/events/intel/uncore.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 155 arch/x86/events/intel/uncore.c if (reg1->idx == EXTRA_REG_NONE || reg1 156 arch/x86/events/intel/uncore.c (!uncore_box_is_fake(box) && reg1->alloc)) reg1 159 arch/x86/events/intel/uncore.c er = &box->shared_regs[reg1->idx]; reg1 162 arch/x86/events/intel/uncore.c (er->config1 == reg1->config && er->config2 == reg2->config)) { reg1 164 arch/x86/events/intel/uncore.c er->config1 = reg1->config; reg1 172 arch/x86/events/intel/uncore.c reg1->alloc = 1; reg1 182 arch/x86/events/intel/uncore.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 192 arch/x86/events/intel/uncore.c if (uncore_box_is_fake(box) || !reg1->alloc) reg1 195 arch/x86/events/intel/uncore.c er = &box->shared_regs[reg1->idx]; reg1 197 arch/x86/events/intel/uncore.c reg1->alloc = 0; reg1 353 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 368 arch/x86/events/intel/uncore_nhmex.c reg1->reg = NHMEX_B0_MSR_MATCH; reg1 370 arch/x86/events/intel/uncore_nhmex.c reg1->reg = NHMEX_B1_MSR_MATCH; reg1 371 arch/x86/events/intel/uncore_nhmex.c reg1->idx = 0; reg1 372 arch/x86/events/intel/uncore_nhmex.c reg1->config = event->attr.config1; reg1 380 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 383 arch/x86/events/intel/uncore_nhmex.c if (reg1->idx != EXTRA_REG_NONE) { reg1 384 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg, reg1->config); reg1 385 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 1, reg2->config); reg1 444 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 453 arch/x86/events/intel/uncore_nhmex.c reg1->reg = NHMEX_S0_MSR_MM_CFG; reg1 455 arch/x86/events/intel/uncore_nhmex.c reg1->reg = NHMEX_S1_MSR_MM_CFG; reg1 456 arch/x86/events/intel/uncore_nhmex.c reg1->idx = 0; reg1 457 arch/x86/events/intel/uncore_nhmex.c reg1->config = event->attr.config1; reg1 465 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 468 arch/x86/events/intel/uncore_nhmex.c if (reg1->idx != EXTRA_REG_NONE) { reg1 469 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg, 0); reg1 470 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 1, reg1->config); reg1 471 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg + 2, reg2->config); reg1 472 arch/x86/events/intel/uncore_nhmex.c wrmsrl(reg1->reg, NHMEX_S_PMON_MM_CFG_EN); reg1 632 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 633 arch/x86/events/intel/uncore_nhmex.c u64 idx, orig_idx = __BITS_VALUE(reg1->idx, 0, 8); reg1 634 arch/x86/events/intel/uncore_nhmex.c u64 config = reg1->config; reg1 652 arch/x86/events/intel/uncore_nhmex.c config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config; reg1 654 arch/x86/events/intel/uncore_nhmex.c config |= WSMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config; reg1 655 arch/x86/events/intel/uncore_nhmex.c config |= NHMEX_M_PMON_ZDP_CTL_FVC_MASK & reg1->config; reg1 662 arch/x86/events/intel/uncore_nhmex.c reg1->config = config; reg1 663 arch/x86/events/intel/uncore_nhmex.c reg1->idx = ~0xff | new_idx; reg1 671 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 674 arch/x86/events/intel/uncore_nhmex.c u64 config1 = reg1->config; reg1 676 arch/x86/events/intel/uncore_nhmex.c idx[0] = __BITS_VALUE(reg1->idx, 0, 8); reg1 677 arch/x86/events/intel/uncore_nhmex.c idx[1] = __BITS_VALUE(reg1->idx, 1, 8); reg1 680 arch/x86/events/intel/uncore_nhmex.c if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) reg1 705 arch/x86/events/intel/uncore_nhmex.c if (idx[0] != 0xff && idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) reg1 707 arch/x86/events/intel/uncore_nhmex.c reg1->alloc |= alloc; reg1 721 arch/x86/events/intel/uncore_nhmex.c BUG_ON(__BITS_VALUE(reg1->idx, 1, 8) != 0xff); reg1 725 arch/x86/events/intel/uncore_nhmex.c if (idx[0] != __BITS_VALUE(reg1->idx, 0, 8)) { reg1 740 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 746 arch/x86/events/intel/uncore_nhmex.c if (reg1->alloc & 0x1) reg1 747 arch/x86/events/intel/uncore_nhmex.c nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 0, 8)); reg1 748 arch/x86/events/intel/uncore_nhmex.c if (reg1->alloc & 0x2) reg1 749 arch/x86/events/intel/uncore_nhmex.c nhmex_mbox_put_shared_reg(box, __BITS_VALUE(reg1->idx, 1, 8)); reg1 750 arch/x86/events/intel/uncore_nhmex.c reg1->alloc = 0; reg1 768 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 794 arch/x86/events/intel/uncore_nhmex.c reg1->idx &= ~(0xff << (reg_idx * 8)); reg1 795 arch/x86/events/intel/uncore_nhmex.c reg1->reg &= ~(0xffff << (reg_idx * 16)); reg1 796 arch/x86/events/intel/uncore_nhmex.c reg1->idx |= nhmex_mbox_extra_reg_idx(er) << (reg_idx * 8); reg1 797 arch/x86/events/intel/uncore_nhmex.c reg1->reg |= msr << (reg_idx * 16); reg1 798 arch/x86/events/intel/uncore_nhmex.c reg1->config = event->attr.config1; reg1 838 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 842 arch/x86/events/intel/uncore_nhmex.c idx = __BITS_VALUE(reg1->idx, 0, 8); reg1 844 arch/x86/events/intel/uncore_nhmex.c wrmsrl(__BITS_VALUE(reg1->reg, 0, 16), reg1 846 arch/x86/events/intel/uncore_nhmex.c idx = __BITS_VALUE(reg1->idx, 1, 8); reg1 848 arch/x86/events/intel/uncore_nhmex.c wrmsrl(__BITS_VALUE(reg1->reg, 1, 16), reg1 947 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 950 arch/x86/events/intel/uncore_nhmex.c if (reg1->idx % 2) { reg1 951 arch/x86/events/intel/uncore_nhmex.c reg1->idx--; reg1 954 arch/x86/events/intel/uncore_nhmex.c reg1->idx++; reg1 959 arch/x86/events/intel/uncore_nhmex.c switch (reg1->idx % 6) { reg1 962 arch/x86/events/intel/uncore_nhmex.c reg1->config >>= 8; reg1 966 arch/x86/events/intel/uncore_nhmex.c reg1->config <<= 8; reg1 981 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 989 arch/x86/events/intel/uncore_nhmex.c if (!uncore_box_is_fake(box) && reg1->alloc) reg1 992 arch/x86/events/intel/uncore_nhmex.c idx = reg1->idx % 6; reg1 993 arch/x86/events/intel/uncore_nhmex.c config1 = reg1->config; reg1 999 arch/x86/events/intel/uncore_nhmex.c er_idx += (reg1->idx / 6) * 5; reg1 1004 arch/x86/events/intel/uncore_nhmex.c if (!atomic_read(&er->ref) || er->config == reg1->config) { reg1 1006 arch/x86/events/intel/uncore_nhmex.c er->config = reg1->config; reg1 1025 arch/x86/events/intel/uncore_nhmex.c er->config1 == reg1->config && reg1 1029 arch/x86/events/intel/uncore_nhmex.c er->config1 = reg1->config; reg1 1044 arch/x86/events/intel/uncore_nhmex.c if (idx != reg1->idx % 6) { reg1 1053 arch/x86/events/intel/uncore_nhmex.c if (idx != reg1->idx % 6) reg1 1055 arch/x86/events/intel/uncore_nhmex.c reg1->alloc = 1; reg1 1065 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 1068 arch/x86/events/intel/uncore_nhmex.c if (uncore_box_is_fake(box) || !reg1->alloc) reg1 1071 arch/x86/events/intel/uncore_nhmex.c idx = reg1->idx % 6; reg1 1075 arch/x86/events/intel/uncore_nhmex.c er_idx += (reg1->idx / 6) * 5; reg1 1083 arch/x86/events/intel/uncore_nhmex.c reg1->alloc = 0; reg1 1089 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 1098 arch/x86/events/intel/uncore_nhmex.c reg1->idx = idx; reg1 1099 arch/x86/events/intel/uncore_nhmex.c reg1->config = event->attr.config1; reg1 1114 arch/x86/events/intel/uncore_nhmex.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 1118 arch/x86/events/intel/uncore_nhmex.c idx = reg1->idx; reg1 1123 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG0(port), reg1->config); reg1 1126 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_IPERF_CFG1(port), reg1->config); reg1 1136 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET1_MATCH(port), reg1->config); reg1 1142 arch/x86/events/intel/uncore_nhmex.c wrmsrl(NHMEX_R_MSR_PORTN_XBR_SET2_MATCH(port), reg1->config); reg1 552 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 554 arch/x86/events/intel/uncore_snbep.c if (reg1->idx != EXTRA_REG_NONE) reg1 555 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, uncore_shared_reg_config(box, 0)); reg1 843 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 851 arch/x86/events/intel/uncore_snbep.c if (reg1->alloc & (0x1 << i)) reg1 854 arch/x86/events/intel/uncore_snbep.c reg1->alloc = 0; reg1 861 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 867 arch/x86/events/intel/uncore_snbep.c if (reg1->idx == EXTRA_REG_NONE) reg1 872 arch/x86/events/intel/uncore_snbep.c if (!(reg1->idx & (0x1 << i))) reg1 874 arch/x86/events/intel/uncore_snbep.c if (!uncore_box_is_fake(box) && (reg1->alloc & (0x1 << i))) reg1 879 arch/x86/events/intel/uncore_snbep.c !((reg1->config ^ er->config) & mask)) { reg1 882 arch/x86/events/intel/uncore_snbep.c er->config |= reg1->config & mask; reg1 893 arch/x86/events/intel/uncore_snbep.c reg1->alloc |= alloc; reg1 928 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 939 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + reg1 941 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & snbep_cbox_filter_mask(idx); reg1 942 arch/x86/events/intel/uncore_snbep.c reg1->idx = idx; reg1 973 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 974 arch/x86/events/intel/uncore_snbep.c u64 config = reg1->config; reg1 976 arch/x86/events/intel/uncore_snbep.c if (new_idx > reg1->idx) reg1 977 arch/x86/events/intel/uncore_snbep.c config <<= 8 * (new_idx - reg1->idx); reg1 979 arch/x86/events/intel/uncore_snbep.c config >>= 8 * (reg1->idx - new_idx); reg1 982 arch/x86/events/intel/uncore_snbep.c hwc->config += new_idx - reg1->idx; reg1 983 arch/x86/events/intel/uncore_snbep.c reg1->config = config; reg1 984 arch/x86/events/intel/uncore_snbep.c reg1->idx = new_idx; reg1 992 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 995 arch/x86/events/intel/uncore_snbep.c int idx = reg1->idx; reg1 996 arch/x86/events/intel/uncore_snbep.c u64 mask, config1 = reg1->config; reg1 999 arch/x86/events/intel/uncore_snbep.c if (reg1->idx == EXTRA_REG_NONE || reg1 1000 arch/x86/events/intel/uncore_snbep.c (!uncore_box_is_fake(box) && reg1->alloc)) reg1 1016 arch/x86/events/intel/uncore_snbep.c if (idx != reg1->idx) { reg1 1024 arch/x86/events/intel/uncore_snbep.c if (idx != reg1->idx) reg1 1026 arch/x86/events/intel/uncore_snbep.c reg1->alloc = 1; reg1 1033 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 1036 arch/x86/events/intel/uncore_snbep.c if (uncore_box_is_fake(box) || !reg1->alloc) reg1 1039 arch/x86/events/intel/uncore_snbep.c atomic_sub(1 << (reg1->idx * 8), &er->ref); reg1 1040 arch/x86/events/intel/uncore_snbep.c reg1->alloc = 0; reg1 1046 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 1050 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNBEP_PCU_MSR_PMON_BOX_FILTER; reg1 1051 arch/x86/events/intel/uncore_snbep.c reg1->idx = ev_sel - 0xb; reg1 1052 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & (0xff << (reg1->idx * 8)); reg1 1102 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 1106 arch/x86/events/intel/uncore_snbep.c reg1->idx = 0; reg1 1107 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNBEP_Q_Py_PCI_PMON_PKT_MATCH0; reg1 1108 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1; reg1 1119 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 1122 arch/x86/events/intel/uncore_snbep.c if (reg1->idx != EXTRA_REG_NONE) { reg1 1128 arch/x86/events/intel/uncore_snbep.c pci_write_config_dword(filter_pdev, reg1->reg, reg1 1129 arch/x86/events/intel/uncore_snbep.c (u32)reg1->config); reg1 1130 arch/x86/events/intel/uncore_snbep.c pci_write_config_dword(filter_pdev, reg1->reg + 4, reg1 1131 arch/x86/events/intel/uncore_snbep.c (u32)(reg1->config >> 32)); reg1 1612 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 1623 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNBEP_C0_MSR_PMON_BOX_FILTER + reg1 1625 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & ivbep_cbox_filter_mask(idx); reg1 1626 arch/x86/events/intel/uncore_snbep.c reg1->idx = idx; reg1 1634 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 1636 arch/x86/events/intel/uncore_snbep.c if (reg1->idx != EXTRA_REG_NONE) { reg1 1638 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, filter & 0xffffffff); reg1 1639 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg + 6, filter >> 32); reg1 2040 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 2051 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + reg1 2053 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & knl_cha_filter_mask(idx); reg1 2055 arch/x86/events/intel/uncore_snbep.c reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_REMOTE_NODE; reg1 2056 arch/x86/events/intel/uncore_snbep.c reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_LOCAL_NODE; reg1 2057 arch/x86/events/intel/uncore_snbep.c reg1->config |= KNL_CHA_MSR_PMON_BOX_FILTER_NNC; reg1 2058 arch/x86/events/intel/uncore_snbep.c reg1->idx = idx; reg1 2462 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 2463 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_U_MSR_PMON_FILTER; reg1 2464 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & HSWEP_U_MSR_PMON_BOX_FILTER_MASK; reg1 2465 arch/x86/events/intel/uncore_snbep.c reg1->idx = 0; reg1 2595 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 2606 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + reg1 2608 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & hswep_cbox_filter_mask(idx); reg1 2609 arch/x86/events/intel/uncore_snbep.c reg1->idx = idx; reg1 2618 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 2620 arch/x86/events/intel/uncore_snbep.c if (reg1->idx != EXTRA_REG_NONE) { reg1 2622 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, filter & 0xffffffff); reg1 2623 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg + 1, filter >> 32); reg1 2713 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 2717 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_PCU_MSR_PMON_BOX_FILTER; reg1 2718 arch/x86/events/intel/uncore_snbep.c reg1->idx = ev_sel - 0xb; reg1 2719 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & (0xff << reg1->idx); reg1 3488 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 3499 arch/x86/events/intel/uncore_snbep.c reg1->reg = HSWEP_C0_MSR_PMON_BOX_FILTER0 + reg1 3501 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & skx_cha_filter_mask(idx); reg1 3502 arch/x86/events/intel/uncore_snbep.c reg1->idx = idx; reg1 4069 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &event->hw.extra_reg; reg1 4071 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNR_C0_MSR_PMON_BOX_FILTER0 + reg1 4073 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & SKX_CHA_MSR_PMON_BOX_FILTER_TID; reg1 4074 arch/x86/events/intel/uncore_snbep.c reg1->idx = 0; reg1 4083 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 4085 arch/x86/events/intel/uncore_snbep.c if (reg1->idx != EXTRA_REG_NONE) reg1 4086 arch/x86/events/intel/uncore_snbep.c wrmsrl(reg1->reg, reg1->config); reg1 4178 arch/x86/events/intel/uncore_snbep.c struct hw_perf_event_extra *reg1 = &hwc->extra_reg; reg1 4182 arch/x86/events/intel/uncore_snbep.c reg1->reg = SNR_PCU_MSR_PMON_BOX_FILTER; reg1 4183 arch/x86/events/intel/uncore_snbep.c reg1->idx = ev_sel - 0xb; reg1 4184 arch/x86/events/intel/uncore_snbep.c reg1->config = event->attr.config1 & (0xff << reg1->idx); reg1 354 drivers/ata/pata_hpt366.c u32 reg1; reg1 368 drivers/ata/pata_hpt366.c pci_read_config_dword(dev, 0x40, ®1); reg1 372 drivers/ata/pata_hpt366.c switch ((reg1 & 0xf00) >> 8) { reg1 261 drivers/ata/pata_macio.c u32 reg1; /* Bits to set in first timing reg */ reg1 417 drivers/ata/pata_macio.c priv->treg[adev->devno][0] |= t->reg1; reg1 421 drivers/ata/pata_macio.c if (t == NULL || (t->reg1 == 0 && t->reg2 == 0)) { reg1 428 drivers/ata/pata_macio.c priv->treg[adev->devno][0] |= t->reg1; reg1 73 drivers/clk/mvebu/armada-37xx-periph.c void __iomem *reg1; reg1 149 drivers/clk/mvebu/armada-37xx-periph.c .reg1 = (void *)_reg1, \ reg1 340 drivers/clk/mvebu/armada-37xx-periph.c div = get_div(double_div->reg1, double_div->shift1); reg1 643 drivers/clk/mvebu/armada-37xx-periph.c rate->reg1 = reg + (u64)rate->reg1; reg1 1018 drivers/edac/amd64_edac.c int reg1 = DCSB1 + (cs * 4); reg1 1031 drivers/edac/amd64_edac.c cs, *base1, (pvt->fam == 0x10) ? reg1 reg1 1037 drivers/edac/amd64_edac.c int reg1 = DCSM1 + (cs * 4); reg1 1050 drivers/edac/amd64_edac.c cs, *mask1, (pvt->fam == 0x10) ? reg1 reg1 392 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c uint32_t reg0, uint32_t reg1, reg1 396 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.c amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); reg1 167 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t reg0, uint32_t reg1, reg1 271 drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h uint32_t reg1, uint32_t val1); reg1 141 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c uint32_t reg0, uint32_t reg1, reg1 152 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c amdgpu_ring_emit_reg_write_reg_wait(ring, reg0, reg1, reg1 177 drivers/gpu/drm/amd/amdgpu/amdgpu_virt.c pr_err("failed to write reg %x wait reg %x\n", reg0, reg1); reg1 4836 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c uint32_t reg0, uint32_t reg1, reg1 4846 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c gfx_v10_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, reg1 4849 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, reg1 5451 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c uint32_t reg0, uint32_t reg1, reg1 5460 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1, reg1 5463 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1, reg1 1196 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c uint32_t reg0, uint32_t reg1, reg1 1202 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c amdgpu_ring_emit_reg_wait(ring, reg1, mask, mask); reg1 924 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c uint32_t reg1 = 0; reg1 933 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); reg1 934 drivers/gpu/drm/amd/display/dc/dce/dce_stream_encoder.c if ((reg1 & 0x1) == 0) reg1 882 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c uint32_t reg1 = 0; reg1 892 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c REG_GET(DP_VID_STREAM_CNTL, DP_VID_STREAM_ENABLE, ®1); reg1 893 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_stream_encoder.c if ((reg1 & 0x1) == 0) reg1 105 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg1 106 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c .enable_reg = SRI(reg1, block, reg_num),\ reg1 108 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg1 110 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg1 111 drivers/gpu/drm/amd/display/dc/irq/dce120/irq_service_dce120.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ reg1 186 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg1 187 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c .enable_reg = SRI(reg1, block, reg_num),\ reg1 189 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg1 191 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg1 192 drivers/gpu/drm/amd/display/dc/irq/dcn10/irq_service_dcn10.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ reg1 188 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg1 189 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c .enable_reg = SRI(reg1, block, reg_num),\ reg1 191 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg1 193 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg1 194 drivers/gpu/drm/amd/display/dc/irq/dcn20/irq_service_dcn20.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ reg1 184 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ reg1 185 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c .enable_reg = SRI(reg1, block, reg_num),\ reg1 187 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg1 189 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\ reg1 190 drivers/gpu/drm/amd/display/dc/irq/dcn21/irq_service_dcn21.c ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \ reg1 340 drivers/gpu/drm/mga/mga_drv.h #define DMA_BLOCK(reg0, val0, reg1, val1, reg2, val2, reg3, val3) \ reg1 343 drivers/gpu/drm/mga/mga_drv.h (DMAREG(reg1) << 8) | \ reg1 131 drivers/gpu/drm/nouveau/dispnv04/hw.c nouveau_hw_decode_pll(struct drm_device *dev, uint32_t reg1, uint32_t pll1, reg1 142 drivers/gpu/drm/nouveau/dispnv04/hw.c if (reg1 <= 0x405c) { reg1 169 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t reg1, pll1, pll2 = 0; reg1 174 drivers/gpu/drm/nouveau/dispnv04/hw.c if (ret || !(reg1 = pll_lim.reg)) reg1 177 drivers/gpu/drm/nouveau/dispnv04/hw.c pll1 = nvif_rd32(device, reg1); reg1 178 drivers/gpu/drm/nouveau/dispnv04/hw.c if (reg1 <= 0x405c) reg1 179 drivers/gpu/drm/nouveau/dispnv04/hw.c pll2 = nvif_rd32(device, reg1 + 4); reg1 181 drivers/gpu/drm/nouveau/dispnv04/hw.c uint32_t reg2 = reg1 + (reg1 == NV_RAMDAC_VPLL2 ? 0x5c : 0x70); reg1 186 drivers/gpu/drm/nouveau/dispnv04/hw.c if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CELSIUS && reg1 >= NV_PRAMDAC_VPLL_COEFF) { reg1 190 drivers/gpu/drm/nouveau/dispnv04/hw.c if (reg1 == NV_PRAMDAC_VPLL_COEFF) { reg1 198 drivers/gpu/drm/nouveau/dispnv04/hw.c nouveau_hw_decode_pll(dev, reg1, pll1, pll2, pllvals); reg1 119 drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h int (*pll_prog)(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *pv); reg1 49 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c nv04_clk_pll_prog(struct nvkm_clk *clk, u32 reg1, struct nvkm_pll_vals *pv) reg1 57 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c if (reg1 > 0x405c) reg1 58 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c setPLL_double_highregs(devinit, reg1, pv); reg1 60 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c setPLL_double_lowregs(devinit, reg1, pv); reg1 62 drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.c setPLL_single(devinit, reg1, pv); reg1 26 drivers/gpu/drm/nouveau/nvkm/subdev/clk/priv.h int nv04_clk_pll_prog(struct nvkm_clk *, u32 reg1, struct nvkm_pll_vals *); reg1 185 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c new_ramdac580(uint32_t reg1, bool ss, uint32_t ramdac580) reg1 187 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c bool head_a = (reg1 == 0x680508); reg1 198 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c setPLL_double_highregs(struct nvkm_devinit *init, u32 reg1, reg1 204 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t reg2 = reg1 + ((reg1 == 0x680520) ? 0x5c : 0x70); reg1 205 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c uint32_t oldpll1 = nvkm_rd32(device, reg1); reg1 212 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c int shift_powerctrl_1 = powerctrl_1_shift(chip_version, reg1); reg1 220 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c if (chip_version > 0x40 && reg1 >= 0x680508) { /* !nv40 */ reg1 222 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c ramdac580 = new_ramdac580(reg1, single_stage, oldramdac580); reg1 246 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c switch (reg1) { reg1 267 drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.c nvkm_wr32(device, reg1, pll1); reg1 420 drivers/gpu/drm/r128/r128_drv.h #define CCE_PACKET1(reg0, reg1) (R128_CCE_PACKET1 | \ reg1 421 drivers/gpu/drm/r128/r128_drv.h (((reg1) >> 2) << 11) | ((reg0) >> 2)) reg1 123 drivers/gpu/ipu-v3/ipu-dc.c u32 reg1, reg2; reg1 126 drivers/gpu/ipu-v3/ipu-dc.c reg1 = (operand << 20) & 0xfff00000; reg1 129 drivers/gpu/ipu-v3/ipu-dc.c reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000); reg1 132 drivers/gpu/ipu-v3/ipu-dc.c reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000); reg1 135 drivers/gpu/ipu-v3/ipu-dc.c writel(reg1, priv->dc_tmpl_reg + word * 8); reg1 358 drivers/hwmon/nct7904.c unsigned int reg1, reg2, reg3; reg1 431 drivers/hwmon/nct7904.c reg1 = LTD_HV_LL_REG; reg1 436 drivers/hwmon/nct7904.c reg1 = LTD_LV_LL_REG; reg1 441 drivers/hwmon/nct7904.c reg1 = LTD_HV_HL_REG; reg1 446 drivers/hwmon/nct7904.c reg1 = LTD_LV_HL_REG; reg1 455 drivers/hwmon/nct7904.c ret = nct7904_read_reg(data, BANK_1, reg1); reg1 535 drivers/hwmon/nct7904.c unsigned int reg1, reg2, reg3; reg1 541 drivers/hwmon/nct7904.c reg1 = LTD_HV_LL_REG; reg1 546 drivers/hwmon/nct7904.c reg1 = LTD_LV_LL_REG; reg1 551 drivers/hwmon/nct7904.c reg1 = LTD_HV_HL_REG; reg1 556 drivers/hwmon/nct7904.c reg1 = LTD_LV_HL_REG; reg1 564 drivers/hwmon/nct7904.c ret = nct7904_write_reg(data, BANK_1, reg1, val); reg1 295 drivers/hwmon/w83795.c u8 reg0, reg1; reg1 307 drivers/hwmon/w83795.c reg1 = clamp_val(DIV_ROUND_CLOSEST(base_clock, val), 1, 128); reg1 308 drivers/hwmon/w83795.c best1 = base_clock / reg1; reg1 309 drivers/hwmon/w83795.c reg1 = 0x80 | (reg1 - 1); reg1 313 drivers/hwmon/w83795.c return reg1; reg1 73 drivers/ide/ali14xx.c static struct { u8 reg1, reg2, reg3, reg4; } regTab[4] = { reg1 139 drivers/ide/ali14xx.c outReg(param1, regTab[driveNum].reg1); reg1 682 drivers/iio/adc/twl6030-gpadc.c unsigned int reg1, unsigned int mask0, unsigned int mask1, reg1 688 drivers/iio/adc/twl6030-gpadc.c val |= (trim_regs[reg1] & mask1) >> 1; reg1 689 drivers/iio/adc/twl6030-gpadc.c if (trim_regs[reg1] & 0x01) reg1 724 drivers/iio/light/si1145.c u8 reg1, reg2, shift; reg1 734 drivers/iio/light/si1145.c reg1 = SI1145_PARAM_PS_ADC_GAIN; reg1 742 drivers/iio/light/si1145.c reg1 = SI1145_PARAM_ALSIR_ADC_GAIN; reg1 745 drivers/iio/light/si1145.c reg1 = SI1145_PARAM_ALSVIS_ADC_GAIN; reg1 757 drivers/iio/light/si1145.c ret = si1145_param_set(data, reg1, val); reg1 773 drivers/iio/light/si1145.c reg1 = SI1145_PS_LED_REG(chan->channel); reg1 780 drivers/iio/light/si1145.c ret = i2c_smbus_read_byte_data(data->client, reg1); reg1 785 drivers/iio/light/si1145.c ret = i2c_smbus_write_byte_data(data->client, reg1, reg1 6746 drivers/infiniband/hw/qib/qib_iba7322.c u64 reg, reg1, reg2; reg1 6761 drivers/infiniband/hw/qib/qib_iba7322.c reg1 = qib_read_kreg_port(ppd, krp_senddmabufmask1); reg1 6765 drivers/infiniband/hw/qib/qib_iba7322.c reg, reg1, reg2); reg1 6770 drivers/infiniband/hw/qib/qib_iba7322.c reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1); reg1 6771 drivers/infiniband/hw/qib/qib_iba7322.c qib_write_kreg_port(ppd, krp_senddmabuf_use0, reg1); reg1 6777 drivers/infiniband/hw/qib/qib_iba7322.c reg, reg1, reg2); reg1 6779 drivers/infiniband/hw/qib/qib_iba7322.c reg1 = qib_read_kreg_port(ppd, krp_senddmabuf_use1); reg1 6784 drivers/infiniband/hw/qib/qib_iba7322.c reg, reg1, reg2); reg1 324 drivers/input/touchscreen/rohm_bu21023.c u8 reg1, reg2, reg3; reg1 409 drivers/input/touchscreen/rohm_bu21023.c reg1 = reg_x >> 3; reg1 414 drivers/input/touchscreen/rohm_bu21023.c CALIBRATION_REG1, reg1); reg1 66 drivers/mcb/mcb-internal.h __le32 reg1; reg1 47 drivers/mcb/mcb-parse.c __le32 reg1; reg1 54 drivers/mcb/mcb-parse.c reg1 = readl(&gdd->reg1); reg1 59 drivers/mcb/mcb-parse.c mdev->id = GDD_DEV(reg1); reg1 60 drivers/mcb/mcb-parse.c mdev->rev = GDD_REV(reg1); reg1 61 drivers/mcb/mcb-parse.c mdev->var = GDD_VAR(reg1); reg1 93 drivers/mcb/mcb-parse.c mdev->irq.start = GDD_IRQ(reg1); reg1 94 drivers/mcb/mcb-parse.c mdev->irq.end = GDD_IRQ(reg1); reg1 21 drivers/media/dvb-frontends/a8293.c u8 reg0, reg1; reg1 50 drivers/media/dvb-frontends/a8293.c reg1 = 0x82; reg1 51 drivers/media/dvb-frontends/a8293.c if (reg1 != dev->reg[1]) { reg1 52 drivers/media/dvb-frontends/a8293.c ret = i2c_master_send(client, ®1, 1); reg1 55 drivers/media/dvb-frontends/a8293.c dev->reg[1] = reg1; reg1 241 drivers/media/dvb-frontends/m88rs2000.c u8 reg0, reg1; reg1 246 drivers/media/dvb-frontends/m88rs2000.c reg1 = m88rs2000_readreg(state, 0xb2); reg1 248 drivers/media/dvb-frontends/m88rs2000.c m88rs2000_writereg(state, 0xb2, reg1); reg1 259 drivers/media/dvb-frontends/m88rs2000.c u8 reg0, reg1; reg1 262 drivers/media/dvb-frontends/m88rs2000.c reg1 = m88rs2000_readreg(state, 0xb2); reg1 264 drivers/media/dvb-frontends/m88rs2000.c reg1 &= 0x3f; reg1 272 drivers/media/dvb-frontends/m88rs2000.c reg1 |= 0x80; reg1 277 drivers/media/dvb-frontends/m88rs2000.c m88rs2000_writereg(state, 0xb2, reg1); reg1 556 drivers/media/dvb-frontends/s5h1409.c u16 reg, reg1, reg2; reg1 571 drivers/media/dvb-frontends/s5h1409.c reg1 = s5h1409_readreg(state, 0xb2); reg1 576 drivers/media/dvb-frontends/s5h1409.c (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); reg1 594 drivers/media/dvb-frontends/s5h1409.c u16 reg, reg1, reg2; reg1 602 drivers/media/dvb-frontends/s5h1409.c reg1 = s5h1409_readreg(state, 0xb2); reg1 607 drivers/media/dvb-frontends/s5h1409.c (((reg1 & 0xf000) >> 4) | (reg2 & 0xf0ff))); reg1 222 drivers/media/dvb-frontends/si21xx.c static int si21_writeregs(struct si21xx_state *state, u8 reg1, reg1 237 drivers/media/dvb-frontends/si21xx.c msg.buf[0] = reg1; reg1 244 drivers/media/dvb-frontends/si21xx.c __func__, reg1, data[0], ret); reg1 307 drivers/media/dvb-frontends/si21xx.c static int si21_readregs(struct si21xx_state *state, u8 reg1, u8 *b, u8 len) reg1 314 drivers/media/dvb-frontends/si21xx.c .buf = ®1, reg1 481 drivers/media/dvb-frontends/si21xx.c u8 reg1; reg1 488 drivers/media/dvb-frontends/si21xx.c reg1 = serit_sp1511lhb_inittab[i]; reg1 490 drivers/media/dvb-frontends/si21xx.c if (reg1 == 0xff && val == 0xff) reg1 492 drivers/media/dvb-frontends/si21xx.c si21_writeregs(state, reg1, &val, 1); reg1 496 drivers/media/dvb-frontends/si21xx.c reg1 = 0x08; reg1 497 drivers/media/dvb-frontends/si21xx.c si21_writeregs(state, SYSTEM_MODE_REG, ®1, 0x01); reg1 95 drivers/media/dvb-frontends/stv0297.c static int stv0297_readregs(struct stv0297_state *state, u8 reg1, u8 * b, u8 len) reg1 99 drivers/media/dvb-frontends/stv0297.c ®1,.len = 1}, reg1 106 drivers/media/dvb-frontends/stv0297.c dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret); reg1 110 drivers/media/dvb-frontends/stv0297.c dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret); reg1 115 drivers/media/dvb-frontends/stv0297.c dprintk("%s: readreg error (reg == 0x%02x, ret == %i)\n", __func__, reg1, ret); reg1 112 drivers/media/dvb-frontends/stv0299.c static int stv0299_readregs (struct stv0299_state* state, u8 reg1, u8 *b, u8 len) reg1 115 drivers/media/dvb-frontends/stv0299.c struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = ®1, .len = 1 }, reg1 64 drivers/media/dvb-frontends/tda8083.c static int tda8083_readregs (struct tda8083_state* state, u8 reg1, u8 *b, u8 len) reg1 67 drivers/media/dvb-frontends/tda8083.c struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = ®1, .len = 1 }, reg1 74 drivers/media/dvb-frontends/tda8083.c __func__, reg1, ret); reg1 64 drivers/media/dvb-frontends/tua6100.c u8 reg1[] = { 0x01, 0x00, 0x00, 0x00 }; reg1 67 drivers/media/dvb-frontends/tua6100.c struct i2c_msg msg1 = { .addr = priv->i2c_address, .flags = 0, .buf = reg1, .len = 4 }; reg1 82 drivers/media/dvb-frontends/tua6100.c reg1[1] = 0x2c; reg1 84 drivers/media/dvb-frontends/tua6100.c reg1[1] = 0x0c; reg1 87 drivers/media/dvb-frontends/tua6100.c reg1[1] |= 0x40; reg1 89 drivers/media/dvb-frontends/tua6100.c reg1[1] |= 0x80; reg1 107 drivers/media/dvb-frontends/tua6100.c reg1[1] |= (div >> 9) & 0x03; reg1 108 drivers/media/dvb-frontends/tua6100.c reg1[2] = div >> 1; reg1 109 drivers/media/dvb-frontends/tua6100.c reg1[3] = (div << 7); reg1 113 drivers/media/dvb-frontends/tua6100.c reg1[3] |= (prediv - (div*_P_VAL)) & 0x7f; reg1 860 drivers/media/i2c/ov9650.c u8 reg0, reg1, reg2; reg1 873 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_VREF, ®1); reg1 876 drivers/media/i2c/ov9650.c gain = ((reg1 >> 6) << 8) | reg0; reg1 887 drivers/media/i2c/ov9650.c ret = ov965x_read(ov965x, REG_AECH, ®1); reg1 893 drivers/media/i2c/ov9650.c exposure = ((reg2 & 0x3f) << 10) | (reg1 << 2) | reg1 229 drivers/media/platform/meson/ao-cec-g12a.c u32 reg0, reg1; reg1 232 drivers/media/platform/meson/ao-cec-g12a.c regmap_read(dualdiv_clk->regmap, CECB_CLK_CNTL_REG0, ®1); reg1 234 drivers/media/platform/meson/ao-cec-g12a.c if (reg1 & CECB_CLK_CNTL_BYPASS_EN) reg1 243 drivers/media/platform/meson/ao-cec-g12a.c m1 = FIELD_GET(CECB_CLK_CNTL_M1, reg1) + 1; reg1 244 drivers/media/platform/meson/ao-cec-g12a.c m2 = FIELD_GET(CECB_CLK_CNTL_M1, reg1) + 1; reg1 738 drivers/media/platform/ti-vpe/cal.c unsigned int reg0, reg1; reg1 780 drivers/media/platform/ti-vpe/cal.c reg1 = reg_read(ctx->cc, CAL_CSI2_PHY_REG1); reg1 781 drivers/media/platform/ti-vpe/cal.c set_field(®1, TCLK_TERM, CAL_CSI2_PHY_REG1_TCLK_TERM_MASK); reg1 782 drivers/media/platform/ti-vpe/cal.c set_field(®1, 0xb8, CAL_CSI2_PHY_REG1_DPHY_HS_SYNC_PATTERN_MASK); reg1 783 drivers/media/platform/ti-vpe/cal.c set_field(®1, TCLK_MISS, CAL_CSI2_PHY_REG1_CTRLCLK_DIV_FACTOR_MASK); reg1 784 drivers/media/platform/ti-vpe/cal.c set_field(®1, TCLK_SETTLE, CAL_CSI2_PHY_REG1_TCLK_SETTLE_MASK); reg1 786 drivers/media/platform/ti-vpe/cal.c ctx_dbg(1, ctx, "CSI2_%d_REG1 = 0x%08x\n", (ctx->csi2_port - 1), reg1); reg1 787 drivers/media/platform/ti-vpe/cal.c reg_write(ctx->cc, CAL_CSI2_PHY_REG1, reg1); reg1 557 drivers/media/usb/dvb-usb-v2/af9015.c unsigned int utmp1, utmp2, reg1, reg2; reg1 574 drivers/media/usb/dvb-usb-v2/af9015.c reg1 = 0xdd88; reg1 578 drivers/media/usb/dvb-usb-v2/af9015.c reg1 = 0xdd8a; reg1 581 drivers/media/usb/dvb-usb-v2/af9015.c ret = regmap_bulk_write(state->regmap, reg1, buf, 2); reg1 40 drivers/misc/cardreader/rtl8411.c u32 reg1 = 0; reg1 43 drivers/misc/cardreader/rtl8411.c rtsx_pci_read_config_dword(pcr, PCR_SETTING_REG1, ®1); reg1 44 drivers/misc/cardreader/rtl8411.c pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg1); reg1 46 drivers/misc/cardreader/rtl8411.c if (!rtsx_vendor_setting_valid(reg1)) reg1 49 drivers/misc/cardreader/rtl8411.c pcr->aspm_en = rtsx_reg_to_aspm(reg1); reg1 51 drivers/misc/cardreader/rtl8411.c map_sd_drive(rtsx_reg_to_sd30_drive_sel_1v8(reg1)); reg1 53 drivers/misc/cardreader/rtl8411.c pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg1); reg1 394 drivers/net/dsa/sja1105/sja1105_dynamic_config.c u8 *reg1 = buf + 4; reg1 396 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &cmd->valid, 31, 31, size, op); reg1 397 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &cmd->index, 26, 24, size, op); reg1 406 drivers/net/dsa/sja1105/sja1105_dynamic_config.c u8 *reg1 = buf + 4; reg1 409 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->speed, 30, 29, size, op); reg1 410 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->drpdtag, 23, 23, size, op); reg1 411 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->drpuntag, 22, 22, size, op); reg1 412 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->retag, 21, 21, size, op); reg1 413 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->dyn_learn, 20, 20, size, op); reg1 414 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->egress, 19, 19, size, op); reg1 415 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->ingress, 18, 18, size, op); reg1 416 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->ing_mirr, 17, 17, size, op); reg1 417 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->egr_mirr, 16, 16, size, op); reg1 418 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->vlanprio, 14, 12, size, op); reg1 419 drivers/net/dsa/sja1105/sja1105_dynamic_config.c sja1105_packing(reg1, &entry->vlanid, 11, 0, size, op); reg1 280 drivers/net/ethernet/8390/wd.c int reg1 = inb(ioaddr+1); reg1 282 drivers/net/ethernet/8390/wd.c if (ancient || reg1 == 0xff) { /* Ack!! No way to read the IRQ! */ reg1 307 drivers/net/ethernet/8390/wd.c dev->irq = irqmap[((reg4 >> 5) & 0x03) + (reg1 & 0x04)]; reg1 1628 drivers/net/ethernet/adaptec/starfire.c u16 reg0, reg1, reg4, reg5; reg1 1637 drivers/net/ethernet/adaptec/starfire.c reg1 = mdio_read(dev, np->phys[0], MII_BMSR); reg1 1639 drivers/net/ethernet/adaptec/starfire.c if (reg1 & BMSR_LSTATUS) { reg1 697 drivers/net/ethernet/marvell/sky2.c u32 reg1; reg1 700 drivers/net/ethernet/marvell/sky2.c reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); reg1 701 drivers/net/ethernet/marvell/sky2.c reg1 &= ~phy_power[port]; reg1 704 drivers/net/ethernet/marvell/sky2.c reg1 |= coma_mode[port]; reg1 706 drivers/net/ethernet/marvell/sky2.c sky2_pci_write32(hw, PCI_DEV_REG1, reg1); reg1 718 drivers/net/ethernet/marvell/sky2.c u32 reg1; reg1 765 drivers/net/ethernet/marvell/sky2.c reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); reg1 766 drivers/net/ethernet/marvell/sky2.c reg1 |= phy_power[port]; /* set PHY to PowerDown/COMA Mode */ reg1 767 drivers/net/ethernet/marvell/sky2.c sky2_pci_write32(hw, PCI_DEV_REG1, reg1); reg1 868 drivers/net/ethernet/marvell/sky2.c u32 reg1 = sky2_pci_read32(hw, PCI_DEV_REG1); reg1 869 drivers/net/ethernet/marvell/sky2.c reg1 |= PCI_Y2_PME_LEGACY; reg1 870 drivers/net/ethernet/marvell/sky2.c sky2_pci_write32(hw, PCI_DEV_REG1, reg1); reg1 85 drivers/net/ethernet/netronome/nfp/bpf/verifier.c const struct bpf_reg_state *reg1 = cur_regs(env) + BPF_REG_1; reg1 99 drivers/net/ethernet/netronome/nfp/bpf/verifier.c offmap = map_to_offmap(reg1->map_ptr); reg1 159 drivers/net/ethernet/netronome/nfp/bpf/verifier.c u32 helper_tgt, const struct bpf_reg_state *reg1) reg1 174 drivers/net/ethernet/netronome/nfp/bpf/verifier.c const struct bpf_reg_state *reg1 = cur_regs(env) + BPF_REG_1; reg1 203 drivers/net/ethernet/netronome/nfp/bpf/verifier.c bpf->helpers.map_lookup, reg1) || reg1 211 drivers/net/ethernet/netronome/nfp/bpf/verifier.c bpf->helpers.map_update, reg1) || reg1 221 drivers/net/ethernet/netronome/nfp/bpf/verifier.c bpf->helpers.map_delete, reg1) || reg1 261 drivers/net/ethernet/netronome/nfp/bpf/verifier.c reg1 = cur_regs(env) + BPF_REG_4; reg1 263 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg1->type != SCALAR_VALUE /* NULL ptr */ && reg1 264 drivers/net/ethernet/netronome/nfp/bpf/verifier.c reg1->type != PTR_TO_STACK && reg1 265 drivers/net/ethernet/netronome/nfp/bpf/verifier.c reg1->type != PTR_TO_MAP_VALUE && reg1 266 drivers/net/ethernet/netronome/nfp/bpf/verifier.c reg1->type != PTR_TO_PACKET) { reg1 268 drivers/net/ethernet/netronome/nfp/bpf/verifier.c reg1->type); reg1 272 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg1->type == PTR_TO_STACK && reg1 273 drivers/net/ethernet/netronome/nfp/bpf/verifier.c !nfp_bpf_stack_arg_ok("event_output", env, reg1, NULL)) reg1 291 drivers/net/ethernet/netronome/nfp/bpf/verifier.c if (reg1->type != meta->arg1.type) { reg1 293 drivers/net/ethernet/netronome/nfp/bpf/verifier.c meta->arg1.type, reg1->type); reg1 304 drivers/net/ethernet/netronome/nfp/bpf/verifier.c meta->arg1 = *reg1; reg1 624 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 748 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 830 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 1522 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 1560 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 5372 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 5452 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 5545 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 5627 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 6455 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 6495 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 7432 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 7726 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 7818 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 8466 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 8506 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 8543 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 8580 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 8771 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 8853 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 8922 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 9424 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 9468 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 9512 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 9767 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 9885 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 10253 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 10360 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 10768 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 10876 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 10941 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 11010 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 11152 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 11401 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 11519 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 11594 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 11640 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 11716 drivers/net/ethernet/qlogic/qed/qed_hsi.h __le32 reg1; reg1 970 drivers/net/ethernet/qlogic/qla3xxx.c u16 reg1; reg1 977 drivers/net/ethernet/qlogic/qla3xxx.c err = ql_mii_read_reg(qdev, PHY_ID_0_REG, ®1); reg1 990 drivers/net/ethernet/qlogic/qla3xxx.c if ((reg1 == 0xffff) || (reg2 == 0xffff)) { reg1 999 drivers/net/ethernet/qlogic/qla3xxx.c err = ql_mii_read_reg_ex(qdev, PHY_ID_0_REG, ®1, miiAddr); reg1 1018 drivers/net/ethernet/qlogic/qla3xxx.c qdev->phyType = getPhyType(qdev, reg1, reg2); reg1 539 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c u32 reg, reg1, reg2, i, j, owner, class; reg1 541 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg1 = QLCRDX(adapter->ahw, QLC_83XX_IDC_DEV_PARTITION_INFO_1); reg1 546 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = reg1; reg1 566 drivers/net/ethernet/qlogic/qlcnic/qlcnic_83xx_init.c reg = reg1; reg1 373 drivers/net/ethernet/socionext/sni_ave.c int reg1, int reg2) reg1 378 drivers/net/ethernet/socionext/sni_ave.c mac_addr[2] << 16 | mac_addr[3] << 24, priv->base + reg1); reg1 2609 drivers/net/ethernet/sun/niu.c u16 reg1 = addr[2] << 8 | addr[3]; reg1 2614 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_ADDR1, reg1); reg1 2618 drivers/net/ethernet/sun/niu.c nw64_mac(BMAC_ADDR1, reg1); reg1 2634 drivers/net/ethernet/sun/niu.c u16 reg1 = addr[2] << 8 | addr[3]; reg1 2642 drivers/net/ethernet/sun/niu.c nw64_mac(XMAC_ALT_ADDR1(index), reg1); reg1 2646 drivers/net/ethernet/sun/niu.c nw64_mac(BMAC_ALT_ADDR1(index), reg1); reg1 158 drivers/net/phy/adin.c u16 reg1; reg1 658 drivers/net/phy/adin.c ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, stat->reg1); reg1 684 drivers/net/phy/adin.c if (stat->reg1 > 0x1f) { reg1 689 drivers/net/phy/adin.c ret = phy_read(phydev, stat->reg1); reg1 71 drivers/net/wireless/ath/ath10k/spectral.c u32 reg0, reg1; reg1 83 drivers/net/wireless/ath/ath10k/spectral.c reg1 = __le32_to_cpu(fftr->reg1); reg1 114 drivers/net/wireless/ath/ath10k/spectral.c fft_sample->relpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB); reg1 115 drivers/net/wireless/ath/ath10k/spectral.c fft_sample->avgpwr_db = MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB); reg1 117 drivers/net/wireless/ath/ath10k/spectral.c peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG); reg1 3955 drivers/net/wireless/ath/ath10k/wmi.c u32 reg0, reg1, tsf32l; reg1 3964 drivers/net/wireless/ath/ath10k/wmi.c reg1 = __le32_to_cpu(rr->reg1); reg1 3976 drivers/net/wireless/ath/ath10k/wmi.c MS(reg1, RADAR_REPORT_REG1_PULSE_SRCH_FFT_VALID), reg1 3977 drivers/net/wireless/ath/ath10k/wmi.c MS(reg1, RADAR_REPORT_REG1_PULSE_AGC_MB_GAIN), reg1 3978 drivers/net/wireless/ath/ath10k/wmi.c MS(reg1, RADAR_REPORT_REG1_PULSE_SUBCHAN_MASK)); reg1 3981 drivers/net/wireless/ath/ath10k/wmi.c MS(reg1, RADAR_REPORT_REG1_PULSE_TSF_OFFSET), reg1 3982 drivers/net/wireless/ath/ath10k/wmi.c MS(reg1, RADAR_REPORT_REG1_PULSE_DUR)); reg1 4006 drivers/net/wireless/ath/ath10k/wmi.c width = MS(reg1, RADAR_REPORT_REG1_PULSE_DUR); reg1 4073 drivers/net/wireless/ath/ath10k/wmi.c u32 reg0, reg1; reg1 4077 drivers/net/wireless/ath/ath10k/wmi.c reg1 = __le32_to_cpu(fftr->reg1); reg1 4088 drivers/net/wireless/ath/ath10k/wmi.c MS(reg1, SEARCH_FFT_REPORT_REG1_RELPWR_DB), reg1 4089 drivers/net/wireless/ath/ath10k/wmi.c MS(reg1, SEARCH_FFT_REPORT_REG1_AVGPWR_DB), reg1 4090 drivers/net/wireless/ath/ath10k/wmi.c MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG), reg1 4091 drivers/net/wireless/ath/ath10k/wmi.c MS(reg1, SEARCH_FFT_REPORT_REG1_NUM_STR_BINS_IB)); reg1 4093 drivers/net/wireless/ath/ath10k/wmi.c peak_mag = MS(reg1, SEARCH_FFT_REPORT_REG1_PEAK_MAG); reg1 3500 drivers/net/wireless/ath/ath10k/wmi.h __le32 reg1; /* RADAR_REPORT_REG1_* */ reg1 3538 drivers/net/wireless/ath/ath10k/wmi.h __le32 reg1; /* SEARCH_FFT_REPORT_REG1_ * */ reg1 123 drivers/pci/controller/pcie-altera.c u32 reg1; reg1 174 drivers/pci/controller/pcie-altera.c cra_writel(pcie, tlp_rp_regdata->reg1, RP_TX_REG1); reg1 205 drivers/pci/controller/pcie-altera.c u32 reg0, reg1; reg1 216 drivers/pci/controller/pcie-altera.c reg1 = cra_readl(pcie, RP_RXCPL_REG1); reg1 220 drivers/pci/controller/pcie-altera.c comp_status = TLP_COMP_STATUS(reg1); reg1 292 drivers/pci/controller/pcie-altera.c tlp_rp_regdata.reg1 = headers[1]; reg1 298 drivers/pci/controller/pcie-altera.c tlp_rp_regdata.reg1 = 0; reg1 303 drivers/pci/controller/pcie-altera.c tlp_rp_regdata.reg1 = 0; reg1 306 drivers/pci/controller/pcie-altera.c tlp_rp_regdata.reg1 = data; reg1 899 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c .fn1 = fn_ ## e, .reg1 = NPCM7XX_GCR_ ## f, .bit1 = g, \ reg1 921 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c int fn1, reg1, bit1; reg1 1426 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c if (cfg->reg1) reg1 1427 drivers/pinctrl/nuvoton/pinctrl-npcm7xx.c regmap_update_bits(gcr_regmap, cfg->reg1, reg1 1390 drivers/pinctrl/pinctrl-ingenic.c u8 reg1, reg2; reg1 1393 drivers/pinctrl/pinctrl-ingenic.c reg1 = JZ4760_GPIO_PAT1; reg1 1396 drivers/pinctrl/pinctrl-ingenic.c reg1 = JZ4740_GPIO_TRIG; reg1 1404 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); reg1 1408 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_set_bit(jzgc, reg1, offset, true); reg1 1414 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, true); reg1 1418 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_set_bit(jzgc, reg1, offset, true); reg1 1424 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); reg1 1428 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_set_bit(jzgc, reg1, offset, false); reg1 1435 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_shadow_set_bit(jzgc, reg1, offset, false); reg1 1439 drivers/pinctrl/pinctrl-ingenic.c ingenic_gpio_set_bit(jzgc, reg1, offset, false); reg1 260 drivers/power/supply/wm831x_power.c int ret, reg1, reg2; reg1 270 drivers/power/supply/wm831x_power.c reg1 = 0; reg1 278 drivers/power/supply/wm831x_power.c reg1 |= WM831X_CHG_ENA; reg1 282 drivers/power/supply/wm831x_power.c reg1 |= WM831X_CHG_FAST; reg1 298 drivers/power/supply/wm831x_power.c pdata->eoc_iterm, ®1, reg1 315 drivers/power/supply/wm831x_power.c reg1); reg1 893 drivers/regulator/helpers.c bool regulator_is_equal(struct regulator *reg1, struct regulator *reg2) reg1 895 drivers/regulator/helpers.c return reg1->rdev == reg2->rdev; reg1 26 drivers/rtc/rtc-aspeed.c u32 reg1, reg2; reg1 35 drivers/rtc/rtc-aspeed.c reg1 = readl(rtc->base + RTC_TIME); reg1 38 drivers/rtc/rtc-aspeed.c tm->tm_mday = (reg1 >> 24) & 0x1f; reg1 39 drivers/rtc/rtc-aspeed.c tm->tm_hour = (reg1 >> 16) & 0x1f; reg1 40 drivers/rtc/rtc-aspeed.c tm->tm_min = (reg1 >> 8) & 0x3f; reg1 41 drivers/rtc/rtc-aspeed.c tm->tm_sec = (reg1 >> 0) & 0x3f; reg1 56 drivers/rtc/rtc-aspeed.c u32 reg1, reg2, ctrl; reg1 62 drivers/rtc/rtc-aspeed.c reg1 = (tm->tm_mday << 24) | (tm->tm_hour << 16) | (tm->tm_min << 8) | reg1 71 drivers/rtc/rtc-aspeed.c writel(reg1, rtc->base + RTC_TIME); reg1 18 drivers/s390/cio/ioasm.c register struct subchannel_id reg1 asm ("1") = schid; reg1 28 drivers/s390/cio/ioasm.c : "d" (reg1), "a" (addr) reg1 46 drivers/s390/cio/ioasm.c register struct subchannel_id reg1 asm ("1") = schid; reg1 56 drivers/s390/cio/ioasm.c : "d" (reg1), "a" (addr), "m" (*addr) reg1 73 drivers/s390/cio/ioasm.c register struct subchannel_id reg1 asm ("1") = schid; reg1 81 drivers/s390/cio/ioasm.c : "d" (reg1), "a" (addr) reg1 98 drivers/s390/cio/ioasm.c register struct subchannel_id reg1 asm("1") = schid; reg1 108 drivers/s390/cio/ioasm.c : "d" (reg1), "a" (addr), "m" (*addr) reg1 126 drivers/s390/cio/ioasm.c register struct subchannel_id reg1 asm("1") = schid; reg1 134 drivers/s390/cio/ioasm.c : "d" (reg1) reg1 188 drivers/s390/cio/ioasm.c register struct subchannel_id reg1 asm("1") = schid; reg1 196 drivers/s390/cio/ioasm.c : "d" (reg1) reg1 214 drivers/s390/cio/ioasm.c register struct subchannel_id reg1 asm("1") = schid; reg1 222 drivers/s390/cio/ioasm.c : "d" (reg1) reg1 240 drivers/s390/cio/ioasm.c register struct subchannel_id reg1 asm("1") = schid; reg1 248 drivers/s390/cio/ioasm.c : "d" (reg1) reg1 198 drivers/scsi/NCR5380.c unsigned int reg1, u8 bit1, u8 val1, reg1 206 drivers/scsi/NCR5380.c if ((NCR5380_read(reg1) & bit1) == val1) reg1 219 drivers/scsi/NCR5380.c if ((NCR5380_read(reg1) & bit1) == val1) reg1 267 drivers/scsi/qedi/qedi_fw_api.c SET_FIELD(ustorm_st_cxt->reg1.reg1_map, ISCSI_REG1_NUM_SGES, num_sges); reg1 1155 drivers/staging/octeon/octeon-stubs.h uint64_t reg1:11; reg1 83 drivers/staging/rts5208/rtsx_card.c u8 reg1 = 0, reg2 = 0; reg1 85 drivers/staging/rts5208/rtsx_card.c rtsx_read_register(chip, 0xFF34, ®1); reg1 88 drivers/staging/rts5208/rtsx_card.c reg1, reg2); reg1 89 drivers/staging/rts5208/rtsx_card.c if ((reg1 & 0xC0) && (reg2 & 0xC0)) { reg1 914 drivers/staging/rts5208/rtsx_chip.c u8 reg0 = 0, reg1 = 0; reg1 925 drivers/staging/rts5208/rtsx_chip.c reg1 = (u8)tmp; reg1 926 drivers/staging/rts5208/rtsx_chip.c if (chip->aspm_level[1] != reg1) { reg1 928 drivers/staging/rts5208/rtsx_chip.c chip->aspm_level[1] = reg1; reg1 931 drivers/staging/rts5208/rtsx_chip.c if ((reg0 & 0x03) && (reg1 & 0x03)) reg1 182 drivers/tee/optee/optee_private.h static inline void *reg_pair_to_ptr(u32 reg0, u32 reg1) reg1 184 drivers/tee/optee/optee_private.h return (void *)(unsigned long)(((u64)reg0 << 32) | reg1); reg1 187 drivers/tee/optee/optee_private.h static inline void reg_pair_from_64(u32 *reg0, u32 *reg1, u64 val) reg1 190 drivers/tee/optee/optee_private.h *reg1 = val; reg1 670 drivers/thermal/ti-soc-thermal/ti-bandgap.c u32 temp1, temp2, reg1, reg2; reg1 689 drivers/thermal/ti-soc-thermal/ti-bandgap.c reg1 = tsr->ctrl_dtemp_1; reg1 693 drivers/thermal/ti-soc-thermal/ti-bandgap.c temp1 = ti_bandgap_readl(bgp, reg1); reg1 402 drivers/video/fbdev/i810/i810_main.c u32 reg1; reg1 405 drivers/video/fbdev/i810/i810_main.c reg1 = i810_readl(PIXCONF, mmio) & ~(0xF0000 | 1 << 27); reg1 408 drivers/video/fbdev/i810/i810_main.c reg1 |= 0x8000 | par->pixconf; reg1 410 drivers/video/fbdev/i810/i810_main.c i810_writel(PIXCONF, mmio, reg1); reg1 7664 drivers/video/fbdev/sis/init301.c unsigned short vclkindex, temp, reg1, reg2; reg1 7667 drivers/video/fbdev/sis/init301.c reg1 = SiS_Pr->CSR2B; reg1 7671 drivers/video/fbdev/sis/init301.c reg1 = SiS_Pr->SiS_VBVCLKData[vclkindex].Part4_A; reg1 7681 drivers/video/fbdev/sis/init301.c SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,reg1); reg1 7687 drivers/video/fbdev/sis/init301.c SiS_SetReg(SiS_Pr->SiS_Part4Port,0x0a,reg1); reg1 852 drivers/video/fbdev/sis/sis_main.c u8 idx, reg1, reg2, reg3, reg4; reg1 869 drivers/video/fbdev/sis/sis_main.c reg1 = SiS_GetReg(SISPART1, (idx+0)); /* 30 */ reg1 873 drivers/video/fbdev/sis/sis_main.c if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING; reg1 874 drivers/video/fbdev/sis/sis_main.c if(reg1 & 0x02) ret |= FB_VBLANK_VSYNCING; reg1 885 drivers/video/fbdev/sis/sis_main.c reg1 = SiS_GetRegByte(SISINPSTAT); reg1 886 drivers/video/fbdev/sis/sis_main.c if(reg1 & 0x08) ret |= FB_VBLANK_VSYNCING; reg1 887 drivers/video/fbdev/sis/sis_main.c if(reg1 & 0x01) ret |= FB_VBLANK_VBLANKING; reg1 888 drivers/video/fbdev/sis/sis_main.c reg1 = SiS_GetReg(SISCR, 0x20); reg1 889 drivers/video/fbdev/sis/sis_main.c reg1 = SiS_GetReg(SISCR, 0x1b); reg1 893 drivers/video/fbdev/sis/sis_main.c (*hcount) = (reg1 | ((reg3 & 0x10) << 4)) << 3; reg1 3820 drivers/video/fbdev/sis/sis_main.c u8 reg1; reg1 3855 drivers/video/fbdev/sis/sis_main.c reg1 = 0xc0; reg1 3859 drivers/video/fbdev/sis/sis_main.c reg1 = 0x00; reg1 3862 drivers/video/fbdev/sis/sis_main.c SiS_SetRegANDOR(SISSR, 0x1f, 0x3f, reg1); reg1 204 include/linux/qed/fcoe_common.h __le32 reg1; reg1 940 include/linux/qed/iscsi_common.h struct iscsi_reg1 reg1; reg1 1357 include/linux/qed/iscsi_common.h __le32 reg1; reg1 1551 include/linux/qed/iscsi_common.h __le32 reg1; reg1 290 include/linux/regulator/consumer.h bool regulator_is_equal(struct regulator *reg1, struct regulator *reg2); reg1 599 include/linux/regulator/consumer.h regulator_is_equal(struct regulator *reg1, struct regulator *reg2) reg1 328 include/sound/sb.h #define SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) \ reg1 329 include/sound/sb.h ((reg1) | ((reg2) << 8) | ((left_shift) << 16) | ((right_shift) << 24)) reg1 350 include/sound/sb.h #define SB16_INPUT_SW(xname, reg1, reg2, left_shift, right_shift) \ reg1 353 include/sound/sb.h .private_value = SB_MIXVAL_INPUT_SW(reg1, reg2, left_shift, right_shift) } reg1 313 net/iucv/iucv.c register unsigned long reg1 asm ("1"); reg1 317 net/iucv/iucv.c reg1 = (unsigned long)parm; reg1 322 net/iucv/iucv.c : "=d" (ccode), "=m" (*parm), "+d" (reg0), "+a" (reg1) reg1 346 net/iucv/iucv.c register unsigned long reg1 asm ("1"); reg1 350 net/iucv/iucv.c reg1 = (unsigned long) param; reg1 355 net/iucv/iucv.c : "=d" (ccode), "+d" (reg0), "+d" (reg1) : : "cc"); reg1 356 net/iucv/iucv.c *max_pathid = reg1; reg1 388 sound/isa/sb/sb_mixer.c int reg1 = kcontrol->private_value & 0xff; reg1 395 sound/isa/sb/sb_mixer.c val1 = snd_sbmixer_read(sb, reg1); reg1 409 sound/isa/sb/sb_mixer.c int reg1 = kcontrol->private_value & 0xff; reg1 417 sound/isa/sb/sb_mixer.c oval1 = snd_sbmixer_read(sb, reg1); reg1 427 sound/isa/sb/sb_mixer.c snd_sbmixer_write(sb, reg1, val1); reg1 198 sound/pci/ak4531_codec.c #define AK4531_INPUT_SW(xname, xindex, reg1, reg2, left_shift, right_shift) \ reg1 202 sound/pci/ak4531_codec.c .private_value = reg1 | (reg2 << 8) | (left_shift << 16) | (right_shift << 24) } reg1 216 sound/pci/ak4531_codec.c int reg1 = kcontrol->private_value & 0xff; reg1 222 sound/pci/ak4531_codec.c ucontrol->value.integer.value[0] = (ak4531->regs[reg1] >> left_shift) & 1; reg1 224 sound/pci/ak4531_codec.c ucontrol->value.integer.value[2] = (ak4531->regs[reg1] >> right_shift) & 1; reg1 233 sound/pci/ak4531_codec.c int reg1 = kcontrol->private_value & 0xff; reg1 241 sound/pci/ak4531_codec.c val1 = ak4531->regs[reg1] & ~((1 << left_shift) | (1 << right_shift)); reg1 247 sound/pci/ak4531_codec.c change = val1 != ak4531->regs[reg1] || val2 != ak4531->regs[reg2]; reg1 248 sound/pci/ak4531_codec.c ak4531->write(ak4531, reg1, ak4531->regs[reg1] = val1); reg1 34 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACL1, reg1 45 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACL2, reg1 56 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACL3, reg1 66 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACCTRL2, reg1 73 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACCTRL2, reg1 80 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACCTRL2, reg1 87 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_IFCTRL, reg1 93 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_IFCTRL, reg1 99 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_IFCTRL, reg1 105 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACCTRL2, reg1 111 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACCTRL2, reg1 117 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACCTRL2, reg1 123 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACCTRL1, reg1 129 sound/pci/ice1712/wm8766.c .reg1 = WM8766_REG_DACCTRL2, reg1 215 sound/pci/ice1712/wm8766.c val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; reg1 253 sound/pci/ice1712/wm8766.c val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; reg1 257 sound/pci/ice1712/wm8766.c wm->ctl[n].reg1 == wm->ctl[n].reg2) { reg1 261 sound/pci/ice1712/wm8766.c snd_wm8766_write(wm, wm->ctl[n].reg1, val); reg1 264 sound/pci/ice1712/wm8766.c wm->ctl[n].reg1 != wm->ctl[n].reg2) { reg1 124 sound/pci/ice1712/wm8766.h u16 reg1, reg2, mask1, mask2, min, max, flags; reg1 137 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_DACLVOL, reg1 147 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_DACCTRL1, reg1 156 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_DACCTRL1, reg1 163 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_HPLVOL, reg1 174 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_PWRDOWN, reg1 181 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_HPLVOL, reg1 190 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_OUTMUX, reg1 196 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_OUTMUX, reg1 202 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_DACCTRL1, reg1 208 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_PHASESWAP, reg1 217 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_DACCTRL2, reg1 224 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ADCLVOL, reg1 234 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ADCMUX, reg1 243 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ADCMUX, reg1 249 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ADCMUX, reg1 255 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ADCMUX, reg1 261 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ADCMUX, reg1 267 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ADCMUX, reg1 283 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ALCCTRL1, reg1 294 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ALCCTRL3, reg1 305 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ALCCTRL3, reg1 315 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_LIMITER, reg1 323 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_LIMITER, reg1 333 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ALCCTRL1, reg1 345 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ALCCTRL3, reg1 356 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ALCCTRL3, reg1 364 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ALCCTRL1, reg1 374 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_LIMITER, reg1 388 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_ALCCTRL2, reg1 395 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_NOISEGATE, reg1 403 sound/pci/ice1712/wm8776.c .reg1 = WM8776_REG_NOISEGATE, reg1 489 sound/pci/ice1712/wm8776.c val1 = wm->regs[wm->ctl[n].reg1] & wm->ctl[n].mask1; reg1 527 sound/pci/ice1712/wm8776.c val = wm->regs[wm->ctl[n].reg1] & ~wm->ctl[n].mask1; reg1 531 sound/pci/ice1712/wm8776.c wm->ctl[n].reg1 == wm->ctl[n].reg2) { reg1 535 sound/pci/ice1712/wm8776.c snd_wm8776_write(wm, wm->ctl[n].reg1, val); reg1 538 sound/pci/ice1712/wm8776.c wm->ctl[n].reg1 != wm->ctl[n].reg2) { reg1 180 sound/pci/ice1712/wm8776.h u16 reg1, reg2, mask1, mask2, min, max, flags; reg1 690 sound/soc/codecs/cx2072x.c union cx2072x_reg_i2spcm_ctrl_reg1 reg1; reg1 782 sound/soc/codecs/cx2072x.c reg1.r.rx_data_one_line = 1; reg1 783 sound/soc/codecs/cx2072x.c reg1.r.tx_data_one_line = 1; reg1 791 sound/soc/codecs/cx2072x.c reg1.r.rx_ws_pol = is_frame_inv; reg1 792 sound/soc/codecs/cx2072x.c reg1.r.rx_ws_wid = pulse_len - 1; reg1 794 sound/soc/codecs/cx2072x.c reg1.r.rx_frm_len = frame_len / BITS_PER_SLOT - 1; reg1 795 sound/soc/codecs/cx2072x.c reg1.r.rx_sa_size = (sample_size / BITS_PER_SLOT) - 1; reg1 797 sound/soc/codecs/cx2072x.c reg1.r.tx_ws_pol = reg1.r.rx_ws_pol; reg1 798 sound/soc/codecs/cx2072x.c reg1.r.tx_ws_wid = pulse_len - 1; reg1 799 sound/soc/codecs/cx2072x.c reg1.r.tx_frm_len = reg1.r.rx_frm_len; reg1 800 sound/soc/codecs/cx2072x.c reg1.r.tx_sa_size = reg1.r.rx_sa_size; reg1 830 sound/soc/codecs/cx2072x.c reg1.r.rx_data_one_line = 1; reg1 831 sound/soc/codecs/cx2072x.c reg1.r.tx_data_one_line = 1; reg1 853 sound/soc/codecs/cx2072x.c regmap_write(cx2072x->regmap, CX2072X_I2SPCM_CONTROL1, reg1.ulval); reg1 471 sound/soc/codecs/wm8993.c u16 reg1, reg4, reg5; reg1 486 sound/soc/codecs/wm8993.c reg1 = snd_soc_component_read32(component, WM8993_FLL_CONTROL_1); reg1 487 sound/soc/codecs/wm8993.c reg1 &= ~WM8993_FLL_ENA; reg1 488 sound/soc/codecs/wm8993.c snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1); reg1 519 sound/soc/codecs/wm8993.c reg1 = snd_soc_component_read32(component, WM8993_FLL_CONTROL_1); reg1 520 sound/soc/codecs/wm8993.c reg1 &= ~WM8993_FLL_ENA; reg1 521 sound/soc/codecs/wm8993.c snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1); reg1 525 sound/soc/codecs/wm8993.c reg1 |= WM8993_FLL_FRAC_MASK; reg1 527 sound/soc/codecs/wm8993.c reg1 &= ~WM8993_FLL_FRAC_MASK; reg1 528 sound/soc/codecs/wm8993.c snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1); reg1 555 sound/soc/codecs/wm8993.c snd_soc_component_write(component, WM8993_FLL_CONTROL_1, reg1 | WM8993_FLL_ENA); reg1 160 sound/soc/codecs/wm8994.c int reg1 = 0; reg1 174 sound/soc/codecs/wm8994.c reg1 |= 0x8; reg1 179 sound/soc/codecs/wm8994.c reg1 |= 0x10; reg1 184 sound/soc/codecs/wm8994.c reg1 |= 0x18; reg1 194 sound/soc/codecs/wm8994.c reg1 |= WM8994_AIF1CLK_DIV; reg1 204 sound/soc/codecs/wm8994.c reg1); reg1 673 sound/soc/codecs/wm8995.c int reg1 = 0; reg1 688 sound/soc/codecs/wm8995.c reg1 |= 0x8; reg1 692 sound/soc/codecs/wm8995.c reg1 |= 0x10; reg1 696 sound/soc/codecs/wm8995.c reg1 |= 0x18; reg1 705 sound/soc/codecs/wm8995.c reg1 |= WM8995_AIF1CLK_DIV; reg1 715 sound/soc/codecs/wm8995.c reg1); reg1 549 sound/soc/codecs/wm9081.c u16 reg1, reg4, reg5; reg1 592 sound/soc/codecs/wm9081.c reg1 = snd_soc_component_read32(component, WM9081_FLL_CONTROL_1); reg1 593 sound/soc/codecs/wm9081.c reg1 &= ~WM9081_FLL_ENA; reg1 594 sound/soc/codecs/wm9081.c snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1); reg1 598 sound/soc/codecs/wm9081.c reg1 |= WM9081_FLL_FRAC_MASK; reg1 600 sound/soc/codecs/wm9081.c reg1 &= ~WM9081_FLL_FRAC_MASK; reg1 601 sound/soc/codecs/wm9081.c snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1); reg1 622 sound/soc/codecs/wm9081.c snd_soc_component_write(component, WM9081_FLL_CONTROL_1, reg1 | WM9081_FLL_ENA);