reference_divider 5259 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 reference_divider; reference_divider 5268 drivers/gpu/drm/amd/amdgpu/si_dpm.c reference_divider = 1 + dividers.ref_div; reference_divider 5270 drivers/gpu/drm/amd/amdgpu/si_dpm.c tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; reference_divider 5291 drivers/gpu/drm/amd/amdgpu/si_dpm.c u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); reference_divider 957 drivers/gpu/drm/amd/display/dc/bios/command_table.c cpu_to_le16((uint16_t)bp_params->reference_divider); reference_divider 1028 drivers/gpu/drm/amd/display/dc/bios/command_table.c (uint8_t)(bp_params->reference_divider); reference_divider 1104 drivers/gpu/drm/amd/display/dc/bios/command_table.c (uint8_t) bp_params->reference_divider; reference_divider 1520 drivers/gpu/drm/amd/display/dc/bios/command_table.c bp_params->reference_divider = params.sOutput.ucRefDiv; reference_divider 237 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->reference_divider = ref_divider; reference_divider 337 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c if (pll_settings->reference_divider) { reference_divider 338 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c min_ref_divider = pll_settings->reference_divider; reference_divider 339 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c max_ref_divider = pll_settings->reference_divider; reference_divider 452 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->reference_divider = reference_divider 453 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c bp_adjust_pixel_clock_params.reference_divider; reference_divider 696 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c pll_settings->reference_divider * ss_data->modulation_freq_hz); reference_divider 865 drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c bp_pc_params.reference_divider = pll_settings->reference_divider; reference_divider 112 drivers/gpu/drm/amd/display/dc/inc/clock_source.h uint32_t reference_divider; reference_divider 200 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t reference_divider; reference_divider 217 drivers/gpu/drm/amd/display/include/bios_parser_types.h uint32_t reference_divider; reference_divider 806 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t reference_divider; reference_divider 819 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c reference_divider = 1 + dividers.uc_pll_ref_div; reference_divider 849 drivers/gpu/drm/amd/powerplay/smumgr/iceland_smumgr.c uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); reference_divider 549 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t reference_divider; reference_divider 562 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c reference_divider = 1 + dividers.uc_pll_ref_div; reference_divider 592 drivers/gpu/drm/amd/powerplay/smumgr/tonga_smumgr.c uint32_t clkS = reference_clock * 5 / (reference_divider * ss_info.speed_spectrum_rate); reference_divider 3170 drivers/gpu/drm/radeon/ci_dpm.c u32 reference_divider; reference_divider 3180 drivers/gpu/drm/radeon/ci_dpm.c reference_divider = 1 + dividers.ref_div; reference_divider 3193 drivers/gpu/drm/radeon/ci_dpm.c u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); reference_divider 2013 drivers/gpu/drm/radeon/ni_dpm.c u32 reference_divider; reference_divider 2022 drivers/gpu/drm/radeon/ni_dpm.c reference_divider = 1 + dividers.ref_div; reference_divider 2025 drivers/gpu/drm/radeon/ni_dpm.c tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16834; reference_divider 2046 drivers/gpu/drm/radeon/ni_dpm.c u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); reference_divider 52 drivers/gpu/drm/radeon/rv730_dpm.c u32 reference_divider, post_divider; reference_divider 61 drivers/gpu/drm/radeon/rv730_dpm.c reference_divider = 1 + dividers.ref_div; reference_divider 69 drivers/gpu/drm/radeon/rv730_dpm.c tmp = (u64) engine_clock * reference_divider * post_divider * 16384; reference_divider 96 drivers/gpu/drm/radeon/rv730_dpm.c u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); reference_divider 131 drivers/gpu/drm/radeon/rv730_dpm.c u32 post_divider, reference_divider; reference_divider 139 drivers/gpu/drm/radeon/rv730_dpm.c reference_divider = dividers.ref_div + 1; reference_divider 172 drivers/gpu/drm/radeon/rv730_dpm.c u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); reference_divider 132 drivers/gpu/drm/radeon/rv740_dpm.c u32 reference_divider; reference_divider 141 drivers/gpu/drm/radeon/rv740_dpm.c reference_divider = 1 + dividers.ref_div; reference_divider 143 drivers/gpu/drm/radeon/rv740_dpm.c tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; reference_divider 164 drivers/gpu/drm/radeon/rv740_dpm.c u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); reference_divider 324 drivers/gpu/drm/radeon/rv770_dpm.c u32 post_divider, reference_divider, feedback_divider8; reference_divider 333 drivers/gpu/drm/radeon/rv770_dpm.c reference_divider = dividers->ref_div; reference_divider 336 drivers/gpu/drm/radeon/rv770_dpm.c (8 * fyclk * reference_divider * post_divider) / reference_clock; reference_divider 501 drivers/gpu/drm/radeon/rv770_dpm.c u32 reference_divider, post_divider; reference_divider 510 drivers/gpu/drm/radeon/rv770_dpm.c reference_divider = 1 + dividers.ref_div; reference_divider 517 drivers/gpu/drm/radeon/rv770_dpm.c tmp = (u64) engine_clock * reference_divider * post_divider * 16384; reference_divider 543 drivers/gpu/drm/radeon/rv770_dpm.c u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); reference_divider 4797 drivers/gpu/drm/radeon/si_dpm.c u32 reference_divider; reference_divider 4806 drivers/gpu/drm/radeon/si_dpm.c reference_divider = 1 + dividers.ref_div; reference_divider 4808 drivers/gpu/drm/radeon/si_dpm.c tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; reference_divider 4829 drivers/gpu/drm/radeon/si_dpm.c u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);