refcyc_per_meta_chunk_vblank_l  698 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
refcyc_per_meta_chunk_vblank_l  899 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
refcyc_per_meta_chunk_vblank_l  205 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
refcyc_per_meta_chunk_vblank_l  265 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				dlg_regs->refcyc_per_pte_group_vblank_c, dlg_regs->refcyc_per_meta_chunk_vblank_l,
refcyc_per_meta_chunk_vblank_l  263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REFCYC_PER_META_CHUNK_VBLANK_L, dlg_attr->refcyc_per_meta_chunk_vblank_l);
refcyc_per_meta_chunk_vblank_l 1097 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		REFCYC_PER_META_CHUNK_VBLANK_L, &dlg_attr->refcyc_per_meta_chunk_vblank_l);
refcyc_per_meta_chunk_vblank_l 1426 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
refcyc_per_meta_chunk_vblank_l 1429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
refcyc_per_meta_chunk_vblank_l 1432 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
refcyc_per_meta_chunk_vblank_l 1426 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
refcyc_per_meta_chunk_vblank_l 1429 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
refcyc_per_meta_chunk_vblank_l 1432 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
refcyc_per_meta_chunk_vblank_l 1504 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
refcyc_per_meta_chunk_vblank_l 1507 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int)dml_pow(2, 13));
refcyc_per_meta_chunk_vblank_l 1510 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l; // dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now
refcyc_per_meta_chunk_vblank_l  425 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int refcyc_per_meta_chunk_vblank_l;
refcyc_per_meta_chunk_vblank_l  248 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 			dlg_regs.refcyc_per_meta_chunk_vblank_l);
refcyc_per_meta_chunk_vblank_l 1526 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	disp_dlg_regs->refcyc_per_meta_chunk_vblank_l =
refcyc_per_meta_chunk_vblank_l 1529 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	ASSERT(disp_dlg_regs->refcyc_per_meta_chunk_vblank_l < (unsigned int) dml_pow(2, 13));
refcyc_per_meta_chunk_vblank_l 1532 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 			disp_dlg_regs->refcyc_per_meta_chunk_vblank_l;/* dcc for 4:2:0 is not supported in dcn1.0.  assigned to be the same as _l for now */