refcyc_per_line_delivery_pre_l 704 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, refcyc_per_line_delivery_pre_l 916 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, refcyc_per_line_delivery_pre_l 212 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l, refcyc_per_line_delivery_pre_l 272 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c dlg_regs->refcyc_per_meta_chunk_nom_c, dlg_regs->refcyc_per_line_delivery_pre_l, refcyc_per_line_delivery_pre_l 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REFCYC_PER_LINE_DELIVERY_PRE_L, dlg_attr->refcyc_per_line_delivery_pre_l, refcyc_per_line_delivery_pre_l 1114 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c REFCYC_PER_LINE_DELIVERY_PRE_L, &dlg_attr->refcyc_per_line_delivery_pre_l, refcyc_per_line_delivery_pre_l 882 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c double refcyc_per_line_delivery_pre_l; refcyc_per_line_delivery_pre_l 1184 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c refcyc_per_line_delivery_pre_l = 0.; refcyc_per_line_delivery_pre_l 1209 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, refcyc_per_line_delivery_pre_l 1239 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c refcyc_per_line_delivery_pre_l); refcyc_per_line_delivery_pre_l 1495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, refcyc_per_line_delivery_pre_l 1499 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); refcyc_per_line_delivery_pre_l 882 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c double refcyc_per_line_delivery_pre_l; refcyc_per_line_delivery_pre_l 1184 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c refcyc_per_line_delivery_pre_l = 0.; refcyc_per_line_delivery_pre_l 1209 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery(mode_lib, refcyc_per_line_delivery_pre_l 1239 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c refcyc_per_line_delivery_pre_l); refcyc_per_line_delivery_pre_l 1495 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor(refcyc_per_line_delivery_pre_l, refcyc_per_line_delivery_pre_l 1499 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13)); refcyc_per_line_delivery_pre_l 929 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c double refcyc_per_line_delivery_pre_l; refcyc_per_line_delivery_pre_l 1236 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c refcyc_per_line_delivery_pre_l = 0.; refcyc_per_line_delivery_pre_l 1262 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( refcyc_per_line_delivery_pre_l 1294 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c refcyc_per_line_delivery_pre_l); refcyc_per_line_delivery_pre_l 1595 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( refcyc_per_line_delivery_pre_l 1596 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c refcyc_per_line_delivery_pre_l, 1); refcyc_per_line_delivery_pre_l 1599 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int)dml_pow(2, 13)); refcyc_per_line_delivery_pre_l 439 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h unsigned int refcyc_per_line_delivery_pre_l; refcyc_per_line_delivery_pre_l 290 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c dlg_regs.refcyc_per_line_delivery_pre_l); refcyc_per_line_delivery_pre_l 1096 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c double refcyc_per_line_delivery_pre_l; refcyc_per_line_delivery_pre_l 1622 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c refcyc_per_line_delivery_pre_l = 0.; refcyc_per_line_delivery_pre_l 1644 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c refcyc_per_line_delivery_pre_l = get_refcyc_per_delivery( refcyc_per_line_delivery_pre_l 1669 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c refcyc_per_line_delivery_pre_l); refcyc_per_line_delivery_pre_l 1675 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c disp_dlg_regs->refcyc_per_line_delivery_pre_l = (unsigned int) dml_floor( refcyc_per_line_delivery_pre_l 1676 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c refcyc_per_line_delivery_pre_l, refcyc_per_line_delivery_pre_l 1681 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c ASSERT(disp_dlg_regs->refcyc_per_line_delivery_pre_l < (unsigned int) dml_pow(2, 13));