refclk_cfg        135 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	u32 refclk_cfg, frac_n_mode, frac_n_value;
refclk_cfg        163 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
refclk_cfg        168 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 		refclk_cfg = 0x0;
refclk_cfg        174 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	DBG("refclk_cfg = %d", refclk_cfg);
refclk_cfg        227 drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c 	pll_write(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG, refclk_cfg);