ref_dppclk        175 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	clk_mgr->dccg->ref_dppclk = khz;
ref_dppclk        372 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn20/dcn20_clk_mgr.c 	clk_mgr_int->dccg->ref_dppclk = clk_mgr->clks.fclk_khz;
ref_dppclk         54 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 	if (dccg->ref_dppclk && req_dppclk) {
ref_dppclk         55 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		int ref_dppclk = dccg->ref_dppclk;
ref_dppclk         58 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		ASSERT(req_dppclk <= ref_dppclk);
ref_dppclk         60 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 		if (ref_dppclk > 0xff) {
ref_dppclk         61 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 			int divider = (ref_dppclk + 0xfe) / 0xff;
ref_dppclk         63 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 			ref_dppclk /= divider;
ref_dppclk         65 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 			if (req_dppclk > ref_dppclk)
ref_dppclk         66 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 				req_dppclk = ref_dppclk;
ref_dppclk         75 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 			if (req_dppclk * current_modulo >= current_phase * ref_dppclk) {
ref_dppclk         78 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 						DPPCLK0_DTO_MODULO, ref_dppclk);
ref_dppclk         87 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dccg.c 					DPPCLK0_DTO_MODULO, ref_dppclk);
ref_dppclk         35 drivers/gpu/drm/amd/display/dc/inc/hw/dccg.h 	int ref_dppclk;