ref_div 148 arch/mips/ath79/clock.c u32 ref_div; ref_div 167 arch/mips/ath79/clock.c ref_div = 1; ref_div 182 arch/mips/ath79/clock.c ref_div = t; ref_div 205 arch/mips/ath79/clock.c ref_div * out_div * cpu_div); ref_div 207 arch/mips/ath79/clock.c ref_div * out_div * ddr_div); ref_div 209 arch/mips/ath79/clock.c ref_div * out_div * ahb_div); ref_div 212 arch/mips/ath79/clock.c static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac, ref_div 220 arch/mips/ath79/clock.c do_div(t, ref_div); ref_div 225 arch/mips/ath79/clock.c do_div(t, ref_div * frac); ref_div 238 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv; ref_div 261 arch/mips/ath79/clock.c ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & ref_div 268 arch/mips/ath79/clock.c ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ref_div 277 arch/mips/ath79/clock.c cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, ref_div 288 arch/mips/ath79/clock.c ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) & ref_div 295 arch/mips/ath79/clock.c ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ref_div 304 arch/mips/ath79/clock.c ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint, ref_div 356 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ref_div 371 arch/mips/ath79/clock.c ref_div = (pll >> QCA953X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ref_div 378 arch/mips/ath79/clock.c cpu_pll = nint * ref_rate / ref_div; ref_div 379 arch/mips/ath79/clock.c cpu_pll += frac * (ref_rate >> 6) / ref_div; ref_div 385 arch/mips/ath79/clock.c ref_div = (pll >> QCA953X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ref_div 392 arch/mips/ath79/clock.c ddr_pll = nint * ref_rate / ref_div; ref_div 393 arch/mips/ath79/clock.c ddr_pll += frac * (ref_rate >> 6) / (ref_div << 4); ref_div 439 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv; ref_div 454 arch/mips/ath79/clock.c ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ref_div 461 arch/mips/ath79/clock.c cpu_pll = nint * ref_rate / ref_div; ref_div 462 arch/mips/ath79/clock.c cpu_pll += frac * ref_rate / (ref_div * (1 << 6)); ref_div 468 arch/mips/ath79/clock.c ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ref_div 475 arch/mips/ath79/clock.c ddr_pll = nint * ref_rate / ref_div; ref_div 476 arch/mips/ath79/clock.c ddr_pll += frac * ref_rate / (ref_div * (1 << 10)); ref_div 522 arch/mips/ath79/clock.c u32 pll, out_div, ref_div, nint, hfrac, lfrac, clk_ctrl, postdiv; ref_div 547 arch/mips/ath79/clock.c ref_div = (pll >> QCA956X_PLL_CPU_CONFIG_REFDIV_SHIFT) & ref_div 558 arch/mips/ath79/clock.c cpu_pll = nint * ref_rate / ref_div; ref_div 559 arch/mips/ath79/clock.c cpu_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); ref_div 560 arch/mips/ath79/clock.c cpu_pll += (hfrac >> 13) * ref_rate / ref_div; ref_div 566 arch/mips/ath79/clock.c ref_div = (pll >> QCA956X_PLL_DDR_CONFIG_REFDIV_SHIFT) & ref_div 576 arch/mips/ath79/clock.c ddr_pll = nint * ref_rate / ref_div; ref_div 577 arch/mips/ath79/clock.c ddr_pll += (lfrac * ref_rate) / ((ref_div * 25) << 13); ref_div 578 arch/mips/ath79/clock.c ddr_pll += (hfrac >> 13) * ref_rate / ref_div; ref_div 311 arch/mips/netlogic/xlp/nlm_hal.c u32 mdiv, fdiv, pll_out_freq_den, reg_select, ref_div, pic_div; ref_div 328 arch/mips/netlogic/xlp/nlm_hal.c ref_div = 3; ref_div 332 arch/mips/netlogic/xlp/nlm_hal.c ref_div = 1; ref_div 336 arch/mips/netlogic/xlp/nlm_hal.c ref_div = 1; ref_div 340 arch/mips/netlogic/xlp/nlm_hal.c ref_div = 3; ref_div 432 arch/mips/netlogic/xlp/nlm_hal.c pll_out_freq_den = (1 << vco_post_div) * pll_post_div * ref_div; ref_div 1030 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->ref_div = args.v3.ucRefDiv; ref_div 1050 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->ref_div = args.v5.ucRefDiv; ref_div 1074 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.c dividers->ref_div = args.v6_out.ucPllRefDiv; ref_div 43 drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.h u32 ref_div; ref_div 85 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c unsigned *fb_div, unsigned *ref_div) ref_div 91 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *ref_div = min(max(DIV_ROUND_CLOSEST(den, post_div), 1u), ref_div_max); ref_div 92 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); ref_div 96 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *ref_div = DIV_ROUND_CLOSEST(*ref_div * fb_div_max, *fb_div); ref_div 127 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c unsigned ref_div_min, ref_div_max, ref_div; ref_div 202 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div_max, &fb_div, &ref_div); ref_div 204 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c (ref_div * post_div)); ref_div 217 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c &fb_div, &ref_div); ref_div 221 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c amdgpu_pll_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); ref_div 229 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div *= tmp; ref_div 244 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c (ref_div * post_div * 10); ref_div 245 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c *ref_div_p = ref_div; ref_div 250 drivers/gpu/drm/amd/amdgpu/amdgpu_pll.c ref_div, post_div); ref_div 582 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c u32 ref_div, ref_div 609 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v1.usRefDiv = cpu_to_le16(ref_div); ref_div 619 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v2.usRefDiv = cpu_to_le16(ref_div); ref_div 629 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v3.usRefDiv = cpu_to_le16(ref_div); ref_div 646 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v5.ucRefDiv = ref_div; ref_div 676 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c args.v6.ucRefDiv = ref_div; ref_div 826 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; ref_div 855 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); ref_div 862 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c ref_div, fb_div, frac_fb_div, post_div, ref_div 875 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c step_size = (4 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / ref_div 878 drivers/gpu/drm/amd/amdgpu/atombios_crtc.c step_size = (2 * amount * ref_div * ((u32)amdgpu_crtc->ss.rate * 2048)) / ref_div 48 drivers/gpu/drm/amd/amdgpu/atombios_crtc.h u32 ref_div, ref_div 5268 drivers/gpu/drm/amd/amdgpu/si_dpm.c reference_divider = 1 + dividers.ref_div; ref_div 5275 drivers/gpu/drm/amd/amdgpu/si_dpm.c spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); ref_div 7376 drivers/gpu/drm/amd/amdgpu/si_dpm.c pi->ref_div = dividers.ref_div + 1; ref_div 7378 drivers/gpu/drm/amd/amdgpu/si_dpm.c pi->ref_div = R600_REFERENCEDIVIDER_DFLT; ref_div 571 drivers/gpu/drm/amd/amdgpu/si_dpm.h u32 ref_div; ref_div 535 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c uint32_t ref_div = 0; ref_div 538 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c REG_GET_2(DCHUBBUB_GLOBAL_TIMER_CNTL, DCHUBBUB_GLOBAL_TIMER_REFDIV, &ref_div, ref_div 542 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubbub.c if (ref_div == 2) ref_div 829 drivers/gpu/drm/radeon/atombios_crtc.c u32 ref_div, ref_div 856 drivers/gpu/drm/radeon/atombios_crtc.c args.v1.usRefDiv = cpu_to_le16(ref_div); ref_div 866 drivers/gpu/drm/radeon/atombios_crtc.c args.v2.usRefDiv = cpu_to_le16(ref_div); ref_div 876 drivers/gpu/drm/radeon/atombios_crtc.c args.v3.usRefDiv = cpu_to_le16(ref_div); ref_div 893 drivers/gpu/drm/radeon/atombios_crtc.c args.v5.ucRefDiv = ref_div; ref_div 922 drivers/gpu/drm/radeon/atombios_crtc.c args.v6.ucRefDiv = ref_div; ref_div 1072 drivers/gpu/drm/radeon/atombios_crtc.c u32 ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; ref_div 1104 drivers/gpu/drm/radeon/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); ref_div 1107 drivers/gpu/drm/radeon/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); ref_div 1110 drivers/gpu/drm/radeon/atombios_crtc.c &fb_div, &frac_fb_div, &ref_div, &post_div); ref_div 1117 drivers/gpu/drm/radeon/atombios_crtc.c ref_div, fb_div, frac_fb_div, post_div, ref_div 1131 drivers/gpu/drm/radeon/atombios_crtc.c step_size = (4 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / ref_div 1134 drivers/gpu/drm/radeon/atombios_crtc.c step_size = (2 * amount * ref_div * ((u32)radeon_crtc->ss.rate * 2048)) / ref_div 2611 drivers/gpu/drm/radeon/btc_dpm.c pi->ref_div = dividers.ref_div + 1; ref_div 2613 drivers/gpu/drm/radeon/btc_dpm.c pi->ref_div = R600_REFERENCEDIVIDER_DFLT; ref_div 3180 drivers/gpu/drm/radeon/ci_dpm.c reference_divider = 1 + dividers.ref_div; ref_div 520 drivers/gpu/drm/radeon/cypress_dpm.c mpll_ad_func_cntl |= CLKR(dividers.ref_div); ref_div 537 drivers/gpu/drm/radeon/cypress_dpm.c mpll_dq_func_cntl |= CLKR(dividers.ref_div); ref_div 561 drivers/gpu/drm/radeon/cypress_dpm.c u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); ref_div 2059 drivers/gpu/drm/radeon/cypress_dpm.c pi->ref_div = dividers.ref_div + 1; ref_div 2061 drivers/gpu/drm/radeon/cypress_dpm.c pi->ref_div = R600_REFERENCEDIVIDER_DFLT; ref_div 2022 drivers/gpu/drm/radeon/ni_dpm.c reference_divider = 1 + dividers.ref_div; ref_div 2030 drivers/gpu/drm/radeon/ni_dpm.c spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); ref_div 2202 drivers/gpu/drm/radeon/ni_dpm.c mpll_ad_func_cntl |= CLKR(dividers.ref_div); ref_div 2219 drivers/gpu/drm/radeon/ni_dpm.c mpll_dq_func_cntl |= CLKR(dividers.ref_div); ref_div 2243 drivers/gpu/drm/radeon/ni_dpm.c u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); ref_div 4108 drivers/gpu/drm/radeon/ni_dpm.c pi->ref_div = dividers.ref_div + 1; ref_div 4110 drivers/gpu/drm/radeon/ni_dpm.c pi->ref_div = R600_REFERENCEDIVIDER_DFLT; ref_div 205 drivers/gpu/drm/radeon/r600.c unsigned fb_div = 0, ref_div, vclk_div = 0, dclk_div = 0; ref_div 228 drivers/gpu/drm/radeon/r600.c ref_div = 34; ref_div 230 drivers/gpu/drm/radeon/r600.c ref_div = 4; ref_div 233 drivers/gpu/drm/radeon/r600.c ref_div + 1, 0xFFF, 2, 30, ~0, ref_div 258 drivers/gpu/drm/radeon/r600.c UPLL_REF_DIV(ref_div), ref_div 2877 drivers/gpu/drm/radeon/radeon_atombios.c dividers->ref_div = args.v2.ucAction; ref_div 2897 drivers/gpu/drm/radeon/radeon_atombios.c dividers->ref_div = args.v3.ucRefDiv; ref_div 2917 drivers/gpu/drm/radeon/radeon_atombios.c dividers->ref_div = args.v5.ucRefDiv; ref_div 2942 drivers/gpu/drm/radeon/radeon_atombios.c dividers->ref_div = args.v6_out.ucPllRefDiv; ref_div 42 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t fb_div, ref_div, post_div, sclk; ref_div 49 drivers/gpu/drm/radeon/radeon_clocks.c ref_div = ref_div 52 drivers/gpu/drm/radeon/radeon_clocks.c if (ref_div == 0) ref_div 55 drivers/gpu/drm/radeon/radeon_clocks.c sclk = fb_div / ref_div; ref_div 72 drivers/gpu/drm/radeon/radeon_clocks.c uint32_t fb_div, ref_div, post_div, mclk; ref_div 79 drivers/gpu/drm/radeon/radeon_clocks.c ref_div = ref_div 82 drivers/gpu/drm/radeon/radeon_clocks.c if (ref_div == 0) ref_div 85 drivers/gpu/drm/radeon/radeon_clocks.c mclk = fb_div / ref_div; ref_div 355 drivers/gpu/drm/radeon/radeon_clocks.c int ref_div = spll->reference_div; ref_div 357 drivers/gpu/drm/radeon/radeon_clocks.c if (!ref_div) ref_div 358 drivers/gpu/drm/radeon/radeon_clocks.c ref_div = ref_div 374 drivers/gpu/drm/radeon/radeon_clocks.c req_clock *= ref_div; ref_div 382 drivers/gpu/drm/radeon/radeon_clocks.c req_clock /= ref_div; ref_div 926 drivers/gpu/drm/radeon/radeon_display.c unsigned *fb_div, unsigned *ref_div) ref_div 932 drivers/gpu/drm/radeon/radeon_display.c *ref_div = min(max(den/post_div, 1u), ref_div_max); ref_div 933 drivers/gpu/drm/radeon/radeon_display.c *fb_div = DIV_ROUND_CLOSEST(nom * *ref_div * post_div, den); ref_div 937 drivers/gpu/drm/radeon/radeon_display.c *ref_div = (*ref_div * fb_div_max)/(*fb_div); ref_div 968 drivers/gpu/drm/radeon/radeon_display.c unsigned ref_div_min, ref_div_max, ref_div; ref_div 1046 drivers/gpu/drm/radeon/radeon_display.c ref_div_max, &fb_div, &ref_div); ref_div 1048 drivers/gpu/drm/radeon/radeon_display.c (ref_div * post_div)); ref_div 1061 drivers/gpu/drm/radeon/radeon_display.c &fb_div, &ref_div); ref_div 1065 drivers/gpu/drm/radeon/radeon_display.c avivo_reduce_ratio(&fb_div, &ref_div, fb_div_min, ref_div_min); ref_div 1073 drivers/gpu/drm/radeon/radeon_display.c ref_div *= tmp; ref_div 1088 drivers/gpu/drm/radeon/radeon_display.c (ref_div * post_div * 10); ref_div 1089 drivers/gpu/drm/radeon/radeon_display.c *ref_div_p = ref_div; ref_div 1094 drivers/gpu/drm/radeon/radeon_display.c ref_div, post_div); ref_div 1171 drivers/gpu/drm/radeon/radeon_display.c uint32_t ref_div; ref_div 1189 drivers/gpu/drm/radeon/radeon_display.c for (ref_div = min_ref_div; ref_div <= max_ref_div; ++ref_div) { ref_div 1191 drivers/gpu/drm/radeon/radeon_display.c uint32_t pll_in = pll->reference_freq / ref_div; ref_div 1208 drivers/gpu/drm/radeon/radeon_display.c vco = radeon_div(tmp, ref_div); ref_div 1222 drivers/gpu/drm/radeon/radeon_display.c current_freq = radeon_div(tmp, ref_div * post_div); ref_div 1238 drivers/gpu/drm/radeon/radeon_display.c best_ref_div = ref_div; ref_div 1247 drivers/gpu/drm/radeon/radeon_display.c best_ref_div = ref_div; ref_div 1253 drivers/gpu/drm/radeon/radeon_display.c } else if (((pll->flags & RADEON_PLL_PREFER_LOW_REF_DIV) && (ref_div < best_ref_div)) || ref_div 1254 drivers/gpu/drm/radeon/radeon_display.c ((pll->flags & RADEON_PLL_PREFER_HIGH_REF_DIV) && (ref_div > best_ref_div)) || ref_div 1260 drivers/gpu/drm/radeon/radeon_display.c best_ref_div = ref_div; ref_div 266 drivers/gpu/drm/radeon/radeon_legacy_crtc.c static uint8_t radeon_compute_pll_gain(uint16_t ref_freq, uint16_t ref_div, ref_div 271 drivers/gpu/drm/radeon/radeon_legacy_crtc.c if (!ref_div) ref_div 274 drivers/gpu/drm/radeon/radeon_legacy_crtc.c vcoFreq = ((unsigned)ref_freq * fb_div) / ref_div; ref_div 595 drivers/gpu/drm/radeon/radeon_mode.h u32 ref_div; ref_div 88 drivers/gpu/drm/radeon/rs780_dpm.c r600_engine_clock_entry_set_reference_divider(rdev, 0, dividers.ref_div); ref_div 455 drivers/gpu/drm/radeon/rs780_dpm.c if ((min_dividers.ref_div != max_dividers.ref_div) || ref_div 457 drivers/gpu/drm/radeon/rs780_dpm.c (max_dividers.ref_div != current_max_dividers.ref_div) || ref_div 990 drivers/gpu/drm/radeon/rs780_dpm.c u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; ref_div 994 drivers/gpu/drm/radeon/rs780_dpm.c (post_div * ref_div); ref_div 1012 drivers/gpu/drm/radeon/rs780_dpm.c u32 ref_div = ((func_cntl & SPLL_REF_DIV_MASK) >> SPLL_REF_DIV_SHIFT) + 1; ref_div 1016 drivers/gpu/drm/radeon/rs780_dpm.c (post_div * ref_div); ref_div 530 drivers/gpu/drm/radeon/rv6xx_dpm.c (dividers->ref_div + 1); ref_div 567 drivers/gpu/drm/radeon/rv6xx_dpm.c (ref_clk / (dividers.ref_div + 1)), ref_div 573 drivers/gpu/drm/radeon/rv6xx_dpm.c (ref_clk / (dividers.ref_div + 1))); ref_div 606 drivers/gpu/drm/radeon/rv6xx_dpm.c rv6xx_memory_clock_entry_set_reference_divider(rdev, entry, dividers.ref_div); ref_div 685 drivers/gpu/drm/radeon/rv6xx_dpm.c (ref_clk / (dividers.ref_div + 1)), ref_div 691 drivers/gpu/drm/radeon/rv6xx_dpm.c (ref_clk / (dividers.ref_div + 1))); ref_div 1960 drivers/gpu/drm/radeon/rv6xx_dpm.c pi->spll_ref_div = dividers.ref_div + 1; ref_div 1967 drivers/gpu/drm/radeon/rv6xx_dpm.c pi->mpll_ref_div = dividers.ref_div + 1; ref_div 61 drivers/gpu/drm/radeon/rv730_dpm.c reference_divider = 1 + dividers.ref_div; ref_div 79 drivers/gpu/drm/radeon/rv730_dpm.c spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); ref_div 139 drivers/gpu/drm/radeon/rv730_dpm.c reference_divider = dividers.ref_div + 1; ref_div 154 drivers/gpu/drm/radeon/rv730_dpm.c mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div); ref_div 141 drivers/gpu/drm/radeon/rv740_dpm.c reference_divider = 1 + dividers.ref_div; ref_div 148 drivers/gpu/drm/radeon/rv740_dpm.c spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); ref_div 216 drivers/gpu/drm/radeon/rv740_dpm.c mpll_ad_func_cntl |= CLKR(dividers.ref_div); ref_div 233 drivers/gpu/drm/radeon/rv740_dpm.c mpll_dq_func_cntl |= CLKR(dividers.ref_div); ref_div 252 drivers/gpu/drm/radeon/rv740_dpm.c u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); ref_div 333 drivers/gpu/drm/radeon/rv770_dpm.c reference_divider = dividers->ref_div; ref_div 414 drivers/gpu/drm/radeon/rv770_dpm.c if ((dividers.ref_div < 1) || (dividers.ref_div > 5)) ref_div 432 drivers/gpu/drm/radeon/rv770_dpm.c mpll_ad_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); ref_div 460 drivers/gpu/drm/radeon/rv770_dpm.c mpll_dq_func_cntl |= CLKR(encoded_reference_dividers[dividers.ref_div - 1]); ref_div 510 drivers/gpu/drm/radeon/rv770_dpm.c reference_divider = 1 + dividers.ref_div; ref_div 526 drivers/gpu/drm/radeon/rv770_dpm.c spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); ref_div 810 drivers/gpu/drm/radeon/rv770_dpm.c (MPLL_LOCK_TIME(R600_MPLLLOCKTIME_DFLT * pi->ref_div) | ref_div 2376 drivers/gpu/drm/radeon/rv770_dpm.c pi->ref_div = dividers.ref_div + 1; ref_div 2378 drivers/gpu/drm/radeon/rv770_dpm.c pi->ref_div = R600_REFERENCEDIVIDER_DFLT; ref_div 115 drivers/gpu/drm/radeon/rv770_dpm.h u32 ref_div; ref_div 4806 drivers/gpu/drm/radeon/si_dpm.c reference_divider = 1 + dividers.ref_div; ref_div 4813 drivers/gpu/drm/radeon/si_dpm.c spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); ref_div 6986 drivers/gpu/drm/radeon/si_dpm.c pi->ref_div = dividers.ref_div + 1; ref_div 6988 drivers/gpu/drm/radeon/si_dpm.c pi->ref_div = R600_REFERENCEDIVIDER_DFLT; ref_div 72 drivers/media/dvb-frontends/tda8261.c static const u8 ref_div[] = { 0x00, 0x01, 0x02, 0x05, 0x07 }; ref_div 109 drivers/media/dvb-frontends/tda8261.c buf[2] = (0x01 << 7) | ((ref_div[config->step_size] & 0x07) << 1); ref_div 307 drivers/net/wireless/ath/ath9k/ar9002_phy.c int ref_div = 5; ref_div 313 drivers/net/wireless/ath/ath9k/ar9002_phy.c ref_div = 10; ref_div 320 drivers/net/wireless/ath/ath9k/ar9002_phy.c pll = SM(ref_div, AR_RTC_9160_PLL_REFDIV); ref_div 51 drivers/video/fbdev/aty/atyfb.h int ref_div; ref_div 3374 drivers/video/fbdev/aty/atyfb_base.c par->pll_limits.ref_div = pll_block.ref_divider; ref_div 582 drivers/video/fbdev/aty/radeon_base.c unsigned sclk, mclk, tmp, ref_div; ref_div 692 drivers/video/fbdev/aty/radeon_base.c ref_div = INPLL(PPLL_REF_DIV) & 0x3ff; ref_div 702 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div = ref_div; ref_div 771 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div = INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK; ref_div 794 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div = BIOS_IN16(pll_info_block + 0x10); ref_div 829 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div, ref_div 1624 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div, rinfo->pll.ref_clk, ref_div 1634 drivers/video/fbdev/aty/radeon_base.c rinfo->pll.ref_div, rinfo->pll.ref_clk, ref_div 1637 drivers/video/fbdev/aty/radeon_base.c fb_div = round_div(rinfo->pll.ref_div*pll_output_freq, ref_div 1639 drivers/video/fbdev/aty/radeon_base.c regs->ppll_ref_div = rinfo->pll.ref_div; ref_div 669 drivers/video/fbdev/aty/radeon_monitor.c rinfo->panel_info.ref_divider = rinfo->pll.ref_div; ref_div 1651 drivers/video/fbdev/aty/radeon_pm.c tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; ref_div 2196 drivers/video/fbdev/aty/radeon_pm.c OUTPLL(pllPPLL_REF_DIV, rinfo->pll.ref_div); ref_div 2453 drivers/video/fbdev/aty/radeon_pm.c tmp = (tmp & ~PPLL_REF_DIV_MASK) | rinfo->pll.ref_div; ref_div 142 drivers/video/fbdev/aty/radeonfb.h int ref_div;