ref_and_mask      251 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	u32 ref_and_mask;
ref_and_mask      254 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA0_MASK;
ref_and_mask      256 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 		ref_and_mask = GPU_HDP_FLUSH_DONE__SDMA1_MASK;
ref_and_mask      261 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
ref_and_mask      262 drivers/gpu/drm/amd/amdgpu/cik_sdma.c 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
ref_and_mask     4426 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 	u32 ref_and_mask, reg_mem_engine;
ref_and_mask     4432 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
ref_and_mask     4435 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
ref_and_mask     4442 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
ref_and_mask     4449 drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c 			       ref_and_mask, ref_and_mask, 0x20);
ref_and_mask     2133 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	u32 ref_and_mask;
ref_and_mask     2139 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
ref_and_mask     2142 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 			ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
ref_and_mask     2148 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 		ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
ref_and_mask     2157 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	amdgpu_ring_write(ring, ref_and_mask);
ref_and_mask     2158 drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c 	amdgpu_ring_write(ring, ref_and_mask);
ref_and_mask     6073 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	u32 ref_and_mask, reg_mem_engine;
ref_and_mask     6079 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			ref_and_mask = GPU_HDP_FLUSH_DONE__CP2_MASK << ring->pipe;
ref_and_mask     6082 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 			ref_and_mask = GPU_HDP_FLUSH_DONE__CP6_MASK << ring->pipe;
ref_and_mask     6089 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 		ref_and_mask = GPU_HDP_FLUSH_DONE__CP0_MASK;
ref_and_mask     6099 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	amdgpu_ring_write(ring, ref_and_mask);
ref_and_mask     6100 drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c 	amdgpu_ring_write(ring, ref_and_mask);
ref_and_mask     4985 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 	u32 ref_and_mask, reg_mem_engine;
ref_and_mask     4991 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
ref_and_mask     4994 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
ref_and_mask     5001 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 		ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
ref_and_mask     5008 drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c 			      ref_and_mask, ref_and_mask, 0x20);
ref_and_mask      280 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	u32 ref_and_mask = 0;
ref_and_mask      283 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
ref_and_mask      285 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
ref_and_mask      292 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
ref_and_mask      293 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
ref_and_mask      454 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	u32 ref_and_mask = 0;
ref_and_mask      457 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
ref_and_mask      459 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 		ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
ref_and_mask      466 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
ref_and_mask      467 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
ref_and_mask      749 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	u32 ref_and_mask = 0;
ref_and_mask      752 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 	ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0 << ring->me;
ref_and_mask      757 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c 			       ref_and_mask, ref_and_mask, 10);
ref_and_mask      427 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	u32 ref_and_mask = 0;
ref_and_mask      431 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		ref_and_mask = nbio_hf_reg->ref_and_mask_sdma0;
ref_and_mask      433 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 		ref_and_mask = nbio_hf_reg->ref_and_mask_sdma1;
ref_and_mask      440 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	amdgpu_ring_write(ring, ref_and_mask); /* reference */
ref_and_mask      441 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c 	amdgpu_ring_write(ring, ref_and_mask); /* mask */
ref_and_mask     3512 drivers/gpu/drm/radeon/cik.c 	u32 ref_and_mask;
ref_and_mask     3520 drivers/gpu/drm/radeon/cik.c 			ref_and_mask = CP2 << ring->pipe;
ref_and_mask     3523 drivers/gpu/drm/radeon/cik.c 			ref_and_mask = CP6 << ring->pipe;
ref_and_mask     3530 drivers/gpu/drm/radeon/cik.c 		ref_and_mask = CP0;
ref_and_mask     3540 drivers/gpu/drm/radeon/cik.c 	radeon_ring_write(ring, ref_and_mask);
ref_and_mask     3541 drivers/gpu/drm/radeon/cik.c 	radeon_ring_write(ring, ref_and_mask);
ref_and_mask      175 drivers/gpu/drm/radeon/cik_sdma.c 	u32 ref_and_mask;
ref_and_mask      178 drivers/gpu/drm/radeon/cik_sdma.c 		ref_and_mask = SDMA0;
ref_and_mask      180 drivers/gpu/drm/radeon/cik_sdma.c 		ref_and_mask = SDMA1;
ref_and_mask      185 drivers/gpu/drm/radeon/cik_sdma.c 	radeon_ring_write(ring, ref_and_mask); /* reference */
ref_and_mask      186 drivers/gpu/drm/radeon/cik_sdma.c 	radeon_ring_write(ring, ref_and_mask); /* mask */