reader_wm_sets    559 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		if (ranges->reader_wm_sets[i].wm_inst > 3)
reader_wm_sets    563 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 					ranges->reader_wm_sets[i].wm_inst;
reader_wm_sets    565 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
reader_wm_sets    567 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
reader_wm_sets    569 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
reader_wm_sets    571 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 				ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
reader_wm_sets    681 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 		if (ranges->reader_wm_sets[i].wm_inst > 3)
reader_wm_sets    685 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 					ranges->reader_wm_sets[i].wm_inst;
reader_wm_sets    687 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			ranges->reader_wm_sets[i].max_drain_clk_mhz * 1000;
reader_wm_sets    689 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			ranges->reader_wm_sets[i].min_drain_clk_mhz * 1000;
reader_wm_sets    691 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			ranges->reader_wm_sets[i].max_fill_clk_mhz * 1000;
reader_wm_sets    693 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_pp_smu.c 			ranges->reader_wm_sets[i].min_fill_clk_mhz * 1000;
reader_wm_sets   1527 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[0].wm_inst = WM_A;
reader_wm_sets   1528 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[0].min_drain_clk_mhz = min_dcfclk_khz / 1000;
reader_wm_sets   1529 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[0].max_drain_clk_mhz = overdrive / 1000;
reader_wm_sets   1530 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[0].min_fill_clk_mhz = min_fclk_khz / 1000;
reader_wm_sets   1531 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[0].max_fill_clk_mhz = overdrive / 1000;
reader_wm_sets   1539 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		ranges.reader_wm_sets[0].wm_inst = WM_A;
reader_wm_sets   1540 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		ranges.reader_wm_sets[0].min_drain_clk_mhz = 300;
reader_wm_sets   1541 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		ranges.reader_wm_sets[0].max_drain_clk_mhz = 5000;
reader_wm_sets   1542 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		ranges.reader_wm_sets[0].min_fill_clk_mhz = 800;
reader_wm_sets   1543 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 		ranges.reader_wm_sets[0].max_fill_clk_mhz = 5000;
reader_wm_sets   1551 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[1] = ranges.writer_wm_sets[0];
reader_wm_sets   1552 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[1].wm_inst = WM_B;
reader_wm_sets   1554 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[2] = ranges.writer_wm_sets[0];
reader_wm_sets   1555 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[2].wm_inst = WM_C;
reader_wm_sets   1557 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[3] = ranges.writer_wm_sets[0];
reader_wm_sets   1558 drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c 	ranges.reader_wm_sets[3].wm_inst = WM_D;
reader_wm_sets    425 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		ranges->reader_wm_sets[num_valid_sets].wm_inst = bw_params->wm_table.entries[i].wm_inst;
reader_wm_sets    426 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		ranges->reader_wm_sets[num_valid_sets].wm_type = bw_params->wm_table.entries[i].wm_type;;
reader_wm_sets    428 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		ranges->reader_wm_sets[num_valid_sets].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
reader_wm_sets    429 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		ranges->reader_wm_sets[num_valid_sets].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
reader_wm_sets    432 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 		if (ranges->reader_wm_sets[num_valid_sets].wm_type == WM_TYPE_PSTATE_CHG) {
reader_wm_sets    434 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = 0;
reader_wm_sets    437 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 				ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = bw_params->clk_table.entries[i - 1].fclk_mhz + 1;
reader_wm_sets    439 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = bw_params->clk_table.entries[i].fclk_mhz;
reader_wm_sets    443 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			ranges->reader_wm_sets[num_valid_sets].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
reader_wm_sets    444 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			ranges->reader_wm_sets[num_valid_sets].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
reader_wm_sets    447 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 			ranges->reader_wm_sets[num_valid_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
reader_wm_sets    456 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	ranges->reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
reader_wm_sets    457 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	ranges->reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
reader_wm_sets    458 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
reader_wm_sets    459 drivers/gpu/drm/amd/display/dc/clk_mgr/dcn21/rn_clk_mgr.c 	ranges->reader_wm_sets[ranges->num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
reader_wm_sets   3577 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			ranges.reader_wm_sets[0].wm_inst = i;
reader_wm_sets   3578 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			ranges.reader_wm_sets[0].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
reader_wm_sets   3579 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			ranges.reader_wm_sets[0].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
reader_wm_sets   3580 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
reader_wm_sets   3581 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			ranges.reader_wm_sets[0].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
reader_wm_sets   3586 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				ranges.reader_wm_sets[i].wm_inst = i;
reader_wm_sets   3587 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				ranges.reader_wm_sets[i].min_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
reader_wm_sets   3588 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				ranges.reader_wm_sets[i].max_drain_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
reader_wm_sets   3589 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				ranges.reader_wm_sets[i].min_fill_clk_mhz = (i > 0) ? (loaded_bb->clock_limits[i - 1].dram_speed_mts / 16) + 1 : 0;
reader_wm_sets   3590 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 				ranges.reader_wm_sets[i].max_fill_clk_mhz = loaded_bb->clock_limits[i].dram_speed_mts / 16;
reader_wm_sets   3595 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			ranges.reader_wm_sets[0].min_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MIN;
reader_wm_sets   3596 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_resource.c 			ranges.reader_wm_sets[ranges.num_reader_wm_sets - 1].max_fill_clk_mhz = PP_SMU_WM_SET_RANGE_CLK_UNCONSTRAINED_MAX;
reader_wm_sets     96 drivers/gpu/drm/amd/display/dc/dm_pp_smu.h 	struct pp_smu_wm_set_range reader_wm_sets[MAX_WATERMARK_SETS];