rcg 39 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 44 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); rcg 47 drivers/clk/qcom/clk-rcg.c ns = ns_to_src(&rcg->s, ns); rcg 49 drivers/clk/qcom/clk-rcg.c if (ns == rcg->s.parent_map[i].cfg) rcg 58 drivers/clk/qcom/clk-rcg.c static int reg_to_bank(struct clk_dyn_rcg *rcg, u32 bank) rcg 60 drivers/clk/qcom/clk-rcg.c bank &= BIT(rcg->mux_sel_bit); rcg 66 drivers/clk/qcom/clk-rcg.c struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); rcg 73 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); rcg 76 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); rcg 77 drivers/clk/qcom/clk-rcg.c s = &rcg->s[bank]; rcg 79 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); rcg 96 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 99 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); rcg 100 drivers/clk/qcom/clk-rcg.c ns = src_to_ns(&rcg->s, rcg->s.parent_map[index].cfg, ns); rcg 101 drivers/clk/qcom/clk-rcg.c regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); rcg 198 drivers/clk/qcom/clk-rcg.c static int configure_bank(struct clk_dyn_rcg *rcg, const struct freq_tbl *f) rcg 207 drivers/clk/qcom/clk-rcg.c bool banked_mn = !!rcg->mn[1].width; rcg 208 drivers/clk/qcom/clk-rcg.c bool banked_p = !!rcg->p[1].pre_div_width; rcg 209 drivers/clk/qcom/clk-rcg.c struct clk_hw *hw = &rcg->clkr.hw; rcg 213 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); rcg 216 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); rcg 219 drivers/clk/qcom/clk-rcg.c ns_reg = rcg->ns_reg[new_bank]; rcg 220 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, ns_reg, &ns); rcg 225 drivers/clk/qcom/clk-rcg.c mn = &rcg->mn[new_bank]; rcg 226 drivers/clk/qcom/clk-rcg.c md_reg = rcg->md_reg[new_bank]; rcg 229 drivers/clk/qcom/clk-rcg.c ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); rcg 233 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, md_reg, &md); rcg 237 drivers/clk/qcom/clk-rcg.c ret = regmap_write(rcg->clkr.regmap, md_reg, md); rcg 241 drivers/clk/qcom/clk-rcg.c ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); rcg 246 drivers/clk/qcom/clk-rcg.c if (rcg->ns_reg[0] != rcg->ns_reg[1]) { rcg 248 drivers/clk/qcom/clk-rcg.c ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); rcg 253 drivers/clk/qcom/clk-rcg.c ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, rcg 260 drivers/clk/qcom/clk-rcg.c ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); rcg 266 drivers/clk/qcom/clk-rcg.c p = &rcg->p[new_bank]; rcg 270 drivers/clk/qcom/clk-rcg.c s = &rcg->s[new_bank]; rcg 275 drivers/clk/qcom/clk-rcg.c ret = regmap_write(rcg->clkr.regmap, ns_reg, ns); rcg 280 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); rcg 283 drivers/clk/qcom/clk-rcg.c reg ^= BIT(rcg->mux_sel_bit); rcg 284 drivers/clk/qcom/clk-rcg.c ret = regmap_write(rcg->clkr.regmap, rcg->bank_reg, reg); rcg 293 drivers/clk/qcom/clk-rcg.c struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); rcg 297 drivers/clk/qcom/clk-rcg.c bool banked_mn = !!rcg->mn[1].width; rcg 298 drivers/clk/qcom/clk-rcg.c bool banked_p = !!rcg->p[1].pre_div_width; rcg 300 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); rcg 301 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); rcg 303 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); rcg 306 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); rcg 307 drivers/clk/qcom/clk-rcg.c f.m = md_to_m(&rcg->mn[bank], md); rcg 308 drivers/clk/qcom/clk-rcg.c f.n = ns_m_to_n(&rcg->mn[bank], ns, f.m); rcg 312 drivers/clk/qcom/clk-rcg.c f.pre_div = ns_to_pre_div(&rcg->p[bank], ns) + 1; rcg 314 drivers/clk/qcom/clk-rcg.c f.src = qcom_find_src_index(hw, rcg->s[bank].parent_map, index); rcg 315 drivers/clk/qcom/clk-rcg.c return configure_bank(rcg, &f); rcg 344 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 346 drivers/clk/qcom/clk-rcg.c struct mn *mn = &rcg->mn; rcg 348 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); rcg 349 drivers/clk/qcom/clk-rcg.c pre_div = ns_to_pre_div(&rcg->p, ns); rcg 351 drivers/clk/qcom/clk-rcg.c if (rcg->mn.width) { rcg 352 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->md_reg, &md); rcg 356 drivers/clk/qcom/clk-rcg.c if (rcg->clkr.enable_reg != rcg->ns_reg) rcg 357 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &mode); rcg 369 drivers/clk/qcom/clk-rcg.c struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); rcg 373 drivers/clk/qcom/clk-rcg.c bool banked_p = !!rcg->p[1].pre_div_width; rcg 374 drivers/clk/qcom/clk-rcg.c bool banked_mn = !!rcg->mn[1].width; rcg 376 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); rcg 377 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); rcg 379 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->ns_reg[bank], &ns); rcg 383 drivers/clk/qcom/clk-rcg.c mn = &rcg->mn[bank]; rcg 384 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->md_reg[bank], &md); rcg 388 drivers/clk/qcom/clk-rcg.c if (rcg->ns_reg[0] != rcg->ns_reg[1]) rcg 394 drivers/clk/qcom/clk-rcg.c pre_div = ns_to_pre_div(&rcg->p[bank], ns); rcg 438 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 440 drivers/clk/qcom/clk-rcg.c return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, rcg 441 drivers/clk/qcom/clk-rcg.c rcg->s.parent_map); rcg 447 drivers/clk/qcom/clk-rcg.c struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); rcg 452 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->bank_reg, ®); rcg 453 drivers/clk/qcom/clk-rcg.c bank = reg_to_bank(rcg, reg); rcg 454 drivers/clk/qcom/clk-rcg.c s = &rcg->s[bank]; rcg 456 drivers/clk/qcom/clk-rcg.c return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, s->parent_map); rcg 462 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 463 drivers/clk/qcom/clk-rcg.c const struct freq_tbl *f = rcg->freq_tbl; rcg 465 drivers/clk/qcom/clk-rcg.c int index = qcom_find_src_index(hw, rcg->s.parent_map, f->src); rcg 474 drivers/clk/qcom/clk-rcg.c static int __clk_rcg_set_rate(struct clk_rcg *rcg, const struct freq_tbl *f) rcg 477 drivers/clk/qcom/clk-rcg.c struct mn *mn = &rcg->mn; rcg 481 drivers/clk/qcom/clk-rcg.c if (rcg->mn.reset_in_cc) rcg 482 drivers/clk/qcom/clk-rcg.c reset_reg = rcg->clkr.enable_reg; rcg 484 drivers/clk/qcom/clk-rcg.c reset_reg = rcg->ns_reg; rcg 486 drivers/clk/qcom/clk-rcg.c if (rcg->mn.width) { rcg 488 drivers/clk/qcom/clk-rcg.c regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, mask); rcg 490 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->md_reg, &md); rcg 492 drivers/clk/qcom/clk-rcg.c regmap_write(rcg->clkr.regmap, rcg->md_reg, md); rcg 494 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); rcg 496 drivers/clk/qcom/clk-rcg.c if (rcg->clkr.enable_reg != rcg->ns_reg) { rcg 497 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->clkr.enable_reg, &ctl); rcg 499 drivers/clk/qcom/clk-rcg.c regmap_write(rcg->clkr.regmap, rcg->clkr.enable_reg, ctl); rcg 505 drivers/clk/qcom/clk-rcg.c regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); rcg 508 drivers/clk/qcom/clk-rcg.c ns = pre_div_to_ns(&rcg->p, f->pre_div - 1, ns); rcg 509 drivers/clk/qcom/clk-rcg.c regmap_write(rcg->clkr.regmap, rcg->ns_reg, ns); rcg 511 drivers/clk/qcom/clk-rcg.c regmap_update_bits(rcg->clkr.regmap, reset_reg, mask, 0); rcg 519 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 522 drivers/clk/qcom/clk-rcg.c f = qcom_find_freq(rcg->freq_tbl, rate); rcg 526 drivers/clk/qcom/clk-rcg.c return __clk_rcg_set_rate(rcg, f); rcg 532 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 534 drivers/clk/qcom/clk-rcg.c return __clk_rcg_set_rate(rcg, rcg->freq_tbl); rcg 552 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 557 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); rcg 561 drivers/clk/qcom/clk-rcg.c src = ns_to_src(&rcg->s, ns); rcg 562 drivers/clk/qcom/clk-rcg.c f.pre_div = ns_to_pre_div(&rcg->p, ns) + 1; rcg 565 drivers/clk/qcom/clk-rcg.c if (src == rcg->s.parent_map[i].cfg) { rcg 566 drivers/clk/qcom/clk-rcg.c f.src = rcg->s.parent_map[i].src; rcg 567 drivers/clk/qcom/clk-rcg.c return __clk_rcg_set_rate(rcg, &f); rcg 620 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 628 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); rcg 632 drivers/clk/qcom/clk-rcg.c src = ns_to_src(&rcg->s, ns); rcg 635 drivers/clk/qcom/clk-rcg.c if (src == rcg->s.parent_map[i].cfg) { rcg 636 drivers/clk/qcom/clk-rcg.c f.src = rcg->s.parent_map[i].src; rcg 655 drivers/clk/qcom/clk-rcg.c return __clk_rcg_set_rate(rcg, &f); rcg 670 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 671 drivers/clk/qcom/clk-rcg.c int pre_div_max = BIT(rcg->p.pre_div_width); rcg 694 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 696 drivers/clk/qcom/clk-rcg.c int pre_div_max = BIT(rcg->p.pre_div_width); rcg 704 drivers/clk/qcom/clk-rcg.c ret = regmap_read(rcg->clkr.regmap, rcg->ns_reg, &ns); rcg 708 drivers/clk/qcom/clk-rcg.c ns = ns_to_src(&rcg->s, ns); rcg 711 drivers/clk/qcom/clk-rcg.c if (ns == rcg->s.parent_map[i].cfg) { rcg 712 drivers/clk/qcom/clk-rcg.c f.src = rcg->s.parent_map[i].src; rcg 721 drivers/clk/qcom/clk-rcg.c return __clk_rcg_set_rate(rcg, &f); rcg 747 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 752 drivers/clk/qcom/clk-rcg.c f = qcom_find_freq(rcg->freq_tbl, rate); rcg 757 drivers/clk/qcom/clk-rcg.c regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); rcg 758 drivers/clk/qcom/clk-rcg.c ret = __clk_rcg_set_rate(rcg, f); rcg 761 drivers/clk/qcom/clk-rcg.c regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); rcg 768 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 772 drivers/clk/qcom/clk-rcg.c return regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, gfm); rcg 777 drivers/clk/qcom/clk-rcg.c struct clk_rcg *rcg = to_clk_rcg(hw); rcg 781 drivers/clk/qcom/clk-rcg.c regmap_update_bits(rcg->clkr.regmap, rcg->ns_reg, gfm, 0); rcg 786 drivers/clk/qcom/clk-rcg.c struct clk_dyn_rcg *rcg = to_clk_dyn_rcg(hw); rcg 789 drivers/clk/qcom/clk-rcg.c f = qcom_find_freq(rcg->freq_tbl, rate); rcg 793 drivers/clk/qcom/clk-rcg.c return configure_bank(rcg, f); rcg 166 drivers/clk/qcom/clk-rcg.h struct clk_rcg2 *rcg; rcg 171 drivers/clk/qcom/clk-rcg.h { .rcg = &r##_src, .init = &r##_init } rcg 44 drivers/clk/qcom/clk-rcg2.c #define RCG_CFG_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + CFG_REG) rcg 45 drivers/clk/qcom/clk-rcg2.c #define RCG_M_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + M_REG) rcg 46 drivers/clk/qcom/clk-rcg2.c #define RCG_N_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + N_REG) rcg 47 drivers/clk/qcom/clk-rcg2.c #define RCG_D_OFFSET(rcg) ((rcg)->cmd_rcgr + (rcg)->cfg_off + D_REG) rcg 64 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 68 drivers/clk/qcom/clk-rcg2.c ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); rcg 77 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 82 drivers/clk/qcom/clk-rcg2.c ret = regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); rcg 90 drivers/clk/qcom/clk-rcg2.c if (cfg == rcg->parent_map[i].cfg) rcg 99 drivers/clk/qcom/clk-rcg2.c static int update_config(struct clk_rcg2 *rcg) rcg 103 drivers/clk/qcom/clk-rcg2.c struct clk_hw *hw = &rcg->clkr.hw; rcg 106 drivers/clk/qcom/clk-rcg2.c ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, rcg 113 drivers/clk/qcom/clk-rcg2.c ret = regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, &cmd); rcg 127 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 129 drivers/clk/qcom/clk-rcg2.c u32 cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; rcg 131 drivers/clk/qcom/clk-rcg2.c ret = regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), rcg 136 drivers/clk/qcom/clk-rcg2.c return update_config(rcg); rcg 167 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 170 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), &cfg); rcg 172 drivers/clk/qcom/clk-rcg2.c if (rcg->mnd_width) { rcg 173 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; rcg 174 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, RCG_M_OFFSET(rcg), &m); rcg 176 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, RCG_N_OFFSET(rcg), &n); rcg 184 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; rcg 197 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 214 drivers/clk/qcom/clk-rcg2.c index = qcom_find_src_index(hw, rcg->parent_map, f->src); rcg 251 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 253 drivers/clk/qcom/clk-rcg2.c return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, CEIL); rcg 259 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 261 drivers/clk/qcom/clk-rcg2.c return _freq_tbl_determine_rate(hw, rcg->freq_tbl, req, FLOOR); rcg 264 drivers/clk/qcom/clk-rcg2.c static int __clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) rcg 267 drivers/clk/qcom/clk-rcg2.c struct clk_hw *hw = &rcg->clkr.hw; rcg 268 drivers/clk/qcom/clk-rcg2.c int ret, index = qcom_find_src_index(hw, rcg->parent_map, f->src); rcg 273 drivers/clk/qcom/clk-rcg2.c if (rcg->mnd_width && f->n) { rcg 274 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; rcg 275 drivers/clk/qcom/clk-rcg2.c ret = regmap_update_bits(rcg->clkr.regmap, rcg 276 drivers/clk/qcom/clk-rcg2.c RCG_M_OFFSET(rcg), mask, f->m); rcg 280 drivers/clk/qcom/clk-rcg2.c ret = regmap_update_bits(rcg->clkr.regmap, rcg 281 drivers/clk/qcom/clk-rcg2.c RCG_N_OFFSET(rcg), mask, ~(f->n - f->m)); rcg 285 drivers/clk/qcom/clk-rcg2.c ret = regmap_update_bits(rcg->clkr.regmap, rcg 286 drivers/clk/qcom/clk-rcg2.c RCG_D_OFFSET(rcg), mask, ~f->n); rcg 291 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; rcg 294 drivers/clk/qcom/clk-rcg2.c cfg |= rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; rcg 295 drivers/clk/qcom/clk-rcg2.c if (rcg->mnd_width && f->n && (f->m != f->n)) rcg 297 drivers/clk/qcom/clk-rcg2.c return regmap_update_bits(rcg->clkr.regmap, RCG_CFG_OFFSET(rcg), rcg 301 drivers/clk/qcom/clk-rcg2.c static int clk_rcg2_configure(struct clk_rcg2 *rcg, const struct freq_tbl *f) rcg 305 drivers/clk/qcom/clk-rcg2.c ret = __clk_rcg2_configure(rcg, f); rcg 309 drivers/clk/qcom/clk-rcg2.c return update_config(rcg); rcg 315 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 320 drivers/clk/qcom/clk-rcg2.c f = qcom_find_freq_floor(rcg->freq_tbl, rate); rcg 323 drivers/clk/qcom/clk-rcg2.c f = qcom_find_freq(rcg->freq_tbl, rate); rcg 332 drivers/clk/qcom/clk-rcg2.c return clk_rcg2_configure(rcg, f); rcg 411 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 412 drivers/clk/qcom/clk-rcg2.c struct freq_tbl f = *rcg->freq_tbl; rcg 417 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; rcg 433 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg 441 drivers/clk/qcom/clk-rcg2.c return clk_rcg2_configure(rcg, &f); rcg 457 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 458 drivers/clk/qcom/clk-rcg2.c const struct freq_tbl *f = rcg->freq_tbl; rcg 462 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; rcg 464 drivers/clk/qcom/clk-rcg2.c int index = qcom_find_src_index(hw, rcg->parent_map, f->src); rcg 483 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg 511 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 512 drivers/clk/qcom/clk-rcg2.c const struct freq_tbl *f = rcg->freq_tbl; rcg 513 drivers/clk/qcom/clk-rcg2.c int index = qcom_find_src_index(hw, rcg->parent_map, f->src); rcg 515 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; rcg 535 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 536 drivers/clk/qcom/clk-rcg2.c struct freq_tbl f = *rcg->freq_tbl; rcg 538 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; rcg 545 drivers/clk/qcom/clk-rcg2.c return clk_rcg2_configure(rcg, &f); rcg 569 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 571 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; rcg 592 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 596 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; rcg 604 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); rcg 609 drivers/clk/qcom/clk-rcg2.c if (cfg == rcg->parent_map[i].cfg) { rcg 610 drivers/clk/qcom/clk-rcg2.c f.src = rcg->parent_map[i].src; rcg 611 drivers/clk/qcom/clk-rcg2.c return clk_rcg2_configure(rcg, &f); rcg 670 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 675 drivers/clk/qcom/clk-rcg2.c u32 mask = BIT(rcg->hid_width) - 1; rcg 679 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); rcg 684 drivers/clk/qcom/clk-rcg2.c if (cfg == rcg->parent_map[i].cfg) { rcg 685 drivers/clk/qcom/clk-rcg2.c f.src = rcg->parent_map[i].src; rcg 696 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg 704 drivers/clk/qcom/clk-rcg2.c return clk_rcg2_configure(rcg, &f); rcg 778 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 783 drivers/clk/qcom/clk-rcg2.c cfg = rcg->parent_map[index].cfg << CFG_SRC_SEL_SHIFT; rcg 784 drivers/clk/qcom/clk-rcg2.c ret = regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); rcg 788 drivers/clk/qcom/clk-rcg2.c return update_config(rcg); rcg 815 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 819 drivers/clk/qcom/clk-rcg2.c ret = regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, rcg 838 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 840 drivers/clk/qcom/clk-rcg2.c return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG, rcg 847 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 854 drivers/clk/qcom/clk-rcg2.c ret = clk_rcg2_configure(rcg, f); rcg 864 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 867 drivers/clk/qcom/clk-rcg2.c f = qcom_find_freq(rcg->freq_tbl, rate); rcg 876 drivers/clk/qcom/clk-rcg2.c return __clk_rcg2_configure(rcg, f); rcg 889 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 900 drivers/clk/qcom/clk-rcg2.c ret = update_config(rcg); rcg 909 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 916 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, &cfg); rcg 928 drivers/clk/qcom/clk-rcg2.c regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, rcg 929 drivers/clk/qcom/clk-rcg2.c rcg->safe_src_index << CFG_SRC_SEL_SHIFT); rcg 931 drivers/clk/qcom/clk-rcg2.c update_config(rcg); rcg 936 drivers/clk/qcom/clk-rcg2.c regmap_write(rcg->clkr.regmap, rcg->cmd_rcgr + CFG_REG, cfg); rcg 955 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 961 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(l), &cfg); rcg 963 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; rcg 973 drivers/clk/qcom/clk-rcg2.c if (src == rcg->parent_map[i].cfg) { rcg 974 drivers/clk/qcom/clk-rcg2.c f->src = rcg->parent_map[i].src; rcg 975 drivers/clk/qcom/clk-rcg2.c p = clk_hw_get_parent_by_index(&rcg->clkr.hw, i); rcg 983 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; rcg 984 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_M_DFSR(l), rcg 989 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_N_DFSR(l), rcg 1000 drivers/clk/qcom/clk-rcg2.c static int clk_rcg2_dfs_populate_freq_table(struct clk_rcg2 *rcg) rcg 1009 drivers/clk/qcom/clk-rcg2.c rcg->freq_tbl = freq_tbl; rcg 1012 drivers/clk/qcom/clk-rcg2.c clk_rcg2_dfs_populate_freq(&rcg->clkr.hw, i, freq_tbl + i); rcg 1020 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 1023 drivers/clk/qcom/clk-rcg2.c if (!rcg->freq_tbl) { rcg 1024 drivers/clk/qcom/clk-rcg2.c ret = clk_rcg2_dfs_populate_freq_table(rcg); rcg 1038 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = to_clk_rcg2(hw); rcg 1041 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg 1042 drivers/clk/qcom/clk-rcg2.c rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &level); rcg 1046 drivers/clk/qcom/clk-rcg2.c if (rcg->freq_tbl) rcg 1047 drivers/clk/qcom/clk-rcg2.c return rcg->freq_tbl[level].freq; rcg 1056 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg->cmd_rcgr + SE_PERF_DFSR(level), rcg 1059 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->hid_width) - 1; rcg 1067 drivers/clk/qcom/clk-rcg2.c mask = BIT(rcg->mnd_width) - 1; rcg 1068 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg 1069 drivers/clk/qcom/clk-rcg2.c rcg->cmd_rcgr + SE_PERF_M_DFSR(level), &m); rcg 1072 drivers/clk/qcom/clk-rcg2.c regmap_read(rcg->clkr.regmap, rcg 1073 drivers/clk/qcom/clk-rcg2.c rcg->cmd_rcgr + SE_PERF_N_DFSR(level), &n); rcg 1092 drivers/clk/qcom/clk-rcg2.c struct clk_rcg2 *rcg = data->rcg; rcg 1097 drivers/clk/qcom/clk-rcg2.c ret = regmap_read(regmap, rcg->cmd_rcgr + SE_CMD_DFSR_OFFSET, &val); rcg 1111 drivers/clk/qcom/clk-rcg2.c rcg->freq_tbl = NULL;