rc_range_params 301 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); rc_range_params 302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); rc_range_params 303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); rc_range_params 639 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, rc_range_params 640 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, rc_range_params 641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); rc_range_params 644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, rc_range_params 645 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, rc_range_params 646 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, rc_range_params 647 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, rc_range_params 648 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, rc_range_params 649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); rc_range_params 652 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, rc_range_params 653 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, rc_range_params 654 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, rc_range_params 655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, rc_range_params 656 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, rc_range_params 657 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); rc_range_params 660 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, rc_range_params 661 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, rc_range_params 662 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, rc_range_params 663 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, rc_range_params 664 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, rc_range_params 665 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); rc_range_params 668 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, rc_range_params 669 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, rc_range_params 670 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, rc_range_params 671 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, rc_range_params 672 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, rc_range_params 673 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); rc_range_params 676 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, rc_range_params 677 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, rc_range_params 678 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, rc_range_params 679 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, rc_range_params 680 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, rc_range_params 681 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); rc_range_params 684 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, rc_range_params 685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, rc_range_params 686 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, rc_range_params 687 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, rc_range_params 688 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, rc_range_params 689 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); rc_range_params 692 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, rc_range_params 693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, rc_range_params 694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, rc_range_params 695 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, rc_range_params 696 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, rc_range_params 697 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); rc_range_params 58 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c memcpy(&to->rc_range_params, &from->rc_range_params, sizeof(from->rc_range_params)); rc_range_params 88 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_range_params[i].range_min_qp = rc->qp_min[i]; rc_range_params 89 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_range_params[i].range_max_qp = rc->qp_max[i]; rc_range_params 91 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i]; rc_range_params 219 drivers/gpu/drm/drm_dsc.c ((dsc_cfg->rc_range_params[i].range_min_qp << rc_range_params 221 drivers/gpu/drm/drm_dsc.c (dsc_cfg->rc_range_params[i].range_max_qp << rc_range_params 223 drivers/gpu/drm/drm_dsc.c (dsc_cfg->rc_range_params[i].range_bpg_offset)); rc_range_params 49 drivers/gpu/drm/i915/display/intel_vdsc.c struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES]; rc_range_params 425 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_range_params[i].range_min_qp = rc_range_params 426 drivers/gpu/drm/i915/display/intel_vdsc.c rc_params[row_index][column_index].rc_range_params[i].range_min_qp; rc_range_params 427 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_range_params[i].range_max_qp = rc_range_params 428 drivers/gpu/drm/i915/display/intel_vdsc.c rc_params[row_index][column_index].rc_range_params[i].range_max_qp; rc_range_params 433 drivers/gpu/drm/i915/display/intel_vdsc.c vdsc_cfg->rc_range_params[i].range_bpg_offset = rc_range_params 434 drivers/gpu/drm/i915/display/intel_vdsc.c rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset & rc_range_params 801 drivers/gpu/drm/i915/display/intel_vdsc.c (u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset << rc_range_params 803 drivers/gpu/drm/i915/display/intel_vdsc.c (vdsc_cfg->rc_range_params[i].range_max_qp << rc_range_params 805 drivers/gpu/drm/i915/display/intel_vdsc.c (vdsc_cfg->rc_range_params[i].range_min_qp << rc_range_params 182 include/drm/drm_dsc.h struct drm_dsc_rc_range_parameters rc_range_params[DSC_NUM_BUF_RANGES];