rc_quant_incr_limit1  293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1);
rc_quant_incr_limit1  493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.rc_quant_incr_limit1        = 11;
rc_quant_incr_limit1  614 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1,
rc_quant_incr_limit1  185 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 	rc->rc_quant_incr_limit1 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
rc_quant_incr_limit1   38 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h 	int      rc_quant_incr_limit1;
rc_quant_incr_limit1   49 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->rc_quant_incr_limit1     = from->rc_quant_incr_limit1;
rc_quant_incr_limit1   80 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	dsc_cfg->rc_quant_incr_limit1   = rc->rc_quant_incr_limit1;
rc_quant_incr_limit1  200 drivers/gpu/drm/drm_dsc.c 	pps_payload->rc_quant_incr_limit1 =
rc_quant_incr_limit1  201 drivers/gpu/drm/drm_dsc.c 		dsc_cfg->rc_quant_incr_limit1;
rc_quant_incr_limit1   48 drivers/gpu/drm/i915/display/intel_vdsc.c 	u8 rc_quant_incr_limit1;
rc_quant_incr_limit1  421 drivers/gpu/drm/i915/display/intel_vdsc.c 	vdsc_cfg->rc_quant_incr_limit1 =
rc_quant_incr_limit1  422 drivers/gpu/drm/i915/display/intel_vdsc.c 		rc_params[row_index][column_index].rc_quant_incr_limit1;
rc_quant_incr_limit1  710 drivers/gpu/drm/i915/display/intel_vdsc.c 		DSC_RC_QUANT_INC_LIMIT1(vdsc_cfg->rc_quant_incr_limit1) |
rc_quant_incr_limit1  139 include/drm/drm_dsc.h 	u8 rc_quant_incr_limit1;
rc_quant_incr_limit1  487 include/drm/drm_dsc.h 	u8 rc_quant_incr_limit1;