rc_quant_incr_limit0  292 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0);
rc_quant_incr_limit0  492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 	reg_vals->pps.rc_quant_incr_limit0        = 11;
rc_quant_incr_limit0  613 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0,
rc_quant_incr_limit0  184 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.c 	rc->rc_quant_incr_limit0 = ((bpc == BPC_8) ? 11 : (bpc == BPC_10 ? 15 : 19)) - ((minor_version == 1 && cm == CM_444) ? 1 : 0);
rc_quant_incr_limit0   37 drivers/gpu/drm/amd/display/dc/dsc/rc_calc.h 	int      rc_quant_incr_limit0;
rc_quant_incr_limit0   50 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	to->rc_quant_incr_limit0     = from->rc_quant_incr_limit0;
rc_quant_incr_limit0   79 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 	dsc_cfg->rc_quant_incr_limit0   = rc->rc_quant_incr_limit0;
rc_quant_incr_limit0  196 drivers/gpu/drm/drm_dsc.c 	pps_payload->rc_quant_incr_limit0 =
rc_quant_incr_limit0  197 drivers/gpu/drm/drm_dsc.c 		dsc_cfg->rc_quant_incr_limit0;
rc_quant_incr_limit0   47 drivers/gpu/drm/i915/display/intel_vdsc.c 	u8 rc_quant_incr_limit0;
rc_quant_incr_limit0  419 drivers/gpu/drm/i915/display/intel_vdsc.c 	vdsc_cfg->rc_quant_incr_limit0 =
rc_quant_incr_limit0  420 drivers/gpu/drm/i915/display/intel_vdsc.c 		rc_params[row_index][column_index].rc_quant_incr_limit0;
rc_quant_incr_limit0  709 drivers/gpu/drm/i915/display/intel_vdsc.c 	pps_val |= DSC_RC_QUANT_INC_LIMIT0(vdsc_cfg->rc_quant_incr_limit0) |
rc_quant_incr_limit0  144 include/drm/drm_dsc.h 	u8 rc_quant_incr_limit0;
rc_quant_incr_limit0  481 include/drm/drm_dsc.h 	u8 rc_quant_incr_limit0;