rbo 2672 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct amdgpu_bo *rbo = gem_to_amdgpu_bo(amdgpu_fb->base.obj[0]); rbo 2673 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c int r = amdgpu_bo_reserve(rbo, false); rbo 2683 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_get_tiling_flags(rbo, tiling_flags); rbo 2685 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_unreserve(rbo); rbo 4492 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct amdgpu_bo *rbo; rbo 4512 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c rbo = gem_to_amdgpu_bo(obj); rbo 4513 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c adev = amdgpu_ttm_adev(rbo->tbo.bdev); rbo 4516 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c tv.bo = &rbo->tbo; rbo 4527 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c domain = amdgpu_display_supported_domains(adev, rbo->flags); rbo 4531 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c r = amdgpu_bo_pin(rbo, domain); rbo 4539 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c r = amdgpu_ttm_alloc_gart(&rbo->tbo); rbo 4541 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_unpin(rbo); rbo 4543 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c DRM_ERROR("%p bind failed\n", rbo); rbo 4547 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_get_tiling_flags(rbo, &tiling_flags); rbo 4551 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c afb->address = amdgpu_bo_gpu_offset(rbo); rbo 4553 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_ref(rbo); rbo 4574 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c struct amdgpu_bo *rbo; rbo 4580 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c rbo = gem_to_amdgpu_bo(old_state->fb->obj[0]); rbo 4581 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c r = amdgpu_bo_reserve(rbo, false); rbo 4587 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_unpin(rbo); rbo 4588 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_unreserve(rbo); rbo 4589 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c amdgpu_bo_unref(&rbo); rbo 409 drivers/gpu/drm/qxl/qxl_drv.h struct qxl_bo **rbo); rbo 322 drivers/gpu/drm/qxl/qxl_release.c struct qxl_bo **rbo) rbo 343 drivers/gpu/drm/qxl/qxl_release.c if (rbo) rbo 344 drivers/gpu/drm/qxl/qxl_release.c *rbo = NULL; rbo 369 drivers/gpu/drm/qxl/qxl_release.c if (rbo) rbo 370 drivers/gpu/drm/qxl/qxl_release.c *rbo = bo; rbo 1153 drivers/gpu/drm/radeon/atombios_crtc.c struct radeon_bo *rbo; rbo 1178 drivers/gpu/drm/radeon/atombios_crtc.c rbo = gem_to_radeon_bo(obj); rbo 1179 drivers/gpu/drm/radeon/atombios_crtc.c r = radeon_bo_reserve(rbo, false); rbo 1184 drivers/gpu/drm/radeon/atombios_crtc.c fb_location = radeon_bo_gpu_offset(rbo); rbo 1186 drivers/gpu/drm/radeon/atombios_crtc.c r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); rbo 1188 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unreserve(rbo); rbo 1193 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); rbo 1194 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unreserve(rbo); rbo 1452 drivers/gpu/drm/radeon/atombios_crtc.c rbo = gem_to_radeon_bo(fb->obj[0]); rbo 1453 drivers/gpu/drm/radeon/atombios_crtc.c r = radeon_bo_reserve(rbo, false); rbo 1456 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unpin(rbo); rbo 1457 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unreserve(rbo); rbo 1474 drivers/gpu/drm/radeon/atombios_crtc.c struct radeon_bo *rbo; rbo 1496 drivers/gpu/drm/radeon/atombios_crtc.c rbo = gem_to_radeon_bo(obj); rbo 1497 drivers/gpu/drm/radeon/atombios_crtc.c r = radeon_bo_reserve(rbo, false); rbo 1505 drivers/gpu/drm/radeon/atombios_crtc.c fb_location = radeon_bo_gpu_offset(rbo); rbo 1507 drivers/gpu/drm/radeon/atombios_crtc.c r = radeon_bo_pin(rbo, RADEON_GEM_DOMAIN_VRAM, &fb_location); rbo 1509 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unreserve(rbo); rbo 1513 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); rbo 1514 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unreserve(rbo); rbo 1661 drivers/gpu/drm/radeon/atombios_crtc.c rbo = gem_to_radeon_bo(fb->obj[0]); rbo 1662 drivers/gpu/drm/radeon/atombios_crtc.c r = radeon_bo_reserve(rbo, false); rbo 1665 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unpin(rbo); rbo 1666 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unreserve(rbo); rbo 2168 drivers/gpu/drm/radeon/atombios_crtc.c struct radeon_bo *rbo; rbo 2170 drivers/gpu/drm/radeon/atombios_crtc.c rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); rbo 2171 drivers/gpu/drm/radeon/atombios_crtc.c r = radeon_bo_reserve(rbo, false); rbo 2175 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unpin(rbo); rbo 2176 drivers/gpu/drm/radeon/atombios_crtc.c radeon_bo_unreserve(rbo); rbo 1688 drivers/gpu/drm/radeon/radeon.h void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, rbo 2811 drivers/gpu/drm/radeon/radeon.h extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); rbo 113 drivers/gpu/drm/radeon/radeon_fb.c struct radeon_bo *rbo = gem_to_radeon_bo(gobj); rbo 116 drivers/gpu/drm/radeon/radeon_fb.c ret = radeon_bo_reserve(rbo, false); rbo 118 drivers/gpu/drm/radeon/radeon_fb.c radeon_bo_kunmap(rbo); rbo 119 drivers/gpu/drm/radeon/radeon_fb.c radeon_bo_unpin(rbo); rbo 120 drivers/gpu/drm/radeon/radeon_fb.c radeon_bo_unreserve(rbo); rbo 132 drivers/gpu/drm/radeon/radeon_fb.c struct radeon_bo *rbo = NULL; rbo 158 drivers/gpu/drm/radeon/radeon_fb.c rbo = gem_to_radeon_bo(gobj); rbo 176 drivers/gpu/drm/radeon/radeon_fb.c ret = radeon_bo_set_tiling_flags(rbo, rbo 184 drivers/gpu/drm/radeon/radeon_fb.c ret = radeon_bo_reserve(rbo, false); rbo 188 drivers/gpu/drm/radeon/radeon_fb.c ret = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, rbo 192 drivers/gpu/drm/radeon/radeon_fb.c radeon_bo_unreserve(rbo); rbo 196 drivers/gpu/drm/radeon/radeon_fb.c radeon_bo_check_tiling(rbo, 0, 0); rbo 197 drivers/gpu/drm/radeon/radeon_fb.c ret = radeon_bo_kmap(rbo, NULL); rbo 198 drivers/gpu/drm/radeon/radeon_fb.c radeon_bo_unreserve(rbo); rbo 221 drivers/gpu/drm/radeon/radeon_fb.c struct radeon_bo *rbo = NULL; rbo 241 drivers/gpu/drm/radeon/radeon_fb.c rbo = gem_to_radeon_bo(gobj); rbo 264 drivers/gpu/drm/radeon/radeon_fb.c memset_io(rbo->kptr, 0x0, radeon_bo_size(rbo)); rbo 268 drivers/gpu/drm/radeon/radeon_fb.c tmp = radeon_bo_gpu_offset(rbo) - rdev->mc.vram_start; rbo 270 drivers/gpu/drm/radeon/radeon_fb.c info->fix.smem_len = radeon_bo_size(rbo); rbo 271 drivers/gpu/drm/radeon/radeon_fb.c info->screen_base = rbo->kptr; rbo 272 drivers/gpu/drm/radeon/radeon_fb.c info->screen_size = radeon_bo_size(rbo); rbo 289 drivers/gpu/drm/radeon/radeon_fb.c DRM_INFO("size %lu\n", (unsigned long)radeon_bo_size(rbo)); rbo 297 drivers/gpu/drm/radeon/radeon_fb.c if (rbo) { rbo 150 drivers/gpu/drm/radeon/radeon_gem.c struct radeon_bo *rbo = gem_to_radeon_bo(obj); rbo 151 drivers/gpu/drm/radeon/radeon_gem.c struct radeon_device *rdev = rbo->rdev; rbo 162 drivers/gpu/drm/radeon/radeon_gem.c r = radeon_bo_reserve(rbo, false); rbo 167 drivers/gpu/drm/radeon/radeon_gem.c bo_va = radeon_vm_bo_find(vm, rbo); rbo 169 drivers/gpu/drm/radeon/radeon_gem.c bo_va = radeon_vm_bo_add(rdev, vm, rbo); rbo 173 drivers/gpu/drm/radeon/radeon_gem.c radeon_bo_unreserve(rbo); rbo 181 drivers/gpu/drm/radeon/radeon_gem.c struct radeon_bo *rbo = gem_to_radeon_bo(obj); rbo 182 drivers/gpu/drm/radeon/radeon_gem.c struct radeon_device *rdev = rbo->rdev; rbo 193 drivers/gpu/drm/radeon/radeon_gem.c r = radeon_bo_reserve(rbo, true); rbo 199 drivers/gpu/drm/radeon/radeon_gem.c bo_va = radeon_vm_bo_find(vm, rbo); rbo 205 drivers/gpu/drm/radeon/radeon_gem.c radeon_bo_unreserve(rbo); rbo 522 drivers/gpu/drm/radeon/radeon_gem.c struct radeon_bo *rbo; rbo 529 drivers/gpu/drm/radeon/radeon_gem.c rbo = gem_to_radeon_bo(gobj); rbo 530 drivers/gpu/drm/radeon/radeon_gem.c r = radeon_bo_reserve(rbo, false); rbo 533 drivers/gpu/drm/radeon/radeon_gem.c radeon_bo_get_tiling_flags(rbo, &args->tiling_flags, &args->pitch); rbo 534 drivers/gpu/drm/radeon/radeon_gem.c radeon_bo_unreserve(rbo); rbo 609 drivers/gpu/drm/radeon/radeon_gem.c struct radeon_bo *rbo; rbo 666 drivers/gpu/drm/radeon/radeon_gem.c rbo = gem_to_radeon_bo(gobj); rbo 667 drivers/gpu/drm/radeon/radeon_gem.c r = radeon_bo_reserve(rbo, false); rbo 673 drivers/gpu/drm/radeon/radeon_gem.c bo_va = radeon_vm_bo_find(&fpriv->vm, rbo); rbo 676 drivers/gpu/drm/radeon/radeon_gem.c radeon_bo_unreserve(rbo); rbo 686 drivers/gpu/drm/radeon/radeon_gem.c radeon_bo_unreserve(rbo); rbo 785 drivers/gpu/drm/radeon/radeon_gem.c struct radeon_bo *rbo; rbo 789 drivers/gpu/drm/radeon/radeon_gem.c list_for_each_entry(rbo, &rdev->gem.objects, list) { rbo 793 drivers/gpu/drm/radeon/radeon_gem.c domain = radeon_mem_type_to_domain(rbo->tbo.mem.mem_type); rbo 807 drivers/gpu/drm/radeon/radeon_gem.c i, radeon_bo_size(rbo) >> 10, radeon_bo_size(rbo) >> 20, rbo 808 drivers/gpu/drm/radeon/radeon_gem.c placement, (unsigned long)rbo->pid); rbo 382 drivers/gpu/drm/radeon/radeon_legacy_crtc.c struct radeon_bo *rbo; rbo 425 drivers/gpu/drm/radeon/radeon_legacy_crtc.c rbo = gem_to_radeon_bo(obj); rbo 427 drivers/gpu/drm/radeon/radeon_legacy_crtc.c r = radeon_bo_reserve(rbo, false); rbo 431 drivers/gpu/drm/radeon/radeon_legacy_crtc.c r = radeon_bo_pin_restricted(rbo, RADEON_GEM_DOMAIN_VRAM, 1 << 27, rbo 434 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_bo_unreserve(rbo); rbo 454 drivers/gpu/drm/radeon/radeon_legacy_crtc.c nsize = radeon_bo_size(rbo); rbo 464 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_bo_get_tiling_flags(rbo, &tiling_flags, NULL); rbo 465 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_bo_unreserve(rbo); rbo 559 drivers/gpu/drm/radeon/radeon_legacy_crtc.c rbo = gem_to_radeon_bo(fb->obj[0]); rbo 560 drivers/gpu/drm/radeon/radeon_legacy_crtc.c r = radeon_bo_reserve(rbo, false); rbo 563 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_bo_unpin(rbo); rbo 564 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_bo_unreserve(rbo); rbo 1093 drivers/gpu/drm/radeon/radeon_legacy_crtc.c struct radeon_bo *rbo; rbo 1095 drivers/gpu/drm/radeon/radeon_legacy_crtc.c rbo = gem_to_radeon_bo(crtc->primary->fb->obj[0]); rbo 1096 drivers/gpu/drm/radeon/radeon_legacy_crtc.c r = radeon_bo_reserve(rbo, false); rbo 1100 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_bo_unpin(rbo); rbo 1101 drivers/gpu/drm/radeon/radeon_legacy_crtc.c radeon_bo_unreserve(rbo); rbo 101 drivers/gpu/drm/radeon/radeon_object.c void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain) rbo 105 drivers/gpu/drm/radeon/radeon_object.c rbo->placement.placement = rbo->placements; rbo 106 drivers/gpu/drm/radeon/radeon_object.c rbo->placement.busy_placement = rbo->placements; rbo 111 drivers/gpu/drm/radeon/radeon_object.c if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) && rbo 112 drivers/gpu/drm/radeon/radeon_object.c rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) { rbo 113 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c].fpfn = rbo 114 drivers/gpu/drm/radeon/radeon_object.c rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; rbo 115 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c++].flags = TTM_PL_FLAG_WC | rbo 120 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c].fpfn = 0; rbo 121 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c++].flags = TTM_PL_FLAG_WC | rbo 127 drivers/gpu/drm/radeon/radeon_object.c if (rbo->flags & RADEON_GEM_GTT_UC) { rbo 128 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c].fpfn = 0; rbo 129 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | rbo 132 drivers/gpu/drm/radeon/radeon_object.c } else if ((rbo->flags & RADEON_GEM_GTT_WC) || rbo 133 drivers/gpu/drm/radeon/radeon_object.c (rbo->rdev->flags & RADEON_IS_AGP)) { rbo 134 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c].fpfn = 0; rbo 135 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c++].flags = TTM_PL_FLAG_WC | rbo 139 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c].fpfn = 0; rbo 140 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | rbo 146 drivers/gpu/drm/radeon/radeon_object.c if (rbo->flags & RADEON_GEM_GTT_UC) { rbo 147 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c].fpfn = 0; rbo 148 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED | rbo 151 drivers/gpu/drm/radeon/radeon_object.c } else if ((rbo->flags & RADEON_GEM_GTT_WC) || rbo 152 drivers/gpu/drm/radeon/radeon_object.c rbo->rdev->flags & RADEON_IS_AGP) { rbo 153 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c].fpfn = 0; rbo 154 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c++].flags = TTM_PL_FLAG_WC | rbo 158 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c].fpfn = 0; rbo 159 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c++].flags = TTM_PL_FLAG_CACHED | rbo 164 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c].fpfn = 0; rbo 165 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[c++].flags = TTM_PL_MASK_CACHING | rbo 169 drivers/gpu/drm/radeon/radeon_object.c rbo->placement.num_placement = c; rbo 170 drivers/gpu/drm/radeon/radeon_object.c rbo->placement.num_busy_placement = c; rbo 173 drivers/gpu/drm/radeon/radeon_object.c if ((rbo->flags & RADEON_GEM_CPU_ACCESS) && rbo 174 drivers/gpu/drm/radeon/radeon_object.c (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && rbo 175 drivers/gpu/drm/radeon/radeon_object.c !rbo->placements[i].fpfn) rbo 176 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[i].lpfn = rbo 177 drivers/gpu/drm/radeon/radeon_object.c rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; rbo 179 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[i].lpfn = 0; rbo 780 drivers/gpu/drm/radeon/radeon_object.c struct radeon_bo *rbo; rbo 785 drivers/gpu/drm/radeon/radeon_object.c rbo = container_of(bo, struct radeon_bo, tbo); rbo 786 drivers/gpu/drm/radeon/radeon_object.c radeon_bo_check_tiling(rbo, 0, 1); rbo 787 drivers/gpu/drm/radeon/radeon_object.c radeon_vm_bo_invalidate(rbo->rdev, rbo); rbo 793 drivers/gpu/drm/radeon/radeon_object.c radeon_update_memory_usage(rbo, bo->mem.mem_type, -1); rbo 794 drivers/gpu/drm/radeon/radeon_object.c radeon_update_memory_usage(rbo, new_mem->mem_type, 1); rbo 801 drivers/gpu/drm/radeon/radeon_object.c struct radeon_bo *rbo; rbo 807 drivers/gpu/drm/radeon/radeon_object.c rbo = container_of(bo, struct radeon_bo, tbo); rbo 808 drivers/gpu/drm/radeon/radeon_object.c radeon_bo_check_tiling(rbo, 0, 0); rbo 809 drivers/gpu/drm/radeon/radeon_object.c rdev = rbo->rdev; rbo 819 drivers/gpu/drm/radeon/radeon_object.c if (rbo->pin_count > 0) rbo 823 drivers/gpu/drm/radeon/radeon_object.c radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM); rbo 825 drivers/gpu/drm/radeon/radeon_object.c for (i = 0; i < rbo->placement.num_placement; i++) { rbo 827 drivers/gpu/drm/radeon/radeon_object.c if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) && rbo 828 drivers/gpu/drm/radeon/radeon_object.c (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn)) rbo 829 drivers/gpu/drm/radeon/radeon_object.c rbo->placements[i].lpfn = lpfn; rbo 831 drivers/gpu/drm/radeon/radeon_object.c r = ttm_bo_validate(bo, &rbo->placement, &ctx); rbo 833 drivers/gpu/drm/radeon/radeon_object.c radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); rbo 834 drivers/gpu/drm/radeon/radeon_object.c return ttm_bo_validate(bo, &rbo->placement, &ctx); rbo 134 drivers/gpu/drm/radeon/radeon_ttm.c struct radeon_bo *rbo; rbo 143 drivers/gpu/drm/radeon/radeon_ttm.c rbo = container_of(bo, struct radeon_bo, tbo); rbo 146 drivers/gpu/drm/radeon/radeon_ttm.c if (rbo->rdev->ring[radeon_copy_ring_index(rbo->rdev)].ready == false) rbo 147 drivers/gpu/drm/radeon/radeon_ttm.c radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); rbo 148 drivers/gpu/drm/radeon/radeon_ttm.c else if (rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size && rbo 149 drivers/gpu/drm/radeon/radeon_ttm.c bo->mem.start < (rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT)) { rbo 150 drivers/gpu/drm/radeon/radeon_ttm.c unsigned fpfn = rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT; rbo 158 drivers/gpu/drm/radeon/radeon_ttm.c radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM | rbo 160 drivers/gpu/drm/radeon/radeon_ttm.c rbo->placement.num_busy_placement = 0; rbo 161 drivers/gpu/drm/radeon/radeon_ttm.c for (i = 0; i < rbo->placement.num_placement; i++) { rbo 162 drivers/gpu/drm/radeon/radeon_ttm.c if (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) { rbo 163 drivers/gpu/drm/radeon/radeon_ttm.c if (rbo->placements[i].fpfn < fpfn) rbo 164 drivers/gpu/drm/radeon/radeon_ttm.c rbo->placements[i].fpfn = fpfn; rbo 166 drivers/gpu/drm/radeon/radeon_ttm.c rbo->placement.busy_placement = rbo 167 drivers/gpu/drm/radeon/radeon_ttm.c &rbo->placements[i]; rbo 168 drivers/gpu/drm/radeon/radeon_ttm.c rbo->placement.num_busy_placement = 1; rbo 172 drivers/gpu/drm/radeon/radeon_ttm.c radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT); rbo 176 drivers/gpu/drm/radeon/radeon_ttm.c radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_CPU); rbo 178 drivers/gpu/drm/radeon/radeon_ttm.c *placement = rbo->placement; rbo 183 drivers/gpu/drm/radeon/radeon_ttm.c struct radeon_bo *rbo = container_of(bo, struct radeon_bo, tbo); rbo 187 drivers/gpu/drm/radeon/radeon_ttm.c return drm_vma_node_verify_access(&rbo->tbo.base.vma_node, rbo 344 drivers/gpu/drm/radeon/radeon_ttm.c struct radeon_bo *rbo; rbo 353 drivers/gpu/drm/radeon/radeon_ttm.c rbo = container_of(bo, struct radeon_bo, tbo); rbo 354 drivers/gpu/drm/radeon/radeon_ttm.c if (WARN_ON_ONCE(rbo->pin_count > 0)) rbo 302 drivers/gpu/drm/radeon/radeon_uvd.c void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, rbo 307 drivers/gpu/drm/radeon/radeon_uvd.c for (i = 0; i < rbo->placement.num_placement; ++i) { rbo 308 drivers/gpu/drm/radeon/radeon_uvd.c rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; rbo 309 drivers/gpu/drm/radeon/radeon_uvd.c rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; rbo 317 drivers/gpu/drm/radeon/radeon_uvd.c if (rbo->placement.num_placement > 1) rbo 321 drivers/gpu/drm/radeon/radeon_uvd.c rbo->placements[1] = rbo->placements[0]; rbo 322 drivers/gpu/drm/radeon/radeon_uvd.c rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; rbo 323 drivers/gpu/drm/radeon/radeon_uvd.c rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; rbo 324 drivers/gpu/drm/radeon/radeon_uvd.c rbo->placement.num_placement++; rbo 325 drivers/gpu/drm/radeon/radeon_uvd.c rbo->placement.num_busy_placement++;