rb_cntl 310 drivers/gpu/drm/amd/amdgpu/cik_sdma.c u32 rb_cntl; rb_cntl 318 drivers/gpu/drm/amd/amdgpu/cik_sdma.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); rb_cntl 319 drivers/gpu/drm/amd/amdgpu/cik_sdma.c rb_cntl &= ~SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK; rb_cntl 320 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 435 drivers/gpu/drm/amd/amdgpu/cik_sdma.c u32 rb_cntl, ib_cntl; rb_cntl 463 drivers/gpu/drm/amd/amdgpu/cik_sdma.c rb_cntl = rb_bufsz << 1; rb_cntl 465 drivers/gpu/drm/amd/amdgpu/cik_sdma.c rb_cntl |= SDMA0_GFX_RB_CNTL__RB_SWAP_ENABLE_MASK | rb_cntl 468 drivers/gpu/drm/amd/amdgpu/cik_sdma.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 482 drivers/gpu/drm/amd/amdgpu/cik_sdma.c rb_cntl |= SDMA0_GFX_RB_CNTL__RPTR_WRITEBACK_ENABLE_MASK; rb_cntl 492 drivers/gpu/drm/amd/amdgpu/cik_sdma.c rb_cntl | SDMA0_GFX_RB_CNTL__RB_ENABLE_MASK); rb_cntl 343 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c u32 rb_cntl, ib_cntl; rb_cntl 351 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); rb_cntl 352 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); rb_cntl 353 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 413 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c u32 rb_cntl, ib_cntl; rb_cntl 439 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); rb_cntl 440 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); rb_cntl 442 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); rb_cntl 443 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, rb_cntl 446 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 460 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); rb_cntl 469 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); rb_cntl 470 drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 517 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c u32 rb_cntl, ib_cntl; rb_cntl 525 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); rb_cntl 526 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); rb_cntl 527 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 648 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c u32 rb_cntl, ib_cntl, wptr_poll_cntl; rb_cntl 677 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]); rb_cntl 678 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); rb_cntl 680 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); rb_cntl 681 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, rb_cntl 684 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 699 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); rb_cntl 737 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); rb_cntl 738 drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 809 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c u32 rb_cntl, ib_cntl; rb_cntl 820 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); rb_cntl 821 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); rb_cntl 822 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); rb_cntl 853 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c u32 rb_cntl, ib_cntl; rb_cntl 866 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); rb_cntl 867 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, rb_cntl 869 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); rb_cntl 960 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c static uint32_t sdma_v4_0_rb_cntl(struct amdgpu_ring *ring, uint32_t rb_cntl) rb_cntl 965 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); rb_cntl 967 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); rb_cntl 968 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, rb_cntl 971 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c return rb_cntl; rb_cntl 986 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c u32 rb_cntl, ib_cntl, wptr_poll_cntl; rb_cntl 994 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = RREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL); rb_cntl 995 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); rb_cntl 996 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); rb_cntl 1010 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, rb_cntl 1050 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); rb_cntl 1051 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32_SDMA(i, mmSDMA0_GFX_RB_CNTL, rb_cntl); rb_cntl 1076 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c u32 rb_cntl, ib_cntl, wptr_poll_cntl; rb_cntl 1084 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = RREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL); rb_cntl 1085 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = sdma_v4_0_rb_cntl(ring, rb_cntl); rb_cntl 1086 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); rb_cntl 1100 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, rb_cntl 1141 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_PAGE_RB_CNTL, RB_ENABLE, 1); rb_cntl 1142 drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c WREG32_SDMA(i, mmSDMA0_PAGE_RB_CNTL, rb_cntl); rb_cntl 502 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c u32 rb_cntl, ib_cntl; rb_cntl 510 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); rb_cntl 511 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0); rb_cntl 512 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); rb_cntl 624 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c u32 rb_cntl, ib_cntl; rb_cntl 642 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = RREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL)); rb_cntl 643 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz); rb_cntl 645 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1); rb_cntl 646 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, rb_cntl 649 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); rb_cntl 677 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1); rb_cntl 743 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1); rb_cntl 744 drivers/gpu/drm/amd/amdgpu/sdma_v5_0.c WREG32(sdma_v5_0_get_reg_offset(adev, i, mmSDMA0_GFX_RB_CNTL), rb_cntl); rb_cntl 115 drivers/gpu/drm/amd/amdgpu/si_dma.c u32 rb_cntl; rb_cntl 121 drivers/gpu/drm/amd/amdgpu/si_dma.c rb_cntl = RREG32(DMA_RB_CNTL + sdma_offsets[i]); rb_cntl 122 drivers/gpu/drm/amd/amdgpu/si_dma.c rb_cntl &= ~DMA_RB_ENABLE; rb_cntl 123 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 134 drivers/gpu/drm/amd/amdgpu/si_dma.c u32 rb_cntl, dma_cntl, ib_cntl, rb_bufsz; rb_cntl 146 drivers/gpu/drm/amd/amdgpu/si_dma.c rb_cntl = rb_bufsz << 1; rb_cntl 148 drivers/gpu/drm/amd/amdgpu/si_dma.c rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; rb_cntl 150 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl); rb_cntl 161 drivers/gpu/drm/amd/amdgpu/si_dma.c rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; rb_cntl 178 drivers/gpu/drm/amd/amdgpu/si_dma.c WREG32(DMA_RB_CNTL + sdma_offsets[i], rb_cntl | DMA_RB_ENABLE); rb_cntl 252 drivers/gpu/drm/radeon/cik_sdma.c u32 rb_cntl, reg_offset; rb_cntl 264 drivers/gpu/drm/radeon/cik_sdma.c rb_cntl = RREG32(SDMA0_GFX_RB_CNTL + reg_offset); rb_cntl 265 drivers/gpu/drm/radeon/cik_sdma.c rb_cntl &= ~SDMA_RB_ENABLE; rb_cntl 266 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); rb_cntl 368 drivers/gpu/drm/radeon/cik_sdma.c u32 rb_cntl, ib_cntl; rb_cntl 389 drivers/gpu/drm/radeon/cik_sdma.c rb_cntl = rb_bufsz << 1; rb_cntl 391 drivers/gpu/drm/radeon/cik_sdma.c rb_cntl |= SDMA_RB_SWAP_ENABLE | SDMA_RPTR_WRITEBACK_SWAP_ENABLE; rb_cntl 393 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl); rb_cntl 406 drivers/gpu/drm/radeon/cik_sdma.c rb_cntl |= SDMA_RPTR_WRITEBACK_ENABLE; rb_cntl 415 drivers/gpu/drm/radeon/cik_sdma.c WREG32(SDMA0_GFX_RB_CNTL + reg_offset, rb_cntl | SDMA_RB_ENABLE); rb_cntl 1689 drivers/gpu/drm/radeon/ni.c uint32_t rb_cntl; rb_cntl 1694 drivers/gpu/drm/radeon/ni.c rb_cntl = order_base_2(ring->ring_size / 8); rb_cntl 1695 drivers/gpu/drm/radeon/ni.c rb_cntl |= order_base_2(RADEON_GPU_PAGE_SIZE/8) << 8; rb_cntl 1697 drivers/gpu/drm/radeon/ni.c rb_cntl |= BUF_SWAP_32BIT; rb_cntl 1699 drivers/gpu/drm/radeon/ni.c WREG32(cp_rb_cntl[i], rb_cntl); rb_cntl 159 drivers/gpu/drm/radeon/ni_dma.c u32 rb_cntl; rb_cntl 166 drivers/gpu/drm/radeon/ni_dma.c rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); rb_cntl 167 drivers/gpu/drm/radeon/ni_dma.c rb_cntl &= ~DMA_RB_ENABLE; rb_cntl 168 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); rb_cntl 171 drivers/gpu/drm/radeon/ni_dma.c rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); rb_cntl 172 drivers/gpu/drm/radeon/ni_dma.c rb_cntl &= ~DMA_RB_ENABLE; rb_cntl 173 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); rb_cntl 190 drivers/gpu/drm/radeon/ni_dma.c u32 rb_cntl, dma_cntl, ib_cntl; rb_cntl 211 drivers/gpu/drm/radeon/ni_dma.c rb_cntl = rb_bufsz << 1; rb_cntl 213 drivers/gpu/drm/radeon/ni_dma.c rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; rb_cntl 215 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); rb_cntl 228 drivers/gpu/drm/radeon/ni_dma.c rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; rb_cntl 246 drivers/gpu/drm/radeon/ni_dma.c WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); rb_cntl 101 drivers/gpu/drm/radeon/r600_dma.c u32 rb_cntl = RREG32(DMA_RB_CNTL); rb_cntl 106 drivers/gpu/drm/radeon/r600_dma.c rb_cntl &= ~DMA_RB_ENABLE; rb_cntl 107 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_CNTL, rb_cntl); rb_cntl 123 drivers/gpu/drm/radeon/r600_dma.c u32 rb_cntl, dma_cntl, ib_cntl; rb_cntl 132 drivers/gpu/drm/radeon/r600_dma.c rb_cntl = rb_bufsz << 1; rb_cntl 134 drivers/gpu/drm/radeon/r600_dma.c rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; rb_cntl 136 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_CNTL, rb_cntl); rb_cntl 149 drivers/gpu/drm/radeon/r600_dma.c rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; rb_cntl 170 drivers/gpu/drm/radeon/r600_dma.c WREG32(DMA_RB_CNTL, rb_cntl | DMA_RB_ENABLE);