rateSection      1817 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 	u8 regulation, bw, channel, rateSection;
rateSection      1823 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 				for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {
rateSection      1824 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 					tempPwrLmt = pHalData->TxPwrLimit_5G[regulation][bw][rateSection][channel][ODM_RF_PATH_A];
rateSection      1830 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 							if (rateSection >= 2 && rateSection <= 9) {
rateSection      1831 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 								if (rateSection == 2) {
rateSection      1834 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 								} else if (rateSection == 3) {
rateSection      1837 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 								} else if (rateSection == 4) {
rateSection      1840 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 								} else if (rateSection == 5) {
rateSection      1843 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 								} else if (rateSection == 6) {
rateSection      1846 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 								} else if (rateSection == 7) {
rateSection      1849 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 								} else if (rateSection == 8) {
rateSection      1852 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 								} else if (rateSection == 9) {
rateSection      1873 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 	u8 regulation, bw, channel, rateSection;
rateSection      1884 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 				for (rateSection = 0; rateSection < MAX_RATE_SECTION_NUM; ++rateSection) {
rateSection      1885 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 					tempPwrLmt = pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][ODM_RF_PATH_A];
rateSection      1889 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 							if (rateSection == 5) /*  HT 4T */
rateSection      1891 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 							else if (rateSection == 4) /*  HT 3T */
rateSection      1893 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 							else if (rateSection == 3) /*  HT 2T */
rateSection      1895 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 							else if (rateSection == 2) /*  HT 1T */
rateSection      1897 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 							else if (rateSection == 1) /*  OFDM */
rateSection      1899 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 							else if (rateSection == 0) /*  CCK */
rateSection      1906 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 							pHalData->TxPwrLimit_2_4G[regulation][bw][rateSection][channel][rfPath] = tempValue;
rateSection      1955 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 	u8 regulation = 0, bandwidth = 0, rateSection = 0, channel;
rateSection      1977 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 0;
rateSection      1979 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 1;
rateSection      1981 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 2;
rateSection      1983 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 3;
rateSection      1985 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 4;
rateSection      1987 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 5;
rateSection      1989 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 6;
rateSection      1991 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 7;
rateSection      1993 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 8;
rateSection      1995 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		rateSection = 9;
rateSection      2017 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		prevPowerLimit = pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A];
rateSection      2020 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			pHalData->TxPwrLimit_2_4G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A] = powerLimit;
rateSection      2030 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 		prevPowerLimit = pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A];
rateSection      2033 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			pHalData->TxPwrLimit_5G[regulation][bandwidth][rateSection][channelIndex][ODM_RF_PATH_A] = powerLimit;
rateSection      2982 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 	char band[10], bandwidth[10], rateSection[10],
rateSection      3004 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			memset((void *) rateSection, 0, 10);
rateSection      3031 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 			if (!ParseQualifiedString(szLine, &i, rateSection, ' ', ',')) {
rateSection      3199 drivers/staging/rtl8723bs/hal/hal_com_phycfg.c 					(u8 *)bandwidth, (u8 *)rateSection, (u8 *)rfPath, (u8 *)channel, (u8 *)powerLimit);