range_bpg_offset  303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset);
range_bpg_offset  641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset);
range_bpg_offset  646 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset,
range_bpg_offset  649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset);
range_bpg_offset  654 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset,
range_bpg_offset  657 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset);
range_bpg_offset  662 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset,
range_bpg_offset  665 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset);
range_bpg_offset  670 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset,
range_bpg_offset  673 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset);
range_bpg_offset  678 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset,
range_bpg_offset  681 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset);
range_bpg_offset  686 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset,
range_bpg_offset  689 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset);
range_bpg_offset  694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset,
range_bpg_offset  697 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c 		RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset);
range_bpg_offset   39 drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h 	int range_bpg_offset;
range_bpg_offset   91 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c 		dsc_cfg->rc_range_params[i].range_bpg_offset = 0x3f & rc->ofs[i];
range_bpg_offset  223 drivers/gpu/drm/drm_dsc.c 			 (dsc_cfg->rc_range_params[i].range_bpg_offset));
range_bpg_offset  433 drivers/gpu/drm/i915/display/intel_vdsc.c 		vdsc_cfg->rc_range_params[i].range_bpg_offset =
range_bpg_offset  434 drivers/gpu/drm/i915/display/intel_vdsc.c 			rc_params[row_index][column_index].rc_range_params[i].range_bpg_offset &
range_bpg_offset  801 drivers/gpu/drm/i915/display/intel_vdsc.c 			(u32)(((vdsc_cfg->rc_range_params[i].range_bpg_offset <<
range_bpg_offset   66 include/drm/drm_dsc.h 	u8 range_bpg_offset;