ramht 17 drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h struct nvkm_ramht *ramht; ramht 27 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_ramht_hash(struct nvkm_ramht *ramht, int chid, u32 handle) ramht 32 drivers/gpu/drm/nouveau/nvkm/core/ramht.c hash ^= (handle & ((1 << ramht->bits) - 1)); ramht 33 drivers/gpu/drm/nouveau/nvkm/core/ramht.c handle >>= ramht->bits; ramht 36 drivers/gpu/drm/nouveau/nvkm/core/ramht.c hash ^= chid << (ramht->bits - 4); ramht 41 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_ramht_search(struct nvkm_ramht *ramht, int chid, u32 handle) ramht 45 drivers/gpu/drm/nouveau/nvkm/core/ramht.c co = ho = nvkm_ramht_hash(ramht, chid, handle); ramht 47 drivers/gpu/drm/nouveau/nvkm/core/ramht.c if (ramht->data[co].chid == chid) { ramht 48 drivers/gpu/drm/nouveau/nvkm/core/ramht.c if (ramht->data[co].handle == handle) ramht 49 drivers/gpu/drm/nouveau/nvkm/core/ramht.c return ramht->data[co].inst; ramht 52 drivers/gpu/drm/nouveau/nvkm/core/ramht.c if (++co >= ramht->size) ramht 60 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_ramht_update(struct nvkm_ramht *ramht, int co, struct nvkm_object *object, ramht 63 drivers/gpu/drm/nouveau/nvkm/core/ramht.c struct nvkm_ramht_data *data = &ramht->data[co]; ramht 72 drivers/gpu/drm/nouveau/nvkm/core/ramht.c ret = nvkm_object_bind(object, ramht->parent, 16, &data->inst); ramht 82 drivers/gpu/drm/nouveau/nvkm/core/ramht.c if (ramht->device->card_type >= NV_50) ramht 92 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_kmap(ramht->gpuobj); ramht 93 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_wo32(ramht->gpuobj, (co << 3) + 0, handle); ramht 94 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_wo32(ramht->gpuobj, (co << 3) + 4, context); ramht 95 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_done(ramht->gpuobj); ramht 100 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_ramht_remove(struct nvkm_ramht *ramht, int cookie) ramht 103 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_ramht_update(ramht, cookie, NULL, -1, 0, 0, 0); ramht 107 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_ramht_insert(struct nvkm_ramht *ramht, struct nvkm_object *object, ramht 112 drivers/gpu/drm/nouveau/nvkm/core/ramht.c if (nvkm_ramht_search(ramht, chid, handle)) ramht 115 drivers/gpu/drm/nouveau/nvkm/core/ramht.c co = ho = nvkm_ramht_hash(ramht, chid, handle); ramht 117 drivers/gpu/drm/nouveau/nvkm/core/ramht.c if (ramht->data[co].chid < 0) { ramht 118 drivers/gpu/drm/nouveau/nvkm/core/ramht.c return nvkm_ramht_update(ramht, co, object, chid, ramht 122 drivers/gpu/drm/nouveau/nvkm/core/ramht.c if (++co >= ramht->size) ramht 132 drivers/gpu/drm/nouveau/nvkm/core/ramht.c struct nvkm_ramht *ramht = *pramht; ramht 133 drivers/gpu/drm/nouveau/nvkm/core/ramht.c if (ramht) { ramht 134 drivers/gpu/drm/nouveau/nvkm/core/ramht.c nvkm_gpuobj_del(&ramht->gpuobj); ramht 144 drivers/gpu/drm/nouveau/nvkm/core/ramht.c struct nvkm_ramht *ramht; ramht 147 drivers/gpu/drm/nouveau/nvkm/core/ramht.c if (!(ramht = *pramht = vzalloc(struct_size(ramht, data, (size >> 3))))) ramht 150 drivers/gpu/drm/nouveau/nvkm/core/ramht.c ramht->device = device; ramht 151 drivers/gpu/drm/nouveau/nvkm/core/ramht.c ramht->parent = parent; ramht 152 drivers/gpu/drm/nouveau/nvkm/core/ramht.c ramht->size = size >> 3; ramht 153 drivers/gpu/drm/nouveau/nvkm/core/ramht.c ramht->bits = order_base_2(ramht->size); ramht 154 drivers/gpu/drm/nouveau/nvkm/core/ramht.c for (i = 0; i < ramht->size; i++) ramht 155 drivers/gpu/drm/nouveau/nvkm/core/ramht.c ramht->data[i].chid = -1; ramht 157 drivers/gpu/drm/nouveau/nvkm/core/ramht.c ret = nvkm_gpuobj_new(ramht->device, size, align, true, ramht 158 drivers/gpu/drm/nouveau/nvkm/core/ramht.c ramht->parent, &ramht->gpuobj); ramht 235 drivers/gpu/drm/nouveau/nvkm/engine/disp/channv50.c nvkm_ramht_remove(object->disp->ramht, object->hash); ramht 33 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgf119.c return nvkm_ramht_insert(chan->disp->ramht, object, ramht 44 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacgv100.c return nvkm_ramht_insert(chan->disp->ramht, object, ramht 73 drivers/gpu/drm/nouveau/nvkm/engine/disp/dmacnv50.c return nvkm_ramht_insert(chan->disp->ramht, object, ramht 71 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c nvkm_ramht_del(&disp->ramht); ramht 142 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.c 0x1000, 0, disp->inst, &disp->ramht); ramht 38 drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.h struct nvkm_ramht *ramht; ramht 201 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c return nvkm_ramht_insert(chan->ramht, object, 0, 4, handle, context); ramht 283 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c return nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht); ramht 154 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nvkm_ramht_remove(chan->ramht, cookie); ramht 175 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c return nvkm_ramht_insert(chan->ramht, object, 0, 4, handle, context); ramht 209 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nvkm_ramht_del(&chan->ramht); ramht 267 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c return nvkm_ramht_new(device, 0x8000, 16, chan->base.inst, &chan->ramht); ramht 16 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h struct nvkm_ramht *ramht; ramht 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | ramht 81 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c (chan->ramht->gpuobj->node->offset >> 4)); ramht 42 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_ramht_remove(imem->ramht, cookie); ramht 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, ramht 163 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c hash = nvkm_ramht_insert(imem->ramht, object, chan->base.chid, 4, ramht 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | ramht 81 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c (chan->ramht->gpuobj->node->offset >> 4)); ramht 80 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | ramht 82 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c (chan->ramht->gpuobj->node->offset >> 4)); ramht 80 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | ramht 82 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c (chan->ramht->gpuobj->node->offset >> 4)); ramht 304 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nvkm_ramht *ramht = imem->ramht; ramht 312 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c ((ramht->bits - 9) << 16) | ramht 313 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c (ramht->gpuobj->addr >> 8)); ramht 56 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c struct nvkm_ramht *ramht = imem->ramht; ramht 64 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c ((ramht->bits - 9) << 16) | ramht 65 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c (ramht->gpuobj->addr >> 8)); ramht 66 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c struct nvkm_ramht *ramht = imem->ramht; ramht 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c ((ramht->bits - 9) << 16) | ramht 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c (ramht->gpuobj->addr >> 8)); ramht 179 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht); ramht 204 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nvkm_ramht_del(&imem->base.ramht); ramht 191 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c ret = nvkm_ramht_new(device, 0x08000, 0, NULL, &imem->base.ramht); ramht 220 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_ramht_del(&imem->base.ramht);