ramfc 19 drivers/gpu/drm/nouveau/include/nvkm/subdev/instmem.h struct nvkm_memory *ramfc; ramfc 210 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c u64 addr = chan->ramfc->addr >> 8; ramfc 279 drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c &chan->ramfc); ramfc 11 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv04.h u32 ramfc; ramfc 198 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c u64 addr = chan->ramfc->addr >> 12; ramfc 213 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c nvkm_gpuobj_del(&chan->ramfc); ramfc 253 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c &chan->ramfc); ramfc 12 drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.h struct nvkm_gpuobj *ramfc; ramfc 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_kmap(chan->ramfc); ramfc 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); ramfc 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); ramfc 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); ramfc 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); ramfc 72 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); ramfc 73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); ramfc 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); ramfc 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); ramfc 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); ramfc 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x78, 0x00000000); ramfc 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); ramfc 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | ramfc 82 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); ramfc 83 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); ramfc 84 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmag84.c nvkm_done(chan->ramfc); ramfc 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c struct nvkm_memory *fctx = device->imem->ramfc; ramfc 83 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c u32 data = chan->ramfc; ramfc 97 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c c = fifo->ramfc; ramfc 108 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c c = fifo->ramfc; ramfc 145 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c const struct nv04_fifo_ramfc *c = fifo->ramfc; ramfc 147 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_kmap(imem->ramfc); ramfc 149 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_wo32(imem->ramfc, chan->ramfc + c->ctxp, 0x00000000); ramfc 151 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_done(imem->ramfc); ramfc 203 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c chan->ramfc = chan->base.chid * 32; ramfc 205 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_kmap(imem->ramfc); ramfc 206 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); ramfc 207 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); ramfc 208 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x08, chan->base.push->addr >> 4); ramfc 209 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x10, ramfc 216 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c nvkm_done(imem->ramfc); ramfc 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c chan->ramfc = chan->base.chid * 32; ramfc 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c nvkm_kmap(imem->ramfc); ramfc 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); ramfc 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); ramfc 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); ramfc 80 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, ramfc 87 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv10.c nvkm_done(imem->ramfc); ramfc 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c chan->ramfc = chan->base.chid * 64; ramfc 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c nvkm_kmap(imem->ramfc); ramfc 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); ramfc 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); ramfc 80 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); ramfc 81 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x14, ramfc 88 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv17.c nvkm_done(imem->ramfc); ramfc 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_kmap(imem->ramfc); ramfc 80 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wo32(imem->ramfc, chan->ramfc + ctx, 0x00000000); ramfc 81 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_done(imem->ramfc); ramfc 110 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_kmap(imem->ramfc); ramfc 111 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wo32(imem->ramfc, chan->ramfc + ctx, inst); ramfc 112 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_done(imem->ramfc); ramfc 222 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c chan->ramfc = chan->base.chid * 128; ramfc 224 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_kmap(imem->ramfc); ramfc 225 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x00, args->v0.offset); ramfc 226 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x04, args->v0.offset); ramfc 227 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x0c, chan->base.push->addr >> 4); ramfc 228 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x18, 0x30000000 | ramfc 235 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_wo32(imem->ramfc, chan->ramfc + 0x3c, 0x0001ffff); ramfc 236 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c nvkm_done(imem->ramfc); ramfc 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_kmap(chan->ramfc); ramfc 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x08, lower_32_bits(args->v0.offset)); ramfc 69 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x0c, upper_32_bits(args->v0.offset)); ramfc 70 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x10, lower_32_bits(args->v0.offset)); ramfc 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x14, upper_32_bits(args->v0.offset)); ramfc 72 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x3c, 0x003f6078); ramfc 73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); ramfc 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); ramfc 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x4c, 0xffffffff); ramfc 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); ramfc 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x78, 0x00000000); ramfc 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); ramfc 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | ramfc 82 drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv50.c nvkm_done(chan->ramfc); ramfc 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_kmap(chan->ramfc); ramfc 72 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); ramfc 73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); ramfc 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); ramfc 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); ramfc 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); ramfc 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); ramfc 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x78, 0x00000000); ramfc 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); ramfc 80 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | ramfc 83 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x88, chan->cache->addr >> 10); ramfc 84 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_wo32(chan->ramfc, 0x98, chan->base.inst->addr >> 12); ramfc 85 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifog84.c nvkm_done(chan->ramfc); ramfc 71 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_kmap(chan->ramfc); ramfc 72 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x3c, 0x403f6078); ramfc 73 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x44, 0x01003fff); ramfc 74 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x48, chan->base.push->node->offset >> 4); ramfc 75 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x50, lower_32_bits(ioffset)); ramfc 76 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x54, upper_32_bits(ioffset) | (ilength << 16)); ramfc 77 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x60, 0x7fffffff); ramfc 78 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x78, 0x00000000); ramfc 79 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x7c, 0x30000001); ramfc 80 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_wo32(chan->ramfc, 0x80, ((chan->ramht->bits - 9) << 27) | ramfc 83 drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifonv50.c nvkm_done(chan->ramfc); ramfc 306 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c struct nvkm_memory *ramfc = imem->ramfc; ramfc 315 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8); ramfc 329 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c int index, int nr, const struct nv04_fifo_ramfc *ramfc, ramfc 337 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.c fifo->ramfc = ramfc; ramfc 17 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.h const struct nv04_fifo_ramfc *ramfc; ramfc 58 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c struct nvkm_memory *ramfc = imem->ramfc; ramfc 67 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.c nvkm_wr32(device, NV03_PFIFO_RAMFC, nvkm_memory_addr(ramfc) >> 8 | ramfc 68 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c struct nvkm_memory *ramfc = imem->ramfc; ramfc 96 drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.c nvkm_memory_addr(ramfc)) >> 16) | ramfc 185 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c &imem->base.ramfc); ramfc 202 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.c nvkm_memory_unref(&imem->base.ramfc); ramfc 207 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c &imem->base.ramfc); ramfc 218 drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.c nvkm_memory_unref(&imem->base.ramfc);