r_stage           228 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	enum mdp5_pipe r_stage[STAGE_MAX + 1][MAX_PIPE_STAGE] = { { SSPP_NONE } };
r_stage           259 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			r_stage[pstate->stage][PIPE_LEFT] =
r_stage           269 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
r_stage           356 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	mdp5_ctl_blend(ctl, pipeline, stage, r_stage, plane_cnt,
r_stage           349 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 		   enum mdp5_pipe r_stage[][MAX_PIPE_STAGE],
r_stage           379 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 				mdp_ctl_blend_mask(r_stage[i][PIPE_LEFT], i) |
r_stage           380 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 				mdp_ctl_blend_mask(r_stage[i][PIPE_RIGHT], i);
r_stage           382 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 			     mdp_ctl_blend_ext_mask(r_stage[i][PIPE_LEFT], i) |
r_stage           383 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.c 			     mdp_ctl_blend_ext_mask(r_stage[i][PIPE_RIGHT], i);
r_stage            57 drivers/gpu/drm/msm/disp/mdp5/mdp5_ctl.h 		   enum mdp5_pipe r_stage[][MAX_PIPE_STAGE],