r500 786 drivers/gpu/drm/radeon/radeon.h struct r500_irq_stat_regs r500; r500 720 drivers/gpu/drm/radeon/rs600.c rdev->irq.stat_regs.r500.disp_int = RREG32(R_007EDC_DISP_INTERRUPT_STATUS); r500 721 drivers/gpu/drm/radeon/rs600.c if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { r500 725 drivers/gpu/drm/radeon/rs600.c if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { r500 729 drivers/gpu/drm/radeon/rs600.c if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { r500 734 drivers/gpu/drm/radeon/rs600.c if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { r500 740 drivers/gpu/drm/radeon/rs600.c rdev->irq.stat_regs.r500.disp_int = 0; r500 744 drivers/gpu/drm/radeon/rs600.c rdev->irq.stat_regs.r500.hdmi0_status = RREG32(R_007404_HDMI0_STATUS) & r500 746 drivers/gpu/drm/radeon/rs600.c if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) { r500 752 drivers/gpu/drm/radeon/rs600.c rdev->irq.stat_regs.r500.hdmi0_status = 0; r500 780 drivers/gpu/drm/radeon/rs600.c !rdev->irq.stat_regs.r500.disp_int && r500 781 drivers/gpu/drm/radeon/rs600.c !rdev->irq.stat_regs.r500.hdmi0_status) { r500 785 drivers/gpu/drm/radeon/rs600.c rdev->irq.stat_regs.r500.disp_int || r500 786 drivers/gpu/drm/radeon/rs600.c rdev->irq.stat_regs.r500.hdmi0_status) { r500 792 drivers/gpu/drm/radeon/rs600.c if (G_007EDC_LB_D1_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { r500 801 drivers/gpu/drm/radeon/rs600.c if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { r500 810 drivers/gpu/drm/radeon/rs600.c if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { r500 814 drivers/gpu/drm/radeon/rs600.c if (G_007EDC_DC_HOT_PLUG_DETECT2_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) { r500 818 drivers/gpu/drm/radeon/rs600.c if (G_007404_HDMI0_AZ_FORMAT_WTRIG(rdev->irq.stat_regs.r500.hdmi0_status)) {