r4tst 236 drivers/crypto/caam/ctrl.c rdsta_val = rd_reg32(&ctrl->r4tst[0].rdsta) & RDSTA_IFMASK; r4tst 354 drivers/crypto/caam/ctrl.c struct rng4tst __iomem *r4tst; r4tst 358 drivers/crypto/caam/ctrl.c r4tst = &ctrl->r4tst[0]; r4tst 361 drivers/crypto/caam/ctrl.c clrsetbits_32(&r4tst->rtmctl, 0, RTMCTL_PRGM); r4tst 371 drivers/crypto/caam/ctrl.c val = (rd_reg32(&r4tst->rtsdctl) & RTSDCTL_ENT_DLY_MASK) r4tst 376 drivers/crypto/caam/ctrl.c val = rd_reg32(&r4tst->rtsdctl); r4tst 379 drivers/crypto/caam/ctrl.c wr_reg32(&r4tst->rtsdctl, val); r4tst 381 drivers/crypto/caam/ctrl.c wr_reg32(&r4tst->rtfrqmin, ent_delay >> 2); r4tst 383 drivers/crypto/caam/ctrl.c wr_reg32(&r4tst->rtfrqmax, RTFRQMAX_DISABLE); r4tst 385 drivers/crypto/caam/ctrl.c val = rd_reg32(&r4tst->rtmctl); r4tst 391 drivers/crypto/caam/ctrl.c clrsetbits_32(&r4tst->rtmctl, RTMCTL_PRGM, RTMCTL_SAMP_MODE_RAW_ES_SC); r4tst 798 drivers/crypto/caam/ctrl.c rd_reg32(&ctrl->r4tst[0].rdsta); r4tst 809 drivers/crypto/caam/ctrl.c rd_reg32(&ctrl->r4tst[0].rdsta) & r4tst 588 drivers/crypto/caam/regs.h struct rng4tst r4tst[2];