qos_level_low_wm  642 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
qos_level_low_wm  952 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
qos_level_low_wm 1013 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
qos_level_low_wm  648 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.h 	uint32_t qos_level_low_wm;
qos_level_low_wm  157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 			DTN_INFO_MICRO_SEC(s->qos_level_low_wm);
qos_level_low_wm  230 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
qos_level_low_wm  157 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 					(s->qos_level_low_wm * frac) / ref_clk_mhz / frac, (s->qos_level_low_wm * frac) / ref_clk_mhz % frac,
qos_level_low_wm  177 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 					(s->qos_level_low_wm * frac) / ref_clk_mhz / frac, (s->qos_level_low_wm * frac) / ref_clk_mhz % frac,
qos_level_low_wm  311 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				pool->hubps[i]->inst, ttu_regs->qos_level_low_wm, ttu_regs->qos_level_high_wm, ttu_regs->min_ttu_vblank,
qos_level_low_wm  143 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_LOW_WM, ttu_attr->qos_level_low_wm,
qos_level_low_wm 1150 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		QoS_LEVEL_LOW_WM, &ttu_attr->qos_level_low_wm,
qos_level_low_wm 1211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 			QoS_LEVEL_LOW_WM, &s->qos_level_low_wm,
qos_level_low_wm 1542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	disp_ttu_regs->qos_level_low_wm = 0;
qos_level_low_wm 1543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
qos_level_low_wm 1542 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	disp_ttu_regs->qos_level_low_wm = 0;
qos_level_low_wm 1543 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
qos_level_low_wm 1642 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	disp_ttu_regs->qos_level_low_wm = 0;
qos_level_low_wm 1643 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));
qos_level_low_wm  461 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int qos_level_low_wm;
qos_level_low_wm  337 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 			ttu_regs.qos_level_low_wm);
qos_level_low_wm 1895 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	disp_ttu_regs->qos_level_low_wm = 0;
qos_level_low_wm 1896 drivers/gpu/drm/amd/display/dc/dml/dml1_display_rq_dlg_calc.c 	ASSERT(disp_ttu_regs->qos_level_low_wm < dml_pow(2, 14));