qe_gc              40 drivers/soc/fsl/qe/gpio.c 	struct qe_gpio_chip *qe_gc =
qe_gc              44 drivers/soc/fsl/qe/gpio.c 	qe_gc->cpdata = in_be32(&regs->cpdata);
qe_gc              45 drivers/soc/fsl/qe/gpio.c 	qe_gc->saved_regs.cpdata = qe_gc->cpdata;
qe_gc              46 drivers/soc/fsl/qe/gpio.c 	qe_gc->saved_regs.cpdir1 = in_be32(&regs->cpdir1);
qe_gc              47 drivers/soc/fsl/qe/gpio.c 	qe_gc->saved_regs.cpdir2 = in_be32(&regs->cpdir2);
qe_gc              48 drivers/soc/fsl/qe/gpio.c 	qe_gc->saved_regs.cppar1 = in_be32(&regs->cppar1);
qe_gc              49 drivers/soc/fsl/qe/gpio.c 	qe_gc->saved_regs.cppar2 = in_be32(&regs->cppar2);
qe_gc              50 drivers/soc/fsl/qe/gpio.c 	qe_gc->saved_regs.cpodr = in_be32(&regs->cpodr);
qe_gc              65 drivers/soc/fsl/qe/gpio.c 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
qe_gc              70 drivers/soc/fsl/qe/gpio.c 	spin_lock_irqsave(&qe_gc->lock, flags);
qe_gc              73 drivers/soc/fsl/qe/gpio.c 		qe_gc->cpdata |= pin_mask;
qe_gc              75 drivers/soc/fsl/qe/gpio.c 		qe_gc->cpdata &= ~pin_mask;
qe_gc              77 drivers/soc/fsl/qe/gpio.c 	out_be32(&regs->cpdata, qe_gc->cpdata);
qe_gc              79 drivers/soc/fsl/qe/gpio.c 	spin_unlock_irqrestore(&qe_gc->lock, flags);
qe_gc              86 drivers/soc/fsl/qe/gpio.c 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
qe_gc              91 drivers/soc/fsl/qe/gpio.c 	spin_lock_irqsave(&qe_gc->lock, flags);
qe_gc              98 drivers/soc/fsl/qe/gpio.c 				qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));
qe_gc             100 drivers/soc/fsl/qe/gpio.c 				qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));
qe_gc             104 drivers/soc/fsl/qe/gpio.c 	out_be32(&regs->cpdata, qe_gc->cpdata);
qe_gc             106 drivers/soc/fsl/qe/gpio.c 	spin_unlock_irqrestore(&qe_gc->lock, flags);
qe_gc             112 drivers/soc/fsl/qe/gpio.c 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
qe_gc             115 drivers/soc/fsl/qe/gpio.c 	spin_lock_irqsave(&qe_gc->lock, flags);
qe_gc             119 drivers/soc/fsl/qe/gpio.c 	spin_unlock_irqrestore(&qe_gc->lock, flags);
qe_gc             127 drivers/soc/fsl/qe/gpio.c 	struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
qe_gc             132 drivers/soc/fsl/qe/gpio.c 	spin_lock_irqsave(&qe_gc->lock, flags);
qe_gc             136 drivers/soc/fsl/qe/gpio.c 	spin_unlock_irqrestore(&qe_gc->lock, flags);
qe_gc             164 drivers/soc/fsl/qe/gpio.c 	struct qe_gpio_chip *qe_gc;
qe_gc             190 drivers/soc/fsl/qe/gpio.c 	qe_gc = gpiochip_get_data(gc);
qe_gc             192 drivers/soc/fsl/qe/gpio.c 	spin_lock_irqsave(&qe_gc->lock, flags);
qe_gc             195 drivers/soc/fsl/qe/gpio.c 	if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
qe_gc             196 drivers/soc/fsl/qe/gpio.c 		qe_pin->controller = qe_gc;
qe_gc             203 drivers/soc/fsl/qe/gpio.c 	spin_unlock_irqrestore(&qe_gc->lock, flags);
qe_gc             224 drivers/soc/fsl/qe/gpio.c 	struct qe_gpio_chip *qe_gc = qe_pin->controller;
qe_gc             228 drivers/soc/fsl/qe/gpio.c 	spin_lock_irqsave(&qe_gc->lock, flags);
qe_gc             229 drivers/soc/fsl/qe/gpio.c 	test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
qe_gc             230 drivers/soc/fsl/qe/gpio.c 	spin_unlock_irqrestore(&qe_gc->lock, flags);
qe_gc             246 drivers/soc/fsl/qe/gpio.c 	struct qe_gpio_chip *qe_gc = qe_pin->controller;
qe_gc             247 drivers/soc/fsl/qe/gpio.c 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
qe_gc             248 drivers/soc/fsl/qe/gpio.c 	struct qe_pio_regs *sregs = &qe_gc->saved_regs;
qe_gc             255 drivers/soc/fsl/qe/gpio.c 	spin_lock_irqsave(&qe_gc->lock, flags);
qe_gc             266 drivers/soc/fsl/qe/gpio.c 		qe_gc->cpdata |= mask1;
qe_gc             268 drivers/soc/fsl/qe/gpio.c 		qe_gc->cpdata &= ~mask1;
qe_gc             270 drivers/soc/fsl/qe/gpio.c 	out_be32(&regs->cpdata, qe_gc->cpdata);
qe_gc             273 drivers/soc/fsl/qe/gpio.c 	spin_unlock_irqrestore(&qe_gc->lock, flags);
qe_gc             286 drivers/soc/fsl/qe/gpio.c 	struct qe_gpio_chip *qe_gc = qe_pin->controller;
qe_gc             287 drivers/soc/fsl/qe/gpio.c 	struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
qe_gc             290 drivers/soc/fsl/qe/gpio.c 	spin_lock_irqsave(&qe_gc->lock, flags);
qe_gc             295 drivers/soc/fsl/qe/gpio.c 	spin_unlock_irqrestore(&qe_gc->lock, flags);
qe_gc             305 drivers/soc/fsl/qe/gpio.c 		struct qe_gpio_chip *qe_gc;
qe_gc             309 drivers/soc/fsl/qe/gpio.c 		qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
qe_gc             310 drivers/soc/fsl/qe/gpio.c 		if (!qe_gc) {
qe_gc             315 drivers/soc/fsl/qe/gpio.c 		spin_lock_init(&qe_gc->lock);
qe_gc             317 drivers/soc/fsl/qe/gpio.c 		mm_gc = &qe_gc->mm_gc;
qe_gc             328 drivers/soc/fsl/qe/gpio.c 		ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
qe_gc             335 drivers/soc/fsl/qe/gpio.c 		kfree(qe_gc);