qce                23 drivers/crypto/qce/ablkcipher.c 	struct qce_device *qce = tmpl->qce;
qce                33 drivers/crypto/qce/ablkcipher.c 	error = qce_dma_terminate_all(&qce->dma);
qce                35 drivers/crypto/qce/ablkcipher.c 		dev_dbg(qce->dev, "ablkcipher dma termination error (%d)\n",
qce                39 drivers/crypto/qce/ablkcipher.c 		dma_unmap_sg(qce->dev, rctx->src_sg, rctx->src_nents, dir_src);
qce                40 drivers/crypto/qce/ablkcipher.c 	dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
qce                44 drivers/crypto/qce/ablkcipher.c 	error = qce_check_status(qce, &status);
qce                46 drivers/crypto/qce/ablkcipher.c 		dev_dbg(qce->dev, "ablkcipher operation error (%x)\n", status);
qce                48 drivers/crypto/qce/ablkcipher.c 	qce->async_req_done(tmpl->qce, error);
qce                58 drivers/crypto/qce/ablkcipher.c 	struct qce_device *qce = tmpl->qce;
qce                79 drivers/crypto/qce/ablkcipher.c 		dev_err(qce->dev, "Invalid numbers of src SG.\n");
qce                83 drivers/crypto/qce/ablkcipher.c 		dev_err(qce->dev, "Invalid numbers of dst SG.\n");
qce                96 drivers/crypto/qce/ablkcipher.c 	sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
qce               113 drivers/crypto/qce/ablkcipher.c 	ret = dma_map_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
qce               118 drivers/crypto/qce/ablkcipher.c 		ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, dir_src);
qce               126 drivers/crypto/qce/ablkcipher.c 	ret = qce_dma_prep_sgs(&qce->dma, rctx->src_sg, rctx->src_nents,
qce               132 drivers/crypto/qce/ablkcipher.c 	qce_dma_issue_pending(&qce->dma);
qce               141 drivers/crypto/qce/ablkcipher.c 	qce_dma_terminate_all(&qce->dma);
qce               144 drivers/crypto/qce/ablkcipher.c 		dma_unmap_sg(qce->dev, req->src, rctx->src_nents, dir_src);
qce               146 drivers/crypto/qce/ablkcipher.c 	dma_unmap_sg(qce->dev, rctx->dst_sg, rctx->dst_nents, dir_dst);
qce               237 drivers/crypto/qce/ablkcipher.c 	return tmpl->qce->async_req_enqueue(tmpl->qce, &req->base);
qce               355 drivers/crypto/qce/ablkcipher.c 				       struct qce_device *qce)
qce               394 drivers/crypto/qce/ablkcipher.c 	tmpl->qce = qce;
qce               399 drivers/crypto/qce/ablkcipher.c 		dev_err(qce->dev, "%s registration failed\n", alg->cra_name);
qce               404 drivers/crypto/qce/ablkcipher.c 	dev_dbg(qce->dev, "%s is registered\n", alg->cra_name);
qce               408 drivers/crypto/qce/ablkcipher.c static void qce_ablkcipher_unregister(struct qce_device *qce)
qce               419 drivers/crypto/qce/ablkcipher.c static int qce_ablkcipher_register(struct qce_device *qce)
qce               424 drivers/crypto/qce/ablkcipher.c 		ret = qce_ablkcipher_register_one(&ablkcipher_def[i], qce);
qce               431 drivers/crypto/qce/ablkcipher.c 	qce_ablkcipher_unregister(qce);
qce                20 drivers/crypto/qce/common.c static inline u32 qce_read(struct qce_device *qce, u32 offset)
qce                22 drivers/crypto/qce/common.c 	return readl(qce->base + offset);
qce                25 drivers/crypto/qce/common.c static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)
qce                27 drivers/crypto/qce/common.c 	writel(val, qce->base + offset);
qce                30 drivers/crypto/qce/common.c static inline void qce_write_array(struct qce_device *qce, u32 offset,
qce                36 drivers/crypto/qce/common.c 		qce_write(qce, offset + i * sizeof(u32), val[i]);
qce                40 drivers/crypto/qce/common.c qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)
qce                45 drivers/crypto/qce/common.c 		qce_write(qce, offset + i * sizeof(u32), 0);
qce               140 drivers/crypto/qce/common.c static u32 qce_config_reg(struct qce_device *qce, int little)
qce               142 drivers/crypto/qce/common.c 	u32 beats = (qce->burst_size >> 3) - 1;
qce               143 drivers/crypto/qce/common.c 	u32 pipe_pair = qce->pipe_pair_id;
qce               189 drivers/crypto/qce/common.c static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
qce               198 drivers/crypto/qce/common.c 	qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
qce               202 drivers/crypto/qce/common.c 	qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
qce               205 drivers/crypto/qce/common.c static void qce_setup_config(struct qce_device *qce)
qce               210 drivers/crypto/qce/common.c 	config = qce_config_reg(qce, 0);
qce               213 drivers/crypto/qce/common.c 	qce_write(qce, REG_STATUS, 0);
qce               214 drivers/crypto/qce/common.c 	qce_write(qce, REG_CONFIG, config);
qce               217 drivers/crypto/qce/common.c static inline void qce_crypto_go(struct qce_device *qce)
qce               219 drivers/crypto/qce/common.c 	qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
qce               229 drivers/crypto/qce/common.c 	struct qce_device *qce = tmpl->qce;
qce               241 drivers/crypto/qce/common.c 	qce_setup_config(qce);
qce               244 drivers/crypto/qce/common.c 		qce_write(qce, REG_AUTH_SEG_CFG, 0);
qce               245 drivers/crypto/qce/common.c 		qce_write(qce, REG_ENCR_SEG_CFG, 0);
qce               246 drivers/crypto/qce/common.c 		qce_write(qce, REG_ENCR_SEG_SIZE, 0);
qce               247 drivers/crypto/qce/common.c 		qce_clear_array(qce, REG_AUTH_IV0, 16);
qce               248 drivers/crypto/qce/common.c 		qce_clear_array(qce, REG_AUTH_KEY0, 16);
qce               249 drivers/crypto/qce/common.c 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
qce               258 drivers/crypto/qce/common.c 		qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey,
qce               271 drivers/crypto/qce/common.c 	qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words);
qce               274 drivers/crypto/qce/common.c 		qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
qce               276 drivers/crypto/qce/common.c 		qce_write_array(qce, REG_AUTH_BYTECNT0,
qce               292 drivers/crypto/qce/common.c 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
qce               293 drivers/crypto/qce/common.c 	qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);
qce               294 drivers/crypto/qce/common.c 	qce_write(qce, REG_AUTH_SEG_START, 0);
qce               295 drivers/crypto/qce/common.c 	qce_write(qce, REG_ENCR_SEG_CFG, 0);
qce               296 drivers/crypto/qce/common.c 	qce_write(qce, REG_SEG_SIZE, req->nbytes);
qce               299 drivers/crypto/qce/common.c 	config = qce_config_reg(qce, 1);
qce               300 drivers/crypto/qce/common.c 	qce_write(qce, REG_CONFIG, config);
qce               302 drivers/crypto/qce/common.c 	qce_crypto_go(qce);
qce               314 drivers/crypto/qce/common.c 	struct qce_device *qce = tmpl->qce;
qce               323 drivers/crypto/qce/common.c 	qce_setup_config(qce);
qce               333 drivers/crypto/qce/common.c 	qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
qce               345 drivers/crypto/qce/common.c 			qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen,
qce               352 drivers/crypto/qce/common.c 	qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words);
qce               360 drivers/crypto/qce/common.c 		qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words);
qce               366 drivers/crypto/qce/common.c 	qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
qce               367 drivers/crypto/qce/common.c 	qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
qce               368 drivers/crypto/qce/common.c 	qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);
qce               371 drivers/crypto/qce/common.c 		qce_write(qce, REG_CNTR_MASK, ~0);
qce               372 drivers/crypto/qce/common.c 		qce_write(qce, REG_CNTR_MASK0, ~0);
qce               373 drivers/crypto/qce/common.c 		qce_write(qce, REG_CNTR_MASK1, ~0);
qce               374 drivers/crypto/qce/common.c 		qce_write(qce, REG_CNTR_MASK2, ~0);
qce               377 drivers/crypto/qce/common.c 	qce_write(qce, REG_SEG_SIZE, totallen);
qce               380 drivers/crypto/qce/common.c 	config = qce_config_reg(qce, 1);
qce               381 drivers/crypto/qce/common.c 	qce_write(qce, REG_CONFIG, config);
qce               383 drivers/crypto/qce/common.c 	qce_crypto_go(qce);
qce               404 drivers/crypto/qce/common.c int qce_check_status(struct qce_device *qce, u32 *status)
qce               408 drivers/crypto/qce/common.c 	*status = qce_read(qce, REG_STATUS);
qce               422 drivers/crypto/qce/common.c void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step)
qce               426 drivers/crypto/qce/common.c 	val = qce_read(qce, REG_VERSION);
qce                85 drivers/crypto/qce/common.h 	struct qce_device *qce;
qce                89 drivers/crypto/qce/common.h int qce_check_status(struct qce_device *qce, u32 *status);
qce                90 drivers/crypto/qce/common.h void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step);
qce                29 drivers/crypto/qce/core.c static void qce_unregister_algs(struct qce_device *qce)
qce                36 drivers/crypto/qce/core.c 		ops->unregister_algs(qce);
qce                40 drivers/crypto/qce/core.c static int qce_register_algs(struct qce_device *qce)
qce                47 drivers/crypto/qce/core.c 		ret = ops->register_algs(qce);
qce                72 drivers/crypto/qce/core.c static int qce_handle_queue(struct qce_device *qce,
qce                79 drivers/crypto/qce/core.c 	spin_lock_irqsave(&qce->lock, flags);
qce                82 drivers/crypto/qce/core.c 		ret = crypto_enqueue_request(&qce->queue, req);
qce                85 drivers/crypto/qce/core.c 	if (qce->req) {
qce                86 drivers/crypto/qce/core.c 		spin_unlock_irqrestore(&qce->lock, flags);
qce                90 drivers/crypto/qce/core.c 	backlog = crypto_get_backlog(&qce->queue);
qce                91 drivers/crypto/qce/core.c 	async_req = crypto_dequeue_request(&qce->queue);
qce                93 drivers/crypto/qce/core.c 		qce->req = async_req;
qce                95 drivers/crypto/qce/core.c 	spin_unlock_irqrestore(&qce->lock, flags);
qce               101 drivers/crypto/qce/core.c 		spin_lock_bh(&qce->lock);
qce               103 drivers/crypto/qce/core.c 		spin_unlock_bh(&qce->lock);
qce               108 drivers/crypto/qce/core.c 		qce->result = err;
qce               109 drivers/crypto/qce/core.c 		tasklet_schedule(&qce->done_tasklet);
qce               117 drivers/crypto/qce/core.c 	struct qce_device *qce = (struct qce_device *)data;
qce               121 drivers/crypto/qce/core.c 	spin_lock_irqsave(&qce->lock, flags);
qce               122 drivers/crypto/qce/core.c 	req = qce->req;
qce               123 drivers/crypto/qce/core.c 	qce->req = NULL;
qce               124 drivers/crypto/qce/core.c 	spin_unlock_irqrestore(&qce->lock, flags);
qce               127 drivers/crypto/qce/core.c 		req->complete(req, qce->result);
qce               129 drivers/crypto/qce/core.c 	qce_handle_queue(qce, NULL);
qce               132 drivers/crypto/qce/core.c static int qce_async_request_enqueue(struct qce_device *qce,
qce               135 drivers/crypto/qce/core.c 	return qce_handle_queue(qce, req);
qce               138 drivers/crypto/qce/core.c static void qce_async_request_done(struct qce_device *qce, int ret)
qce               140 drivers/crypto/qce/core.c 	qce->result = ret;
qce               141 drivers/crypto/qce/core.c 	tasklet_schedule(&qce->done_tasklet);
qce               144 drivers/crypto/qce/core.c static int qce_check_version(struct qce_device *qce)
qce               148 drivers/crypto/qce/core.c 	qce_get_version(qce, &major, &minor, &step);
qce               157 drivers/crypto/qce/core.c 	qce->burst_size = QCE_BAM_BURST_SIZE;
qce               158 drivers/crypto/qce/core.c 	qce->pipe_pair_id = 1;
qce               160 drivers/crypto/qce/core.c 	dev_dbg(qce->dev, "Crypto device found, version %d.%d.%d\n",
qce               169 drivers/crypto/qce/core.c 	struct qce_device *qce;
qce               172 drivers/crypto/qce/core.c 	qce = devm_kzalloc(dev, sizeof(*qce), GFP_KERNEL);
qce               173 drivers/crypto/qce/core.c 	if (!qce)
qce               176 drivers/crypto/qce/core.c 	qce->dev = dev;
qce               177 drivers/crypto/qce/core.c 	platform_set_drvdata(pdev, qce);
qce               179 drivers/crypto/qce/core.c 	qce->base = devm_platform_ioremap_resource(pdev, 0);
qce               180 drivers/crypto/qce/core.c 	if (IS_ERR(qce->base))
qce               181 drivers/crypto/qce/core.c 		return PTR_ERR(qce->base);
qce               187 drivers/crypto/qce/core.c 	qce->core = devm_clk_get(qce->dev, "core");
qce               188 drivers/crypto/qce/core.c 	if (IS_ERR(qce->core))
qce               189 drivers/crypto/qce/core.c 		return PTR_ERR(qce->core);
qce               191 drivers/crypto/qce/core.c 	qce->iface = devm_clk_get(qce->dev, "iface");
qce               192 drivers/crypto/qce/core.c 	if (IS_ERR(qce->iface))
qce               193 drivers/crypto/qce/core.c 		return PTR_ERR(qce->iface);
qce               195 drivers/crypto/qce/core.c 	qce->bus = devm_clk_get(qce->dev, "bus");
qce               196 drivers/crypto/qce/core.c 	if (IS_ERR(qce->bus))
qce               197 drivers/crypto/qce/core.c 		return PTR_ERR(qce->bus);
qce               199 drivers/crypto/qce/core.c 	ret = clk_prepare_enable(qce->core);
qce               203 drivers/crypto/qce/core.c 	ret = clk_prepare_enable(qce->iface);
qce               207 drivers/crypto/qce/core.c 	ret = clk_prepare_enable(qce->bus);
qce               211 drivers/crypto/qce/core.c 	ret = qce_dma_request(qce->dev, &qce->dma);
qce               215 drivers/crypto/qce/core.c 	ret = qce_check_version(qce);
qce               219 drivers/crypto/qce/core.c 	spin_lock_init(&qce->lock);
qce               220 drivers/crypto/qce/core.c 	tasklet_init(&qce->done_tasklet, qce_tasklet_req_done,
qce               221 drivers/crypto/qce/core.c 		     (unsigned long)qce);
qce               222 drivers/crypto/qce/core.c 	crypto_init_queue(&qce->queue, QCE_QUEUE_LENGTH);
qce               224 drivers/crypto/qce/core.c 	qce->async_req_enqueue = qce_async_request_enqueue;
qce               225 drivers/crypto/qce/core.c 	qce->async_req_done = qce_async_request_done;
qce               227 drivers/crypto/qce/core.c 	ret = qce_register_algs(qce);
qce               234 drivers/crypto/qce/core.c 	qce_dma_release(&qce->dma);
qce               236 drivers/crypto/qce/core.c 	clk_disable_unprepare(qce->bus);
qce               238 drivers/crypto/qce/core.c 	clk_disable_unprepare(qce->iface);
qce               240 drivers/crypto/qce/core.c 	clk_disable_unprepare(qce->core);
qce               246 drivers/crypto/qce/core.c 	struct qce_device *qce = platform_get_drvdata(pdev);
qce               248 drivers/crypto/qce/core.c 	tasklet_kill(&qce->done_tasklet);
qce               249 drivers/crypto/qce/core.c 	qce_unregister_algs(qce);
qce               250 drivers/crypto/qce/core.c 	qce_dma_release(&qce->dma);
qce               251 drivers/crypto/qce/core.c 	clk_disable_unprepare(qce->bus);
qce               252 drivers/crypto/qce/core.c 	clk_disable_unprepare(qce->iface);
qce               253 drivers/crypto/qce/core.c 	clk_disable_unprepare(qce->core);
qce                41 drivers/crypto/qce/core.h 	int (*async_req_enqueue)(struct qce_device *qce,
qce                43 drivers/crypto/qce/core.h 	void (*async_req_done)(struct qce_device *qce, int ret);
qce                55 drivers/crypto/qce/core.h 	int (*register_algs)(struct qce_device *qce);
qce                56 drivers/crypto/qce/core.h 	void (*unregister_algs)(struct qce_device *qce);
qce                36 drivers/crypto/qce/sha.c 	struct qce_device *qce = tmpl->qce;
qce                37 drivers/crypto/qce/sha.c 	struct qce_result_dump *result = qce->dma.result_buf;
qce                42 drivers/crypto/qce/sha.c 	error = qce_dma_terminate_all(&qce->dma);
qce                44 drivers/crypto/qce/sha.c 		dev_dbg(qce->dev, "ahash dma termination error (%d)\n", error);
qce                46 drivers/crypto/qce/sha.c 	dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
qce                47 drivers/crypto/qce/sha.c 	dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
qce                56 drivers/crypto/qce/sha.c 	error = qce_check_status(qce, &status);
qce                58 drivers/crypto/qce/sha.c 		dev_dbg(qce->dev, "ahash operation error (%x)\n", status);
qce                65 drivers/crypto/qce/sha.c 	qce->async_req_done(tmpl->qce, error);
qce                74 drivers/crypto/qce/sha.c 	struct qce_device *qce = tmpl->qce;
qce                88 drivers/crypto/qce/sha.c 		dev_err(qce->dev, "Invalid numbers of src SG.\n");
qce                92 drivers/crypto/qce/sha.c 	ret = dma_map_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
qce                96 drivers/crypto/qce/sha.c 	sg_init_one(&rctx->result_sg, qce->dma.result_buf, QCE_RESULT_BUF_SZ);
qce                98 drivers/crypto/qce/sha.c 	ret = dma_map_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
qce               102 drivers/crypto/qce/sha.c 	ret = qce_dma_prep_sgs(&qce->dma, req->src, rctx->src_nents,
qce               107 drivers/crypto/qce/sha.c 	qce_dma_issue_pending(&qce->dma);
qce               116 drivers/crypto/qce/sha.c 	qce_dma_terminate_all(&qce->dma);
qce               118 drivers/crypto/qce/sha.c 	dma_unmap_sg(qce->dev, &rctx->result_sg, 1, DMA_FROM_DEVICE);
qce               120 drivers/crypto/qce/sha.c 	dma_unmap_sg(qce->dev, req->src, rctx->src_nents, DMA_TO_DEVICE);
qce               231 drivers/crypto/qce/sha.c 	struct qce_device *qce = tmpl->qce;
qce               299 drivers/crypto/qce/sha.c 	return qce->async_req_enqueue(tmpl->qce, &req->base);
qce               306 drivers/crypto/qce/sha.c 	struct qce_device *qce = tmpl->qce;
qce               322 drivers/crypto/qce/sha.c 	return qce->async_req_enqueue(tmpl->qce, &req->base);
qce               329 drivers/crypto/qce/sha.c 	struct qce_device *qce = tmpl->qce;
qce               341 drivers/crypto/qce/sha.c 	return qce->async_req_enqueue(tmpl->qce, &req->base);
qce               470 drivers/crypto/qce/sha.c 				  struct qce_device *qce)
qce               511 drivers/crypto/qce/sha.c 	tmpl->qce = qce;
qce               516 drivers/crypto/qce/sha.c 		dev_err(qce->dev, "%s registration failed\n", base->cra_name);
qce               521 drivers/crypto/qce/sha.c 	dev_dbg(qce->dev, "%s is registered\n", base->cra_name);
qce               525 drivers/crypto/qce/sha.c static void qce_ahash_unregister(struct qce_device *qce)
qce               536 drivers/crypto/qce/sha.c static int qce_ahash_register(struct qce_device *qce)
qce               541 drivers/crypto/qce/sha.c 		ret = qce_ahash_register_one(&ahash_def[i], qce);
qce               548 drivers/crypto/qce/sha.c 	qce_ahash_unregister(qce);
qce                26 fs/ntfs/quota.c 	QUOTA_CONTROL_ENTRY *qce;
qce                58 fs/ntfs/quota.c 	qce = (QUOTA_CONTROL_ENTRY*)ictx->data;
qce                59 fs/ntfs/quota.c 	if (le32_to_cpu(qce->version) != QUOTA_VERSION) {
qce                61 fs/ntfs/quota.c 				"supported.", le32_to_cpu(qce->version));
qce                64 fs/ntfs/quota.c 	ntfs_debug("Quota defaults flags = 0x%x.", le32_to_cpu(qce->flags));
qce                66 fs/ntfs/quota.c 	if (qce->flags & QUOTA_FLAG_OUT_OF_DATE)
qce                72 fs/ntfs/quota.c 	if (!(qce->flags & (QUOTA_FLAG_TRACKING_ENABLED |
qce                81 fs/ntfs/quota.c 	qce->flags |= QUOTA_FLAG_OUT_OF_DATE;