pxlclk             23 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	u64 pxlclk, aclk;
pxlclk             30 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000ULL;
pxlclk             33 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	kcrtc_st->clock_ratio = div64_u64(aclk << 32, pxlclk);
pxlclk            121 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	err = clk_set_rate(master->pxlclk, mode->crtc_clock * 1000);
pxlclk            124 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	err = clk_prepare_enable(master->pxlclk);
pxlclk            160 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	clk_disable_unprepare(master->pxlclk);
pxlclk            342 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 			  unsigned long pxlclk)
pxlclk            348 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 		return pxlclk * 2;
pxlclk            350 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 		return pxlclk;
pxlclk            358 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	unsigned long pxlclk = kcrtc_st->base.adjusted_mode.crtc_clock * 1000;
pxlclk            361 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	min_aclk = komeda_calc_min_aclk_rate(to_kcrtc(crtc), pxlclk);
pxlclk            381 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	if (min_pxlclk != clk_round_rate(master->pxlclk, min_pxlclk)) {
pxlclk            417 drivers/gpu/drm/arm/display/komeda/komeda_crtc.c 	adjusted_mode->crtc_clock = clk_round_rate(kcrtc->master->pxlclk,
pxlclk            122 drivers/gpu/drm/arm/display/komeda/komeda_dev.c 	pipe->pxlclk = clk;
pxlclk             55 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.c 	clk_put(pipe->pxlclk);
pxlclk            387 drivers/gpu/drm/arm/display/komeda/komeda_pipeline.h 	struct clk *pxlclk;
pxlclk             37 drivers/gpu/drm/arm/malidp_crtc.c 		rate = clk_round_rate(hwdev->pxlclk, req_rate);
pxlclk             62 drivers/gpu/drm/arm/malidp_crtc.c 	clk_prepare_enable(hwdev->pxlclk);
pxlclk             65 drivers/gpu/drm/arm/malidp_crtc.c 	clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
pxlclk             85 drivers/gpu/drm/arm/malidp_crtc.c 	clk_disable_unprepare(hwdev->pxlclk);
pxlclk            764 drivers/gpu/drm/arm/malidp_drv.c 	hwdev->pxlclk = devm_clk_get(dev, "pxlclk");
pxlclk            765 drivers/gpu/drm/arm/malidp_drv.c 	if (IS_ERR(hwdev->pxlclk))
pxlclk            766 drivers/gpu/drm/arm/malidp_drv.c 		return PTR_ERR(hwdev->pxlclk);
pxlclk            475 drivers/gpu/drm/arm/malidp_hw.c 	unsigned long pxlclk = vm->pixelclock; /* Hz */
pxlclk            493 drivers/gpu/drm/arm/malidp_hw.c 	mclk = a * pxlclk / 10;
pxlclk            816 drivers/gpu/drm/arm/malidp_hw.c 	unsigned long pxlclk = vm->pixelclock;
pxlclk            834 drivers/gpu/drm/arm/malidp_hw.c 	mclk = (pxlclk * numerator) / denominator;
pxlclk            240 drivers/gpu/drm/arm/malidp_hw.h 	struct clk *pxlclk;