pxl_pllparam      472 drivers/gpu/drm/bridge/tc358767.c 	u32 pxl_pllparam;
pxl_pllparam      546 drivers/gpu/drm/bridge/tc358767.c 	pxl_pllparam  = vco_hi << 24; /* For PLL VCO >= 300 MHz = 1 */
pxl_pllparam      547 drivers/gpu/drm/bridge/tc358767.c 	pxl_pllparam |= ext_div[best_pre] << 20; /* External Pre-divider */
pxl_pllparam      548 drivers/gpu/drm/bridge/tc358767.c 	pxl_pllparam |= ext_div[best_post] << 16; /* External Post-divider */
pxl_pllparam      549 drivers/gpu/drm/bridge/tc358767.c 	pxl_pllparam |= IN_SEL_REFCLK; /* Use RefClk as PLL input */
pxl_pllparam      550 drivers/gpu/drm/bridge/tc358767.c 	pxl_pllparam |= best_div << 8; /* Divider for PLL RefClk */
pxl_pllparam      551 drivers/gpu/drm/bridge/tc358767.c 	pxl_pllparam |= best_mul; /* Multiplier for PLL */
pxl_pllparam      553 drivers/gpu/drm/bridge/tc358767.c 	ret = regmap_write(tc->regmap, PXL_PLLPARAM, pxl_pllparam);