pw_idx 319 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->hsw.idx; pw_idx 323 drivers/gpu/drm/i915/display/intel_display_power.c HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) { pw_idx 334 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx) pw_idx 336 drivers/gpu/drm/i915/display/intel_display_power.c u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx); pw_idx 352 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->hsw.idx; pw_idx 366 drivers/gpu/drm/i915/display/intel_display_power.c HSW_PWR_WELL_CTL_STATE(pw_idx))) || pw_idx 367 drivers/gpu/drm/i915/display/intel_display_power.c (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1); pw_idx 388 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->hsw.idx; pw_idx 394 drivers/gpu/drm/i915/display/intel_display_power.c pg = INTEL_GEN(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) : pw_idx 395 drivers/gpu/drm/i915/display/intel_display_power.c SKL_PW_CTL_IDX_TO_PG(pw_idx); pw_idx 408 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); pw_idx 413 drivers/gpu/drm/i915/display/intel_display_power.c pw_idx >= GLK_PW_CTL_IDX_AUX_B && pw_idx 414 drivers/gpu/drm/i915/display/intel_display_power.c pw_idx <= CNL_PW_CTL_IDX_AUX_F) { pw_idx 415 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(CNL_AUX_ANAOVRD1(pw_idx)); pw_idx 417 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(CNL_AUX_ANAOVRD1(pw_idx), val); pw_idx 432 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->hsw.idx; pw_idx 439 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); pw_idx 443 drivers/gpu/drm/i915/display/intel_display_power.c #define ICL_AUX_PW_TO_PHY(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) pw_idx 450 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->hsw.idx; pw_idx 451 drivers/gpu/drm/i915/display/intel_display_power.c enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); pw_idx 456 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->driver, val | HSW_PWR_WELL_CTL_REQ(pw_idx)); pw_idx 472 drivers/gpu/drm/i915/display/intel_display_power.c pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= wa_idx_max && pw_idx 474 drivers/gpu/drm/i915/display/intel_display_power.c val = I915_READ(ICL_AUX_ANAOVRD1(pw_idx)); pw_idx 476 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(ICL_AUX_ANAOVRD1(pw_idx), val); pw_idx 485 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->hsw.idx; pw_idx 486 drivers/gpu/drm/i915/display/intel_display_power.c enum phy phy = ICL_AUX_PW_TO_PHY(pw_idx); pw_idx 495 drivers/gpu/drm/i915/display/intel_display_power.c I915_WRITE(regs->driver, val & ~HSW_PWR_WELL_CTL_REQ(pw_idx)); pw_idx 500 drivers/gpu/drm/i915/display/intel_display_power.c #define ICL_AUX_PW_TO_CH(pw_idx) \ pw_idx 501 drivers/gpu/drm/i915/display/intel_display_power.c ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A) pw_idx 503 drivers/gpu/drm/i915/display/intel_display_power.c #define ICL_TBT_AUX_PW_TO_CH(pw_idx) \ pw_idx 504 drivers/gpu/drm/i915/display/intel_display_power.c ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C) pw_idx 509 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->hsw.idx; pw_idx 511 drivers/gpu/drm/i915/display/intel_display_power.c return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) : pw_idx 512 drivers/gpu/drm/i915/display/intel_display_power.c ICL_AUX_PW_TO_CH(pw_idx); pw_idx 618 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->hsw.idx; pw_idx 619 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) | pw_idx 620 drivers/gpu/drm/i915/display/intel_display_power.c HSW_PWR_WELL_CTL_STATE(pw_idx); pw_idx 898 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->hsw.idx; pw_idx 899 drivers/gpu/drm/i915/display/intel_display_power.c u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx); pw_idx 1059 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->vlv.idx; pw_idx 1064 drivers/gpu/drm/i915/display/intel_display_power.c mask = PUNIT_PWRGT_MASK(pw_idx); pw_idx 1065 drivers/gpu/drm/i915/display/intel_display_power.c state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) : pw_idx 1066 drivers/gpu/drm/i915/display/intel_display_power.c PUNIT_PWRGT_PWR_GATE(pw_idx); pw_idx 1107 drivers/gpu/drm/i915/display/intel_display_power.c int pw_idx = power_well->desc->vlv.idx; pw_idx 1113 drivers/gpu/drm/i915/display/intel_display_power.c mask = PUNIT_PWRGT_MASK(pw_idx); pw_idx 1114 drivers/gpu/drm/i915/display/intel_display_power.c ctrl = PUNIT_PWRGT_PWR_ON(pw_idx); pw_idx 1123 drivers/gpu/drm/i915/display/intel_display_power.c WARN_ON(state != PUNIT_PWRGT_PWR_ON(pw_idx) && pw_idx 1124 drivers/gpu/drm/i915/display/intel_display_power.c state != PUNIT_PWRGT_PWR_GATE(pw_idx)); pw_idx 1150 drivers/gpu/drm/i915/i915_reg.h #define PUNIT_PWRGT_MASK(pw_idx) (3 << ((pw_idx) * 2)) pw_idx 1151 drivers/gpu/drm/i915/i915_reg.h #define PUNIT_PWRGT_PWR_ON(pw_idx) (0 << ((pw_idx) * 2)) pw_idx 1152 drivers/gpu/drm/i915/i915_reg.h #define PUNIT_PWRGT_CLK_GATE(pw_idx) (1 << ((pw_idx) * 2)) pw_idx 1153 drivers/gpu/drm/i915/i915_reg.h #define PUNIT_PWRGT_RESET(pw_idx) (2 << ((pw_idx) * 2)) pw_idx 1154 drivers/gpu/drm/i915/i915_reg.h #define PUNIT_PWRGT_PWR_GATE(pw_idx) (3 << ((pw_idx) * 2)) pw_idx 9132 drivers/gpu/drm/i915/i915_reg.h #define HSW_PWR_WELL_CTL_REQ(pw_idx) (0x2 << ((pw_idx) * 2)) pw_idx 9133 drivers/gpu/drm/i915/i915_reg.h #define HSW_PWR_WELL_CTL_STATE(pw_idx) (0x1 << ((pw_idx) * 2)) pw_idx 9225 drivers/gpu/drm/i915/i915_reg.h #define SKL_PW_CTL_IDX_TO_PG(pw_idx) \ pw_idx 9226 drivers/gpu/drm/i915/i915_reg.h ((pw_idx) - SKL_PW_CTL_IDX_PW_1 + SKL_PG1) pw_idx 9231 drivers/gpu/drm/i915/i915_reg.h #define ICL_PW_CTL_IDX_TO_PG(pw_idx) \ pw_idx 9232 drivers/gpu/drm/i915/i915_reg.h ((pw_idx) - ICL_PW_CTL_IDX_PW_1 + SKL_PG1) pw_idx 9235 drivers/gpu/drm/i915/i915_reg.h #define _CNL_AUX_REG_IDX(pw_idx) ((pw_idx) - GLK_PW_CTL_IDX_AUX_B) pw_idx 9240 drivers/gpu/drm/i915/i915_reg.h #define CNL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_CNL_AUX_REG_IDX(pw_idx), \ pw_idx 9248 drivers/gpu/drm/i915/i915_reg.h #define _ICL_AUX_REG_IDX(pw_idx) ((pw_idx) - ICL_PW_CTL_IDX_AUX_A) pw_idx 9252 drivers/gpu/drm/i915/i915_reg.h #define ICL_AUX_ANAOVRD1(pw_idx) _MMIO(_PICK(_ICL_AUX_REG_IDX(pw_idx), \