pvt               156 arch/s390/kernel/cache.c 	unsigned int level, idx, pvt;
pvt               167 arch/s390/kernel/cache.c 		pvt = (ct.ci[level].scope == CACHE_SCOPE_PRIVATE) ? 1 : 0;
pvt               170 arch/s390/kernel/cache.c 			ci_leaf_init(this_leaf++, pvt, CACHE_TYPE_DATA, level, cpu);
pvt               171 arch/s390/kernel/cache.c 			ci_leaf_init(this_leaf++, pvt, CACHE_TYPE_INST, level, cpu);
pvt               173 arch/s390/kernel/cache.c 			ci_leaf_init(this_leaf++, pvt, ctype, level, cpu);
pvt                90 drivers/edac/amd64_edac.c static void f15h_select_dct(struct amd64_pvt *pvt, u8 dct)
pvt                94 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F1, DCT_CFG_SEL, &reg);
pvt                95 drivers/edac/amd64_edac.c 	reg &= (pvt->model == 0x30) ? ~3 : ~1;
pvt                97 drivers/edac/amd64_edac.c 	amd64_write_pci_cfg(pvt->F1, DCT_CFG_SEL, reg);
pvt               114 drivers/edac/amd64_edac.c static inline int amd64_read_dct_pci_cfg(struct amd64_pvt *pvt, u8 dct,
pvt               117 drivers/edac/amd64_edac.c 	switch (pvt->fam) {
pvt               130 drivers/edac/amd64_edac.c 			if (dct_ganging_enabled(pvt))
pvt               142 drivers/edac/amd64_edac.c 		dct = (dct && pvt->model == 0x30) ? 3 : dct;
pvt               143 drivers/edac/amd64_edac.c 		f15h_select_dct(pvt, dct);
pvt               154 drivers/edac/amd64_edac.c 	return amd64_read_pci_cfg(pvt->F2, offset, val);
pvt               171 drivers/edac/amd64_edac.c static inline void __f17h_set_scrubval(struct amd64_pvt *pvt, u32 scrubval)
pvt               180 drivers/edac/amd64_edac.c 		pci_write_bits32(pvt->F6, F17H_SCR_LIMIT_ADDR, scrubval, 0xF);
pvt               181 drivers/edac/amd64_edac.c 		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 1, 0x1);
pvt               183 drivers/edac/amd64_edac.c 		pci_write_bits32(pvt->F6, F17H_SCR_BASE_ADDR, 0, 0x1);
pvt               190 drivers/edac/amd64_edac.c static int __set_scrub_rate(struct amd64_pvt *pvt, u32 new_bw, u32 min_rate)
pvt               218 drivers/edac/amd64_edac.c 	if (pvt->fam == 0x17 || pvt->fam == 0x18) {
pvt               219 drivers/edac/amd64_edac.c 		__f17h_set_scrubval(pvt, scrubval);
pvt               220 drivers/edac/amd64_edac.c 	} else if (pvt->fam == 0x15 && pvt->model == 0x60) {
pvt               221 drivers/edac/amd64_edac.c 		f15h_select_dct(pvt, 0);
pvt               222 drivers/edac/amd64_edac.c 		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
pvt               223 drivers/edac/amd64_edac.c 		f15h_select_dct(pvt, 1);
pvt               224 drivers/edac/amd64_edac.c 		pci_write_bits32(pvt->F2, F15H_M60H_SCRCTRL, scrubval, 0x001F);
pvt               226 drivers/edac/amd64_edac.c 		pci_write_bits32(pvt->F3, SCRCTRL, scrubval, 0x001F);
pvt               237 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt               240 drivers/edac/amd64_edac.c 	if (pvt->fam == 0xf)
pvt               243 drivers/edac/amd64_edac.c 	if (pvt->fam == 0x15) {
pvt               245 drivers/edac/amd64_edac.c 		if (pvt->model < 0x10)
pvt               246 drivers/edac/amd64_edac.c 			f15h_select_dct(pvt, 0);
pvt               248 drivers/edac/amd64_edac.c 		if (pvt->model == 0x60)
pvt               251 drivers/edac/amd64_edac.c 	return __set_scrub_rate(pvt, bw, min_scrubrate);
pvt               256 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt               260 drivers/edac/amd64_edac.c 	switch (pvt->fam) {
pvt               263 drivers/edac/amd64_edac.c 		if (pvt->model < 0x10)
pvt               264 drivers/edac/amd64_edac.c 			f15h_select_dct(pvt, 0);
pvt               266 drivers/edac/amd64_edac.c 		if (pvt->model == 0x60)
pvt               267 drivers/edac/amd64_edac.c 			amd64_read_pci_cfg(pvt->F2, F15H_M60H_SCRCTRL, &scrubval);
pvt               272 drivers/edac/amd64_edac.c 		amd64_read_pci_cfg(pvt->F6, F17H_SCR_BASE_ADDR, &scrubval);
pvt               274 drivers/edac/amd64_edac.c 			amd64_read_pci_cfg(pvt->F6, F17H_SCR_LIMIT_ADDR, &scrubval);
pvt               283 drivers/edac/amd64_edac.c 		amd64_read_pci_cfg(pvt->F3, SCRCTRL, &scrubval);
pvt               302 drivers/edac/amd64_edac.c static bool base_limit_match(struct amd64_pvt *pvt, u64 sys_addr, u8 nid)
pvt               314 drivers/edac/amd64_edac.c 	return ((addr >= get_dram_base(pvt, nid)) &&
pvt               315 drivers/edac/amd64_edac.c 		(addr <= get_dram_limit(pvt, nid)));
pvt               327 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt;
pvt               335 drivers/edac/amd64_edac.c 	pvt = mci->pvt_info;
pvt               342 drivers/edac/amd64_edac.c 	intlv_en = dram_intlv_en(pvt, 0);
pvt               346 drivers/edac/amd64_edac.c 			if (base_limit_match(pvt, sys_addr, node_id))
pvt               362 drivers/edac/amd64_edac.c 		if ((dram_intlv_sel(pvt, node_id) & intlv_en) == bits)
pvt               370 drivers/edac/amd64_edac.c 	if (unlikely(!base_limit_match(pvt, sys_addr, node_id))) {
pvt               391 drivers/edac/amd64_edac.c static void get_cs_base_and_mask(struct amd64_pvt *pvt, int csrow, u8 dct,
pvt               397 drivers/edac/amd64_edac.c 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
pvt               398 drivers/edac/amd64_edac.c 		csbase		= pvt->csels[dct].csbases[csrow];
pvt               399 drivers/edac/amd64_edac.c 		csmask		= pvt->csels[dct].csmasks[csrow];
pvt               408 drivers/edac/amd64_edac.c 	} else if (pvt->fam == 0x16 ||
pvt               409 drivers/edac/amd64_edac.c 		  (pvt->fam == 0x15 && pvt->model >= 0x30)) {
pvt               410 drivers/edac/amd64_edac.c 		csbase          = pvt->csels[dct].csbases[csrow];
pvt               411 drivers/edac/amd64_edac.c 		csmask          = pvt->csels[dct].csmasks[csrow >> 1];
pvt               426 drivers/edac/amd64_edac.c 		csbase		= pvt->csels[dct].csbases[csrow];
pvt               427 drivers/edac/amd64_edac.c 		csmask		= pvt->csels[dct].csmasks[csrow >> 1];
pvt               430 drivers/edac/amd64_edac.c 		if (pvt->fam == 0x15)
pvt               447 drivers/edac/amd64_edac.c #define for_each_chip_select(i, dct, pvt) \
pvt               448 drivers/edac/amd64_edac.c 	for (i = 0; i < pvt->csels[dct].b_cnt; i++)
pvt               450 drivers/edac/amd64_edac.c #define chip_select_base(i, dct, pvt) \
pvt               451 drivers/edac/amd64_edac.c 	pvt->csels[dct].csbases[i]
pvt               453 drivers/edac/amd64_edac.c #define for_each_chip_select_mask(i, dct, pvt) \
pvt               454 drivers/edac/amd64_edac.c 	for (i = 0; i < pvt->csels[dct].m_cnt; i++)
pvt               465 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt;
pvt               469 drivers/edac/amd64_edac.c 	pvt = mci->pvt_info;
pvt               471 drivers/edac/amd64_edac.c 	for_each_chip_select(csrow, 0, pvt) {
pvt               472 drivers/edac/amd64_edac.c 		if (!csrow_enabled(csrow, 0, pvt))
pvt               475 drivers/edac/amd64_edac.c 		get_cs_base_and_mask(pvt, csrow, 0, &base, &mask);
pvt               482 drivers/edac/amd64_edac.c 				 pvt->mc_node_id);
pvt               488 drivers/edac/amd64_edac.c 		 (unsigned long)input_addr, pvt->mc_node_id);
pvt               512 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt               515 drivers/edac/amd64_edac.c 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_E) {
pvt               517 drivers/edac/amd64_edac.c 			 pvt->ext_model, pvt->mc_node_id);
pvt               522 drivers/edac/amd64_edac.c 	if (pvt->fam >= 0x10 && !dhar_mem_hoist_valid(pvt)) {
pvt               527 drivers/edac/amd64_edac.c 	if (!dhar_valid(pvt)) {
pvt               529 drivers/edac/amd64_edac.c 			 pvt->mc_node_id);
pvt               551 drivers/edac/amd64_edac.c 	*hole_base = dhar_base(pvt);
pvt               554 drivers/edac/amd64_edac.c 	*hole_offset = (pvt->fam > 0xf) ? f10_dhar_offset(pvt)
pvt               555 drivers/edac/amd64_edac.c 					: k8_dhar_offset(pvt);
pvt               558 drivers/edac/amd64_edac.c 		 pvt->mc_node_id, (unsigned long)*hole_base,
pvt               596 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt               600 drivers/edac/amd64_edac.c 	dram_base = get_dram_base(pvt, pvt->mc_node_id);
pvt               652 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt;
pvt               656 drivers/edac/amd64_edac.c 	pvt = mci->pvt_info;
pvt               662 drivers/edac/amd64_edac.c 	intlv_shift = num_node_interleave_bits(dram_intlv_en(pvt, 0));
pvt               724 drivers/edac/amd64_edac.c static unsigned long determine_edac_cap(struct amd64_pvt *pvt)
pvt               729 drivers/edac/amd64_edac.c 	if (pvt->umc) {
pvt               733 drivers/edac/amd64_edac.c 			if (!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT))
pvt               739 drivers/edac/amd64_edac.c 			if (pvt->umc[i].umc_cfg & BIT(12))
pvt               746 drivers/edac/amd64_edac.c 		bit = (pvt->fam > 0xf || pvt->ext_model >= K8_REV_F)
pvt               750 drivers/edac/amd64_edac.c 		if (pvt->dclr0 & BIT(bit))
pvt               759 drivers/edac/amd64_edac.c static void debug_dump_dramcfg_low(struct amd64_pvt *pvt, u32 dclr, int chan)
pvt               763 drivers/edac/amd64_edac.c 	if (pvt->dram_type == MEM_LRDDR3) {
pvt               764 drivers/edac/amd64_edac.c 		u32 dcsm = pvt->csels[chan].csmasks[0];
pvt               780 drivers/edac/amd64_edac.c 	if (pvt->fam == 0x10)
pvt               799 drivers/edac/amd64_edac.c static int f17_get_cs_mode(int dimm, u8 ctrl, struct amd64_pvt *pvt)
pvt               803 drivers/edac/amd64_edac.c 	if (csrow_enabled(2 * dimm, ctrl, pvt))
pvt               806 drivers/edac/amd64_edac.c 	if (csrow_enabled(2 * dimm + 1, ctrl, pvt))
pvt               810 drivers/edac/amd64_edac.c 	if (csrow_sec_enabled(2 * dimm + 1, ctrl, pvt))
pvt               816 drivers/edac/amd64_edac.c static void debug_display_dimm_sizes_df(struct amd64_pvt *pvt, u8 ctrl)
pvt               826 drivers/edac/amd64_edac.c 		cs_mode = f17_get_cs_mode(dimm, ctrl, pvt);
pvt               828 drivers/edac/amd64_edac.c 		size0 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs0);
pvt               829 drivers/edac/amd64_edac.c 		size1 = pvt->ops->dbam_to_cs(pvt, ctrl, cs_mode, cs1);
pvt               837 drivers/edac/amd64_edac.c static void __dump_misc_regs_df(struct amd64_pvt *pvt)
pvt               844 drivers/edac/amd64_edac.c 		umc = &pvt->umc[i];
pvt               851 drivers/edac/amd64_edac.c 		amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ECC_BAD_SYMBOL, &tmp);
pvt               854 drivers/edac/amd64_edac.c 		amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_UMC_CAP, &tmp);
pvt               868 drivers/edac/amd64_edac.c 		if (pvt->dram_type == MEM_LRDDR4) {
pvt               869 drivers/edac/amd64_edac.c 			amd_smn_read(pvt->mc_node_id, umc_base + UMCCH_ADDR_CFG, &tmp);
pvt               874 drivers/edac/amd64_edac.c 		debug_display_dimm_sizes_df(pvt, i);
pvt               878 drivers/edac/amd64_edac.c 		 pvt->dhar, dhar_base(pvt));
pvt               882 drivers/edac/amd64_edac.c static void __dump_misc_regs(struct amd64_pvt *pvt)
pvt               884 drivers/edac/amd64_edac.c 	edac_dbg(1, "F3xE8 (NB Cap): 0x%08x\n", pvt->nbcap);
pvt               887 drivers/edac/amd64_edac.c 		 (pvt->nbcap & NBCAP_DCT_DUAL) ? "yes" : "no");
pvt               890 drivers/edac/amd64_edac.c 		 (pvt->nbcap & NBCAP_SECDED) ? "yes" : "no",
pvt               891 drivers/edac/amd64_edac.c 		 (pvt->nbcap & NBCAP_CHIPKILL) ? "yes" : "no");
pvt               893 drivers/edac/amd64_edac.c 	debug_dump_dramcfg_low(pvt, pvt->dclr0, 0);
pvt               895 drivers/edac/amd64_edac.c 	edac_dbg(1, "F3xB0 (Online Spare): 0x%08x\n", pvt->online_spare);
pvt               898 drivers/edac/amd64_edac.c 		 pvt->dhar, dhar_base(pvt),
pvt               899 drivers/edac/amd64_edac.c 		 (pvt->fam == 0xf) ? k8_dhar_offset(pvt)
pvt               900 drivers/edac/amd64_edac.c 				   : f10_dhar_offset(pvt));
pvt               902 drivers/edac/amd64_edac.c 	debug_display_dimm_sizes(pvt, 0);
pvt               905 drivers/edac/amd64_edac.c 	if (pvt->fam == 0xf)
pvt               908 drivers/edac/amd64_edac.c 	debug_display_dimm_sizes(pvt, 1);
pvt               911 drivers/edac/amd64_edac.c 	if (!dct_ganging_enabled(pvt))
pvt               912 drivers/edac/amd64_edac.c 		debug_dump_dramcfg_low(pvt, pvt->dclr1, 1);
pvt               916 drivers/edac/amd64_edac.c static void dump_misc_regs(struct amd64_pvt *pvt)
pvt               918 drivers/edac/amd64_edac.c 	if (pvt->umc)
pvt               919 drivers/edac/amd64_edac.c 		__dump_misc_regs_df(pvt);
pvt               921 drivers/edac/amd64_edac.c 		__dump_misc_regs(pvt);
pvt               923 drivers/edac/amd64_edac.c 	edac_dbg(1, "  DramHoleValid: %s\n", dhar_valid(pvt) ? "yes" : "no");
pvt               925 drivers/edac/amd64_edac.c 	amd64_info("using x%u syndromes.\n", pvt->ecc_sym_sz);
pvt               931 drivers/edac/amd64_edac.c static void prep_chip_selects(struct amd64_pvt *pvt)
pvt               933 drivers/edac/amd64_edac.c 	if (pvt->fam == 0xf && pvt->ext_model < K8_REV_F) {
pvt               934 drivers/edac/amd64_edac.c 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
pvt               935 drivers/edac/amd64_edac.c 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 8;
pvt               936 drivers/edac/amd64_edac.c 	} else if (pvt->fam == 0x15 && pvt->model == 0x30) {
pvt               937 drivers/edac/amd64_edac.c 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 4;
pvt               938 drivers/edac/amd64_edac.c 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 2;
pvt               939 drivers/edac/amd64_edac.c 	} else if (pvt->fam >= 0x17) {
pvt               943 drivers/edac/amd64_edac.c 			pvt->csels[umc].b_cnt = 4;
pvt               944 drivers/edac/amd64_edac.c 			pvt->csels[umc].m_cnt = 2;
pvt               948 drivers/edac/amd64_edac.c 		pvt->csels[0].b_cnt = pvt->csels[1].b_cnt = 8;
pvt               949 drivers/edac/amd64_edac.c 		pvt->csels[0].m_cnt = pvt->csels[1].m_cnt = 4;
pvt               953 drivers/edac/amd64_edac.c static void read_umc_base_mask(struct amd64_pvt *pvt)
pvt               967 drivers/edac/amd64_edac.c 		for_each_chip_select(cs, umc, pvt) {
pvt               968 drivers/edac/amd64_edac.c 			base = &pvt->csels[umc].csbases[cs];
pvt               969 drivers/edac/amd64_edac.c 			base_sec = &pvt->csels[umc].csbases_sec[cs];
pvt               974 drivers/edac/amd64_edac.c 			if (!amd_smn_read(pvt->mc_node_id, base_reg, base))
pvt               978 drivers/edac/amd64_edac.c 			if (!amd_smn_read(pvt->mc_node_id, base_reg_sec, base_sec))
pvt               986 drivers/edac/amd64_edac.c 		for_each_chip_select_mask(cs, umc, pvt) {
pvt               987 drivers/edac/amd64_edac.c 			mask = &pvt->csels[umc].csmasks[cs];
pvt               988 drivers/edac/amd64_edac.c 			mask_sec = &pvt->csels[umc].csmasks_sec[cs];
pvt               993 drivers/edac/amd64_edac.c 			if (!amd_smn_read(pvt->mc_node_id, mask_reg, mask))
pvt               997 drivers/edac/amd64_edac.c 			if (!amd_smn_read(pvt->mc_node_id, mask_reg_sec, mask_sec))
pvt              1007 drivers/edac/amd64_edac.c static void read_dct_base_mask(struct amd64_pvt *pvt)
pvt              1011 drivers/edac/amd64_edac.c 	prep_chip_selects(pvt);
pvt              1013 drivers/edac/amd64_edac.c 	if (pvt->umc)
pvt              1014 drivers/edac/amd64_edac.c 		return read_umc_base_mask(pvt);
pvt              1016 drivers/edac/amd64_edac.c 	for_each_chip_select(cs, 0, pvt) {
pvt              1019 drivers/edac/amd64_edac.c 		u32 *base0 = &pvt->csels[0].csbases[cs];
pvt              1020 drivers/edac/amd64_edac.c 		u32 *base1 = &pvt->csels[1].csbases[cs];
pvt              1022 drivers/edac/amd64_edac.c 		if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, base0))
pvt              1026 drivers/edac/amd64_edac.c 		if (pvt->fam == 0xf)
pvt              1029 drivers/edac/amd64_edac.c 		if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, base1))
pvt              1031 drivers/edac/amd64_edac.c 				 cs, *base1, (pvt->fam == 0x10) ? reg1
pvt              1035 drivers/edac/amd64_edac.c 	for_each_chip_select_mask(cs, 0, pvt) {
pvt              1038 drivers/edac/amd64_edac.c 		u32 *mask0 = &pvt->csels[0].csmasks[cs];
pvt              1039 drivers/edac/amd64_edac.c 		u32 *mask1 = &pvt->csels[1].csmasks[cs];
pvt              1041 drivers/edac/amd64_edac.c 		if (!amd64_read_dct_pci_cfg(pvt, 0, reg0, mask0))
pvt              1045 drivers/edac/amd64_edac.c 		if (pvt->fam == 0xf)
pvt              1048 drivers/edac/amd64_edac.c 		if (!amd64_read_dct_pci_cfg(pvt, 1, reg0, mask1))
pvt              1050 drivers/edac/amd64_edac.c 				 cs, *mask1, (pvt->fam == 0x10) ? reg1
pvt              1055 drivers/edac/amd64_edac.c static void determine_memory_type(struct amd64_pvt *pvt)
pvt              1059 drivers/edac/amd64_edac.c 	switch (pvt->fam) {
pvt              1061 drivers/edac/amd64_edac.c 		if (pvt->ext_model >= K8_REV_F)
pvt              1064 drivers/edac/amd64_edac.c 		pvt->dram_type = (pvt->dclr0 & BIT(18)) ? MEM_DDR : MEM_RDDR;
pvt              1068 drivers/edac/amd64_edac.c 		if (pvt->dchr0 & DDR3_MODE)
pvt              1071 drivers/edac/amd64_edac.c 		pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR2 : MEM_RDDR2;
pvt              1075 drivers/edac/amd64_edac.c 		if (pvt->model < 0x60)
pvt              1087 drivers/edac/amd64_edac.c 		amd64_read_dct_pci_cfg(pvt, 0, DRAM_CONTROL, &dram_ctrl);
pvt              1088 drivers/edac/amd64_edac.c 		dcsm = pvt->csels[0].csmasks[0];
pvt              1091 drivers/edac/amd64_edac.c 			pvt->dram_type = MEM_DDR4;
pvt              1092 drivers/edac/amd64_edac.c 		else if (pvt->dclr0 & BIT(16))
pvt              1093 drivers/edac/amd64_edac.c 			pvt->dram_type = MEM_DDR3;
pvt              1095 drivers/edac/amd64_edac.c 			pvt->dram_type = MEM_LRDDR3;
pvt              1097 drivers/edac/amd64_edac.c 			pvt->dram_type = MEM_RDDR3;
pvt              1106 drivers/edac/amd64_edac.c 		if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(5))
pvt              1107 drivers/edac/amd64_edac.c 			pvt->dram_type = MEM_LRDDR4;
pvt              1108 drivers/edac/amd64_edac.c 		else if ((pvt->umc[0].dimm_cfg | pvt->umc[1].dimm_cfg) & BIT(4))
pvt              1109 drivers/edac/amd64_edac.c 			pvt->dram_type = MEM_RDDR4;
pvt              1111 drivers/edac/amd64_edac.c 			pvt->dram_type = MEM_DDR4;
pvt              1115 drivers/edac/amd64_edac.c 		WARN(1, KERN_ERR "%s: Family??? 0x%x\n", __func__, pvt->fam);
pvt              1116 drivers/edac/amd64_edac.c 		pvt->dram_type = MEM_EMPTY;
pvt              1121 drivers/edac/amd64_edac.c 	pvt->dram_type = (pvt->dclr0 & BIT(16)) ? MEM_DDR3 : MEM_RDDR3;
pvt              1125 drivers/edac/amd64_edac.c static int k8_early_channel_count(struct amd64_pvt *pvt)
pvt              1129 drivers/edac/amd64_edac.c 	if (pvt->ext_model >= K8_REV_F)
pvt              1131 drivers/edac/amd64_edac.c 		flag = pvt->dclr0 & WIDTH_128;
pvt              1134 drivers/edac/amd64_edac.c 		flag = pvt->dclr0 & REVE_WIDTH_128;
pvt              1137 drivers/edac/amd64_edac.c 	pvt->dclr1 = 0;
pvt              1143 drivers/edac/amd64_edac.c static u64 get_error_address(struct amd64_pvt *pvt, struct mce *m)
pvt              1155 drivers/edac/amd64_edac.c 	pvt = mci->pvt_info;
pvt              1157 drivers/edac/amd64_edac.c 	if (pvt->fam == 0xf) {
pvt              1167 drivers/edac/amd64_edac.c 	if (pvt->fam == 0x15) {
pvt              1176 drivers/edac/amd64_edac.c 		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_LIM, &tmp);
pvt              1191 drivers/edac/amd64_edac.c 		amd64_read_pci_cfg(pvt->F1, DRAM_LOCAL_NODE_BASE, &tmp);
pvt              1224 drivers/edac/amd64_edac.c static void read_dram_base_limit_regs(struct amd64_pvt *pvt, unsigned range)
pvt              1232 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_LO + off,  &pvt->ranges[range].base.lo);
pvt              1233 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_LO + off, &pvt->ranges[range].lim.lo);
pvt              1235 drivers/edac/amd64_edac.c 	if (pvt->fam == 0xf)
pvt              1238 drivers/edac/amd64_edac.c 	if (!dram_rw(pvt, range))
pvt              1241 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F1, DRAM_BASE_HI + off,  &pvt->ranges[range].base.hi);
pvt              1242 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F1, DRAM_LIMIT_HI + off, &pvt->ranges[range].lim.hi);
pvt              1245 drivers/edac/amd64_edac.c 	if (pvt->fam != 0x15)
pvt              1248 drivers/edac/amd64_edac.c 	nb = node_to_amd_nb(dram_dst_node(pvt, range));
pvt              1252 drivers/edac/amd64_edac.c 	if (pvt->model == 0x60)
pvt              1254 drivers/edac/amd64_edac.c 	else if (pvt->model == 0x30)
pvt              1265 drivers/edac/amd64_edac.c 	pvt->ranges[range].lim.lo &= GENMASK_ULL(15, 0);
pvt              1268 drivers/edac/amd64_edac.c 	pvt->ranges[range].lim.lo |= ((llim & 0x1fff) << 3 | 0x7) << 16;
pvt              1270 drivers/edac/amd64_edac.c 	pvt->ranges[range].lim.hi &= GENMASK_ULL(7, 0);
pvt              1273 drivers/edac/amd64_edac.c 	pvt->ranges[range].lim.hi |= llim >> 13;
pvt              1281 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt              1305 drivers/edac/amd64_edac.c 	if (pvt->nbcfg & NBCFG_CHIPKILL) {
pvt              1346 drivers/edac/amd64_edac.c static int k8_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
pvt              1349 drivers/edac/amd64_edac.c 	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
pvt              1351 drivers/edac/amd64_edac.c 	if (pvt->ext_model >= K8_REV_F) {
pvt              1355 drivers/edac/amd64_edac.c 	else if (pvt->ext_model >= K8_REV_D) {
pvt              1401 drivers/edac/amd64_edac.c static int f1x_early_channel_count(struct amd64_pvt *pvt)
pvt              1406 drivers/edac/amd64_edac.c 	if (pvt->fam == 0x10 && (pvt->dclr0 & WIDTH_128))
pvt              1425 drivers/edac/amd64_edac.c 		u32 dbam = (i ? pvt->dbam1 : pvt->dbam0);
pvt              1443 drivers/edac/amd64_edac.c static int f17_early_channel_count(struct amd64_pvt *pvt)
pvt              1449 drivers/edac/amd64_edac.c 		channels += !!(pvt->umc[i].sdp_ctrl & UMC_SDP_INIT);
pvt              1513 drivers/edac/amd64_edac.c static int f10_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
pvt              1516 drivers/edac/amd64_edac.c 	u32 dclr = dct ? pvt->dclr1 : pvt->dclr0;
pvt              1520 drivers/edac/amd64_edac.c 	if (pvt->dchr0 & DDR3_MODE || pvt->dchr1 & DDR3_MODE)
pvt              1529 drivers/edac/amd64_edac.c static int f15_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
pvt              1538 drivers/edac/amd64_edac.c static int f15_m60h_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
pvt              1542 drivers/edac/amd64_edac.c 	u32 dcsm = pvt->csels[dct].csmasks[cs_mask_nr];
pvt              1546 drivers/edac/amd64_edac.c 	if (pvt->dram_type == MEM_DDR4) {
pvt              1551 drivers/edac/amd64_edac.c 	} else if (pvt->dram_type == MEM_LRDDR3) {
pvt              1571 drivers/edac/amd64_edac.c static int f16_dbam_to_chip_select(struct amd64_pvt *pvt, u8 dct,
pvt              1583 drivers/edac/amd64_edac.c static int f17_addr_mask_to_cs_size(struct amd64_pvt *pvt, u8 umc,
pvt              1611 drivers/edac/amd64_edac.c 		addr_mask_orig = pvt->csels[umc].csmasks_sec[dimm];
pvt              1613 drivers/edac/amd64_edac.c 		addr_mask_orig = pvt->csels[umc].csmasks[dimm];
pvt              1640 drivers/edac/amd64_edac.c static void read_dram_ctl_register(struct amd64_pvt *pvt)
pvt              1643 drivers/edac/amd64_edac.c 	if (pvt->fam == 0xf)
pvt              1646 drivers/edac/amd64_edac.c 	if (!amd64_read_pci_cfg(pvt->F2, DCT_SEL_LO, &pvt->dct_sel_lo)) {
pvt              1648 drivers/edac/amd64_edac.c 			 pvt->dct_sel_lo, dct_sel_baseaddr(pvt));
pvt              1651 drivers/edac/amd64_edac.c 			 (dct_ganging_enabled(pvt) ? "ganged" : "unganged"));
pvt              1653 drivers/edac/amd64_edac.c 		if (!dct_ganging_enabled(pvt))
pvt              1655 drivers/edac/amd64_edac.c 				 (dct_high_range_enabled(pvt) ? "yes" : "no"));
pvt              1658 drivers/edac/amd64_edac.c 			 (dct_data_intlv_enabled(pvt) ? "enabled" : "disabled"),
pvt              1659 drivers/edac/amd64_edac.c 			 (dct_memory_cleared(pvt) ? "yes" : "no"));
pvt              1663 drivers/edac/amd64_edac.c 			 (dct_interleave_enabled(pvt) ? "enabled" : "disabled"),
pvt              1664 drivers/edac/amd64_edac.c 			 dct_sel_interleave_addr(pvt));
pvt              1667 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F2, DCT_SEL_HI, &pvt->dct_sel_hi);
pvt              1674 drivers/edac/amd64_edac.c static u8 f15_m30h_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
pvt              1688 drivers/edac/amd64_edac.c 		u8 intlv_addr = dct_sel_interleave_addr(pvt);
pvt              1705 drivers/edac/amd64_edac.c static u8 f1x_determine_channel(struct amd64_pvt *pvt, u64 sys_addr,
pvt              1708 drivers/edac/amd64_edac.c 	u8 dct_sel_high = (pvt->dct_sel_lo >> 1) & 1;
pvt              1710 drivers/edac/amd64_edac.c 	if (dct_ganging_enabled(pvt))
pvt              1719 drivers/edac/amd64_edac.c 	if (dct_interleave_enabled(pvt)) {
pvt              1720 drivers/edac/amd64_edac.c 		u8 intlv_addr = dct_sel_interleave_addr(pvt);
pvt              1742 drivers/edac/amd64_edac.c 	if (dct_high_range_enabled(pvt))
pvt              1749 drivers/edac/amd64_edac.c static u64 f1x_get_norm_dct_addr(struct amd64_pvt *pvt, u8 range,
pvt              1754 drivers/edac/amd64_edac.c 	u64 dram_base		= get_dram_base(pvt, range);
pvt              1755 drivers/edac/amd64_edac.c 	u64 hole_off		= f10_dhar_offset(pvt);
pvt              1756 drivers/edac/amd64_edac.c 	u64 dct_sel_base_off	= (u64)(pvt->dct_sel_hi & 0xFFFFFC00) << 16;
pvt              1771 drivers/edac/amd64_edac.c 		     dct_sel_base_addr < dhar_base(pvt)) &&
pvt              1772 drivers/edac/amd64_edac.c 		    dhar_valid(pvt) &&
pvt              1787 drivers/edac/amd64_edac.c 		if (dhar_valid(pvt) && (sys_addr >= BIT_64(32)))
pvt              1800 drivers/edac/amd64_edac.c static int f10_process_possible_spare(struct amd64_pvt *pvt, u8 dct, int csrow)
pvt              1804 drivers/edac/amd64_edac.c 	if (online_spare_swap_done(pvt, dct) &&
pvt              1805 drivers/edac/amd64_edac.c 	    csrow == online_spare_bad_dramcs(pvt, dct)) {
pvt              1807 drivers/edac/amd64_edac.c 		for_each_chip_select(tmp_cs, dct, pvt) {
pvt              1808 drivers/edac/amd64_edac.c 			if (chip_select_base(tmp_cs, dct, pvt) & 0x2) {
pvt              1828 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt;
pvt              1837 drivers/edac/amd64_edac.c 	pvt = mci->pvt_info;
pvt              1841 drivers/edac/amd64_edac.c 	for_each_chip_select(csrow, dct, pvt) {
pvt              1842 drivers/edac/amd64_edac.c 		if (!csrow_enabled(csrow, dct, pvt))
pvt              1845 drivers/edac/amd64_edac.c 		get_cs_base_and_mask(pvt, csrow, dct, &cs_base, &cs_mask);
pvt              1856 drivers/edac/amd64_edac.c 			if (pvt->fam == 0x15 && pvt->model >= 0x30) {
pvt              1860 drivers/edac/amd64_edac.c 			cs_found = f10_process_possible_spare(pvt, dct, csrow);
pvt              1874 drivers/edac/amd64_edac.c static u64 f1x_swap_interleaved_region(struct amd64_pvt *pvt, u64 sys_addr)
pvt              1878 drivers/edac/amd64_edac.c 	if (pvt->fam == 0x10) {
pvt              1880 drivers/edac/amd64_edac.c 		if (pvt->model < 4 || (pvt->model < 0xa && pvt->stepping < 3))
pvt              1884 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F2, SWAP_INTLV_REG, &swap_reg);
pvt              1904 drivers/edac/amd64_edac.c static int f1x_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
pvt              1913 drivers/edac/amd64_edac.c 	u8 node_id    = dram_dst_node(pvt, range);
pvt              1914 drivers/edac/amd64_edac.c 	u8 intlv_en   = dram_intlv_en(pvt, range);
pvt              1915 drivers/edac/amd64_edac.c 	u32 intlv_sel = dram_intlv_sel(pvt, range);
pvt              1918 drivers/edac/amd64_edac.c 		 range, sys_addr, get_dram_limit(pvt, range));
pvt              1920 drivers/edac/amd64_edac.c 	if (dhar_valid(pvt) &&
pvt              1921 drivers/edac/amd64_edac.c 	    dhar_base(pvt) <= sys_addr &&
pvt              1931 drivers/edac/amd64_edac.c 	sys_addr = f1x_swap_interleaved_region(pvt, sys_addr);
pvt              1933 drivers/edac/amd64_edac.c 	dct_sel_base = dct_sel_baseaddr(pvt);
pvt              1939 drivers/edac/amd64_edac.c 	if (dct_high_range_enabled(pvt) &&
pvt              1940 drivers/edac/amd64_edac.c 	   !dct_ganging_enabled(pvt) &&
pvt              1944 drivers/edac/amd64_edac.c 	channel = f1x_determine_channel(pvt, sys_addr, high_range, intlv_en);
pvt              1946 drivers/edac/amd64_edac.c 	chan_addr = f1x_get_norm_dct_addr(pvt, range, sys_addr,
pvt              1955 drivers/edac/amd64_edac.c 	if (dct_interleave_enabled(pvt) &&
pvt              1956 drivers/edac/amd64_edac.c 	   !dct_high_range_enabled(pvt) &&
pvt              1957 drivers/edac/amd64_edac.c 	   !dct_ganging_enabled(pvt)) {
pvt              1959 drivers/edac/amd64_edac.c 		if (dct_sel_interleave_addr(pvt) != 1) {
pvt              1960 drivers/edac/amd64_edac.c 			if (dct_sel_interleave_addr(pvt) == 0x3)
pvt              1984 drivers/edac/amd64_edac.c static int f15_m30h_match_to_this_node(struct amd64_pvt *pvt, unsigned range,
pvt              1994 drivers/edac/amd64_edac.c 	u64 dhar_offset		= f10_dhar_offset(pvt);
pvt              1995 drivers/edac/amd64_edac.c 	u8 intlv_addr		= dct_sel_interleave_addr(pvt);
pvt              1996 drivers/edac/amd64_edac.c 	u8 node_id		= dram_dst_node(pvt, range);
pvt              1997 drivers/edac/amd64_edac.c 	u8 intlv_en		= dram_intlv_en(pvt, range);
pvt              1999 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &dct_cont_base_reg);
pvt              2000 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &dct_cont_limit_reg);
pvt              2006 drivers/edac/amd64_edac.c 		 range, sys_addr, get_dram_limit(pvt, range));
pvt              2008 drivers/edac/amd64_edac.c 	if (!(get_dram_base(pvt, range)  <= sys_addr) &&
pvt              2009 drivers/edac/amd64_edac.c 	    !(get_dram_limit(pvt, range) >= sys_addr))
pvt              2012 drivers/edac/amd64_edac.c 	if (dhar_valid(pvt) &&
pvt              2013 drivers/edac/amd64_edac.c 	    dhar_base(pvt) <= sys_addr &&
pvt              2021 drivers/edac/amd64_edac.c 	dct_base = (u64) dct_sel_baseaddr(pvt);
pvt              2035 drivers/edac/amd64_edac.c 	if (pvt->model >= 0x60)
pvt              2036 drivers/edac/amd64_edac.c 		channel = f1x_determine_channel(pvt, sys_addr, false, intlv_en);
pvt              2038 drivers/edac/amd64_edac.c 		channel = f15_m30h_determine_channel(pvt, sys_addr, intlv_en,
pvt              2078 drivers/edac/amd64_edac.c 		amd64_read_pci_cfg(pvt->F1,
pvt              2084 drivers/edac/amd64_edac.c 	f15h_select_dct(pvt, channel);
pvt              2106 drivers/edac/amd64_edac.c static int f1x_translate_sysaddr_to_cs(struct amd64_pvt *pvt,
pvt              2114 drivers/edac/amd64_edac.c 		if (!dram_rw(pvt, range))
pvt              2117 drivers/edac/amd64_edac.c 		if (pvt->fam == 0x15 && pvt->model >= 0x30)
pvt              2118 drivers/edac/amd64_edac.c 			cs_found = f15_m30h_match_to_this_node(pvt, range,
pvt              2122 drivers/edac/amd64_edac.c 		else if ((get_dram_base(pvt, range)  <= sys_addr) &&
pvt              2123 drivers/edac/amd64_edac.c 			 (get_dram_limit(pvt, range) >= sys_addr)) {
pvt              2124 drivers/edac/amd64_edac.c 			cs_found = f1x_match_to_this_node(pvt, range,
pvt              2143 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt              2147 drivers/edac/amd64_edac.c 	err->csrow = f1x_translate_sysaddr_to_cs(pvt, sys_addr, &err->channel);
pvt              2158 drivers/edac/amd64_edac.c 	if (dct_ganging_enabled(pvt))
pvt              2166 drivers/edac/amd64_edac.c static void debug_display_dimm_sizes(struct amd64_pvt *pvt, u8 ctrl)
pvt              2169 drivers/edac/amd64_edac.c 	u32 *dcsb = ctrl ? pvt->csels[1].csbases : pvt->csels[0].csbases;
pvt              2170 drivers/edac/amd64_edac.c 	u32 dbam  = ctrl ? pvt->dbam1 : pvt->dbam0;
pvt              2172 drivers/edac/amd64_edac.c 	if (pvt->fam == 0xf) {
pvt              2174 drivers/edac/amd64_edac.c 	       if (pvt->ext_model < K8_REV_F)
pvt              2180 drivers/edac/amd64_edac.c 	if (pvt->fam == 0x10) {
pvt              2181 drivers/edac/amd64_edac.c 		dbam = (ctrl && !dct_ganging_enabled(pvt)) ? pvt->dbam1
pvt              2182 drivers/edac/amd64_edac.c 							   : pvt->dbam0;
pvt              2183 drivers/edac/amd64_edac.c 		dcsb = (ctrl && !dct_ganging_enabled(pvt)) ?
pvt              2184 drivers/edac/amd64_edac.c 				 pvt->csels[1].csbases :
pvt              2185 drivers/edac/amd64_edac.c 				 pvt->csels[0].csbases;
pvt              2187 drivers/edac/amd64_edac.c 		dbam = pvt->dbam0;
pvt              2188 drivers/edac/amd64_edac.c 		dcsb = pvt->csels[1].csbases;
pvt              2206 drivers/edac/amd64_edac.c 			size0 = pvt->ops->dbam_to_cs(pvt, ctrl,
pvt              2212 drivers/edac/amd64_edac.c 			size1 = pvt->ops->dbam_to_cs(pvt, ctrl,
pvt              2476 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt              2479 drivers/edac/amd64_edac.c 	if (pvt->ecc_sym_sz == 8)
pvt              2482 drivers/edac/amd64_edac.c 					  pvt->ecc_sym_sz);
pvt              2483 drivers/edac/amd64_edac.c 	else if (pvt->ecc_sym_sz == 4)
pvt              2486 drivers/edac/amd64_edac.c 					  pvt->ecc_sym_sz);
pvt              2488 drivers/edac/amd64_edac.c 		amd64_warn("Illegal syndrome type: %u\n", pvt->ecc_sym_sz);
pvt              2492 drivers/edac/amd64_edac.c 	return map_err_sym_to_channel(err_sym, pvt->ecc_sym_sz);
pvt              2545 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt;
pvt              2556 drivers/edac/amd64_edac.c 	pvt = mci->pvt_info;
pvt              2568 drivers/edac/amd64_edac.c 	sys_addr = get_error_address(pvt, m);
pvt              2573 drivers/edac/amd64_edac.c 	pvt->ops->map_sysaddr_to_csrow(mci, sys_addr, &err);
pvt              2596 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt;
pvt              2604 drivers/edac/amd64_edac.c 	pvt = mci->pvt_info;
pvt              2629 drivers/edac/amd64_edac.c 	if (umc_normaddr_to_sysaddr(m->addr, pvt->mc_node_id, err.channel, &sys_addr)) {
pvt              2646 drivers/edac/amd64_edac.c reserve_mc_sibling_devs(struct amd64_pvt *pvt, u16 pci_id1, u16 pci_id2)
pvt              2648 drivers/edac/amd64_edac.c 	if (pvt->umc) {
pvt              2649 drivers/edac/amd64_edac.c 		pvt->F0 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
pvt              2650 drivers/edac/amd64_edac.c 		if (!pvt->F0) {
pvt              2655 drivers/edac/amd64_edac.c 		pvt->F6 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
pvt              2656 drivers/edac/amd64_edac.c 		if (!pvt->F6) {
pvt              2657 drivers/edac/amd64_edac.c 			pci_dev_put(pvt->F0);
pvt              2658 drivers/edac/amd64_edac.c 			pvt->F0 = NULL;
pvt              2664 drivers/edac/amd64_edac.c 		edac_dbg(1, "F0: %s\n", pci_name(pvt->F0));
pvt              2665 drivers/edac/amd64_edac.c 		edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
pvt              2666 drivers/edac/amd64_edac.c 		edac_dbg(1, "F6: %s\n", pci_name(pvt->F6));
pvt              2672 drivers/edac/amd64_edac.c 	pvt->F1 = pci_get_related_function(pvt->F3->vendor, pci_id1, pvt->F3);
pvt              2673 drivers/edac/amd64_edac.c 	if (!pvt->F1) {
pvt              2679 drivers/edac/amd64_edac.c 	pvt->F2 = pci_get_related_function(pvt->F3->vendor, pci_id2, pvt->F3);
pvt              2680 drivers/edac/amd64_edac.c 	if (!pvt->F2) {
pvt              2681 drivers/edac/amd64_edac.c 		pci_dev_put(pvt->F1);
pvt              2682 drivers/edac/amd64_edac.c 		pvt->F1 = NULL;
pvt              2688 drivers/edac/amd64_edac.c 	edac_dbg(1, "F1: %s\n", pci_name(pvt->F1));
pvt              2689 drivers/edac/amd64_edac.c 	edac_dbg(1, "F2: %s\n", pci_name(pvt->F2));
pvt              2690 drivers/edac/amd64_edac.c 	edac_dbg(1, "F3: %s\n", pci_name(pvt->F3));
pvt              2695 drivers/edac/amd64_edac.c static void free_mc_sibling_devs(struct amd64_pvt *pvt)
pvt              2697 drivers/edac/amd64_edac.c 	if (pvt->umc) {
pvt              2698 drivers/edac/amd64_edac.c 		pci_dev_put(pvt->F0);
pvt              2699 drivers/edac/amd64_edac.c 		pci_dev_put(pvt->F6);
pvt              2701 drivers/edac/amd64_edac.c 		pci_dev_put(pvt->F1);
pvt              2702 drivers/edac/amd64_edac.c 		pci_dev_put(pvt->F2);
pvt              2706 drivers/edac/amd64_edac.c static void determine_ecc_sym_sz(struct amd64_pvt *pvt)
pvt              2708 drivers/edac/amd64_edac.c 	pvt->ecc_sym_sz = 4;
pvt              2710 drivers/edac/amd64_edac.c 	if (pvt->umc) {
pvt              2715 drivers/edac/amd64_edac.c 			if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
pvt              2716 drivers/edac/amd64_edac.c 				if (pvt->umc[i].ecc_ctrl & BIT(9)) {
pvt              2717 drivers/edac/amd64_edac.c 					pvt->ecc_sym_sz = 16;
pvt              2719 drivers/edac/amd64_edac.c 				} else if (pvt->umc[i].ecc_ctrl & BIT(7)) {
pvt              2720 drivers/edac/amd64_edac.c 					pvt->ecc_sym_sz = 8;
pvt              2725 drivers/edac/amd64_edac.c 	} else if (pvt->fam >= 0x10) {
pvt              2728 drivers/edac/amd64_edac.c 		amd64_read_pci_cfg(pvt->F3, EXT_NB_MCA_CFG, &tmp);
pvt              2730 drivers/edac/amd64_edac.c 		if (pvt->fam != 0x16)
pvt              2731 drivers/edac/amd64_edac.c 			amd64_read_dct_pci_cfg(pvt, 1, DBAM0, &pvt->dbam1);
pvt              2734 drivers/edac/amd64_edac.c 		if ((pvt->fam > 0x10 || pvt->model > 7) && tmp & BIT(25))
pvt              2735 drivers/edac/amd64_edac.c 			pvt->ecc_sym_sz = 8;
pvt              2742 drivers/edac/amd64_edac.c static void __read_mc_regs_df(struct amd64_pvt *pvt)
pvt              2744 drivers/edac/amd64_edac.c 	u8 nid = pvt->mc_node_id;
pvt              2752 drivers/edac/amd64_edac.c 		umc = &pvt->umc[i];
pvt              2766 drivers/edac/amd64_edac.c static void read_mc_regs(struct amd64_pvt *pvt)
pvt              2775 drivers/edac/amd64_edac.c 	rdmsrl(MSR_K8_TOP_MEM1, pvt->top_mem);
pvt              2776 drivers/edac/amd64_edac.c 	edac_dbg(0, "  TOP_MEM:  0x%016llx\n", pvt->top_mem);
pvt              2781 drivers/edac/amd64_edac.c 		rdmsrl(MSR_K8_TOP_MEM2, pvt->top_mem2);
pvt              2782 drivers/edac/amd64_edac.c 		edac_dbg(0, "  TOP_MEM2: 0x%016llx\n", pvt->top_mem2);
pvt              2787 drivers/edac/amd64_edac.c 	if (pvt->umc) {
pvt              2788 drivers/edac/amd64_edac.c 		__read_mc_regs_df(pvt);
pvt              2789 drivers/edac/amd64_edac.c 		amd64_read_pci_cfg(pvt->F0, DF_DHAR, &pvt->dhar);
pvt              2794 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F3, NBCAP, &pvt->nbcap);
pvt              2796 drivers/edac/amd64_edac.c 	read_dram_ctl_register(pvt);
pvt              2802 drivers/edac/amd64_edac.c 		read_dram_base_limit_regs(pvt, range);
pvt              2804 drivers/edac/amd64_edac.c 		rw = dram_rw(pvt, range);
pvt              2810 drivers/edac/amd64_edac.c 			 get_dram_base(pvt, range),
pvt              2811 drivers/edac/amd64_edac.c 			 get_dram_limit(pvt, range));
pvt              2814 drivers/edac/amd64_edac.c 			 dram_intlv_en(pvt, range) ? "Enabled" : "Disabled",
pvt              2817 drivers/edac/amd64_edac.c 			 dram_intlv_sel(pvt, range),
pvt              2818 drivers/edac/amd64_edac.c 			 dram_dst_node(pvt, range));
pvt              2821 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F1, DHAR, &pvt->dhar);
pvt              2822 drivers/edac/amd64_edac.c 	amd64_read_dct_pci_cfg(pvt, 0, DBAM0, &pvt->dbam0);
pvt              2824 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F3, F10_ONLINE_SPARE, &pvt->online_spare);
pvt              2826 drivers/edac/amd64_edac.c 	amd64_read_dct_pci_cfg(pvt, 0, DCLR0, &pvt->dclr0);
pvt              2827 drivers/edac/amd64_edac.c 	amd64_read_dct_pci_cfg(pvt, 0, DCHR0, &pvt->dchr0);
pvt              2829 drivers/edac/amd64_edac.c 	if (!dct_ganging_enabled(pvt)) {
pvt              2830 drivers/edac/amd64_edac.c 		amd64_read_dct_pci_cfg(pvt, 1, DCLR0, &pvt->dclr1);
pvt              2831 drivers/edac/amd64_edac.c 		amd64_read_dct_pci_cfg(pvt, 1, DCHR0, &pvt->dchr1);
pvt              2835 drivers/edac/amd64_edac.c 	read_dct_base_mask(pvt);
pvt              2837 drivers/edac/amd64_edac.c 	determine_memory_type(pvt);
pvt              2838 drivers/edac/amd64_edac.c 	edac_dbg(1, "  DIMM type: %s\n", edac_mem_types[pvt->dram_type]);
pvt              2840 drivers/edac/amd64_edac.c 	determine_ecc_sym_sz(pvt);
pvt              2842 drivers/edac/amd64_edac.c 	dump_misc_regs(pvt);
pvt              2879 drivers/edac/amd64_edac.c static u32 get_csrow_nr_pages(struct amd64_pvt *pvt, u8 dct, int csrow_nr_orig)
pvt              2881 drivers/edac/amd64_edac.c 	u32 dbam = dct ? pvt->dbam1 : pvt->dbam0;
pvt              2885 drivers/edac/amd64_edac.c 	if (!pvt->umc) {
pvt              2889 drivers/edac/amd64_edac.c 		cs_mode = f17_get_cs_mode(csrow_nr >> 1, dct, pvt);
pvt              2892 drivers/edac/amd64_edac.c 	nr_pages   = pvt->ops->dbam_to_cs(pvt, dct, cs_mode, csrow_nr);
pvt              2904 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt              2925 drivers/edac/amd64_edac.c 		for_each_chip_select(cs, umc, pvt) {
pvt              2926 drivers/edac/amd64_edac.c 			if (!csrow_enabled(cs, umc, pvt))
pvt              2933 drivers/edac/amd64_edac.c 					pvt->mc_node_id, cs);
pvt              2935 drivers/edac/amd64_edac.c 			dimm->nr_pages = get_csrow_nr_pages(pvt, umc, cs);
pvt              2936 drivers/edac/amd64_edac.c 			dimm->mtype = pvt->dram_type;
pvt              2952 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt              2960 drivers/edac/amd64_edac.c 	if (pvt->umc)
pvt              2963 drivers/edac/amd64_edac.c 	amd64_read_pci_cfg(pvt->F3, NBCFG, &val);
pvt              2965 drivers/edac/amd64_edac.c 	pvt->nbcfg = val;
pvt              2968 drivers/edac/amd64_edac.c 		 pvt->mc_node_id, val,
pvt              2974 drivers/edac/amd64_edac.c 	for_each_chip_select(i, 0, pvt) {
pvt              2975 drivers/edac/amd64_edac.c 		bool row_dct0 = !!csrow_enabled(i, 0, pvt);
pvt              2978 drivers/edac/amd64_edac.c 		if (pvt->fam != 0xf)
pvt              2979 drivers/edac/amd64_edac.c 			row_dct1 = !!csrow_enabled(i, 1, pvt);
pvt              2988 drivers/edac/amd64_edac.c 			    pvt->mc_node_id, i);
pvt              2991 drivers/edac/amd64_edac.c 			nr_pages = get_csrow_nr_pages(pvt, 0, i);
pvt              2996 drivers/edac/amd64_edac.c 		if (pvt->fam != 0xf && row_dct1) {
pvt              2997 drivers/edac/amd64_edac.c 			int row_dct1_pages = get_csrow_nr_pages(pvt, 1, i);
pvt              3006 drivers/edac/amd64_edac.c 		if (pvt->nbcfg & NBCFG_ECC_ENABLE) {
pvt              3007 drivers/edac/amd64_edac.c 			edac_mode = (pvt->nbcfg & NBCFG_CHIPKILL)
pvt              3012 drivers/edac/amd64_edac.c 		for (j = 0; j < pvt->channel_count; j++) {
pvt              3014 drivers/edac/amd64_edac.c 			dimm->mtype = pvt->dram_type;
pvt              3253 drivers/edac/amd64_edac.c f17h_determine_edac_ctl_cap(struct mem_ctl_info *mci, struct amd64_pvt *pvt)
pvt              3258 drivers/edac/amd64_edac.c 		if (pvt->umc[i].sdp_ctrl & UMC_SDP_INIT) {
pvt              3259 drivers/edac/amd64_edac.c 			ecc_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_ENABLED);
pvt              3260 drivers/edac/amd64_edac.c 			cpk_en &= !!(pvt->umc[i].umc_cap_hi & UMC_ECC_CHIPKILL_CAP);
pvt              3262 drivers/edac/amd64_edac.c 			dev_x4  &= !!(pvt->umc[i].dimm_cfg & BIT(6));
pvt              3263 drivers/edac/amd64_edac.c 			dev_x16 &= !!(pvt->umc[i].dimm_cfg & BIT(7));
pvt              3286 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt              3291 drivers/edac/amd64_edac.c 	if (pvt->umc) {
pvt              3292 drivers/edac/amd64_edac.c 		f17h_determine_edac_ctl_cap(mci, pvt);
pvt              3294 drivers/edac/amd64_edac.c 		if (pvt->nbcap & NBCAP_SECDED)
pvt              3297 drivers/edac/amd64_edac.c 		if (pvt->nbcap & NBCAP_CHIPKILL)
pvt              3301 drivers/edac/amd64_edac.c 	mci->edac_cap		= determine_edac_cap(pvt);
pvt              3304 drivers/edac/amd64_edac.c 	mci->dev_name		= pci_name(pvt->F3);
pvt              3315 drivers/edac/amd64_edac.c static struct amd64_family_type *per_family_init(struct amd64_pvt *pvt)
pvt              3319 drivers/edac/amd64_edac.c 	pvt->ext_model  = boot_cpu_data.x86_model >> 4;
pvt              3320 drivers/edac/amd64_edac.c 	pvt->stepping	= boot_cpu_data.x86_stepping;
pvt              3321 drivers/edac/amd64_edac.c 	pvt->model	= boot_cpu_data.x86_model;
pvt              3322 drivers/edac/amd64_edac.c 	pvt->fam	= boot_cpu_data.x86;
pvt              3324 drivers/edac/amd64_edac.c 	switch (pvt->fam) {
pvt              3327 drivers/edac/amd64_edac.c 		pvt->ops	= &family_types[K8_CPUS].ops;
pvt              3332 drivers/edac/amd64_edac.c 		pvt->ops	= &family_types[F10_CPUS].ops;
pvt              3336 drivers/edac/amd64_edac.c 		if (pvt->model == 0x30) {
pvt              3338 drivers/edac/amd64_edac.c 			pvt->ops = &family_types[F15_M30H_CPUS].ops;
pvt              3340 drivers/edac/amd64_edac.c 		} else if (pvt->model == 0x60) {
pvt              3342 drivers/edac/amd64_edac.c 			pvt->ops = &family_types[F15_M60H_CPUS].ops;
pvt              3347 drivers/edac/amd64_edac.c 		pvt->ops	= &family_types[F15_CPUS].ops;
pvt              3351 drivers/edac/amd64_edac.c 		if (pvt->model == 0x30) {
pvt              3353 drivers/edac/amd64_edac.c 			pvt->ops = &family_types[F16_M30H_CPUS].ops;
pvt              3357 drivers/edac/amd64_edac.c 		pvt->ops	= &family_types[F16_CPUS].ops;
pvt              3361 drivers/edac/amd64_edac.c 		if (pvt->model >= 0x10 && pvt->model <= 0x2f) {
pvt              3363 drivers/edac/amd64_edac.c 			pvt->ops = &family_types[F17_M10H_CPUS].ops;
pvt              3365 drivers/edac/amd64_edac.c 		} else if (pvt->model >= 0x30 && pvt->model <= 0x3f) {
pvt              3367 drivers/edac/amd64_edac.c 			pvt->ops = &family_types[F17_M30H_CPUS].ops;
pvt              3369 drivers/edac/amd64_edac.c 		} else if (pvt->model >= 0x70 && pvt->model <= 0x7f) {
pvt              3371 drivers/edac/amd64_edac.c 			pvt->ops = &family_types[F17_M70H_CPUS].ops;
pvt              3377 drivers/edac/amd64_edac.c 		pvt->ops	= &family_types[F17_CPUS].ops;
pvt              3379 drivers/edac/amd64_edac.c 		if (pvt->fam == 0x18)
pvt              3389 drivers/edac/amd64_edac.c 		     (pvt->fam == 0xf ?
pvt              3390 drivers/edac/amd64_edac.c 				(pvt->ext_model >= K8_REV_F  ? "revF or later "
pvt              3392 drivers/edac/amd64_edac.c 				 : ""), pvt->mc_node_id);
pvt              3428 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt = NULL;
pvt              3433 drivers/edac/amd64_edac.c 	pvt = kzalloc(sizeof(struct amd64_pvt), GFP_KERNEL);
pvt              3434 drivers/edac/amd64_edac.c 	if (!pvt)
pvt              3437 drivers/edac/amd64_edac.c 	pvt->mc_node_id	= nid;
pvt              3438 drivers/edac/amd64_edac.c 	pvt->F3 = F3;
pvt              3441 drivers/edac/amd64_edac.c 	fam_type = per_family_init(pvt);
pvt              3445 drivers/edac/amd64_edac.c 	if (pvt->fam >= 0x17) {
pvt              3446 drivers/edac/amd64_edac.c 		pvt->umc = kcalloc(num_umcs, sizeof(struct amd64_umc), GFP_KERNEL);
pvt              3447 drivers/edac/amd64_edac.c 		if (!pvt->umc) {
pvt              3459 drivers/edac/amd64_edac.c 	err = reserve_mc_sibling_devs(pvt, pci_id1, pci_id2);
pvt              3463 drivers/edac/amd64_edac.c 	read_mc_regs(pvt);
pvt              3471 drivers/edac/amd64_edac.c 	pvt->channel_count = pvt->ops->early_channel_count(pvt);
pvt              3472 drivers/edac/amd64_edac.c 	if (pvt->channel_count < 0)
pvt              3477 drivers/edac/amd64_edac.c 	layers[0].size = pvt->csels[0].b_cnt;
pvt              3489 drivers/edac/amd64_edac.c 	if (pvt->fam >= 0x17)
pvt              3499 drivers/edac/amd64_edac.c 	mci->pvt_info = pvt;
pvt              3500 drivers/edac/amd64_edac.c 	mci->pdev = &pvt->F3->dev;
pvt              3519 drivers/edac/amd64_edac.c 	free_mc_sibling_devs(pvt);
pvt              3522 drivers/edac/amd64_edac.c 	if (pvt->fam >= 0x17)
pvt              3523 drivers/edac/amd64_edac.c 		kfree(pvt->umc);
pvt              3526 drivers/edac/amd64_edac.c 	kfree(pvt);
pvt              3586 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt;
pvt              3596 drivers/edac/amd64_edac.c 	pvt = mci->pvt_info;
pvt              3600 drivers/edac/amd64_edac.c 	free_mc_sibling_devs(pvt);
pvt              3608 drivers/edac/amd64_edac.c 	kfree(pvt);
pvt              3615 drivers/edac/amd64_edac.c 	struct amd64_pvt *pvt;
pvt              3624 drivers/edac/amd64_edac.c 	pvt = mci->pvt_info;
pvt              3625 drivers/edac/amd64_edac.c 	if (pvt->umc)
pvt              3626 drivers/edac/amd64_edac.c 		pci_ctl = edac_pci_create_generic_ctl(&pvt->F0->dev, EDAC_MOD_STR);
pvt              3628 drivers/edac/amd64_edac.c 		pci_ctl = edac_pci_create_generic_ctl(&pvt->F2->dev, EDAC_MOD_STR);
pvt               143 drivers/edac/amd64_edac.h #define dram_rw(pvt, i)			((u8)(pvt->ranges[i].base.lo & 0x3))
pvt               144 drivers/edac/amd64_edac.h #define dram_intlv_sel(pvt, i)		((u8)((pvt->ranges[i].lim.lo >> 8) & 0x7))
pvt               145 drivers/edac/amd64_edac.h #define dram_dst_node(pvt, i)		((u8)(pvt->ranges[i].lim.lo & 0x7))
pvt               148 drivers/edac/amd64_edac.h #define dhar_mem_hoist_valid(pvt)	((pvt)->dhar & BIT(1))
pvt               149 drivers/edac/amd64_edac.h #define dhar_base(pvt)			((pvt)->dhar & 0xff000000)
pvt               150 drivers/edac/amd64_edac.h #define k8_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff00) << 16)
pvt               153 drivers/edac/amd64_edac.h #define f10_dhar_offset(pvt)		(((pvt)->dhar & 0x0000ff80) << 16)
pvt               174 drivers/edac/amd64_edac.h #define csrow_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases[(i)]     & DCSB_CS_ENABLE)
pvt               175 drivers/edac/amd64_edac.h #define csrow_sec_enabled(i, dct, pvt)	((pvt)->csels[(dct)].csbases_sec[(i)] & DCSB_CS_ENABLE)
pvt               197 drivers/edac/amd64_edac.h #define dct_high_range_enabled(pvt)	((pvt)->dct_sel_lo & BIT(0))
pvt               198 drivers/edac/amd64_edac.h #define dct_interleave_enabled(pvt)	((pvt)->dct_sel_lo & BIT(2))
pvt               200 drivers/edac/amd64_edac.h #define dct_ganging_enabled(pvt)	((boot_cpu_data.x86 == 0x10) && ((pvt)->dct_sel_lo & BIT(4)))
pvt               202 drivers/edac/amd64_edac.h #define dct_data_intlv_enabled(pvt)	((pvt)->dct_sel_lo & BIT(5))
pvt               203 drivers/edac/amd64_edac.h #define dct_memory_cleared(pvt)		((pvt)->dct_sel_lo & BIT(10))
pvt               229 drivers/edac/amd64_edac.h #define online_spare_swap_done(pvt, c)	(((pvt)->online_spare >> (1 + 2 * (c))) & 0x1)
pvt               230 drivers/edac/amd64_edac.h #define online_spare_bad_dramcs(pvt, c)	(((pvt)->online_spare >> (4 + 4 * (c))) & 0x7)
pvt               413 drivers/edac/amd64_edac.h static inline u64 get_dram_base(struct amd64_pvt *pvt, u8 i)
pvt               415 drivers/edac/amd64_edac.h 	u64 addr = ((u64)pvt->ranges[i].base.lo & 0xffff0000) << 8;
pvt               420 drivers/edac/amd64_edac.h 	return (((u64)pvt->ranges[i].base.hi & 0x000000ff) << 40) | addr;
pvt               423 drivers/edac/amd64_edac.h static inline u64 get_dram_limit(struct amd64_pvt *pvt, u8 i)
pvt               425 drivers/edac/amd64_edac.h 	u64 lim = (((u64)pvt->ranges[i].lim.lo & 0xffff0000) << 8) | 0x00ffffff;
pvt               430 drivers/edac/amd64_edac.h 	return (((u64)pvt->ranges[i].lim.hi & 0x000000ff) << 40) | lim;
pvt               438 drivers/edac/amd64_edac.h static inline u8 dct_sel_interleave_addr(struct amd64_pvt *pvt)
pvt               440 drivers/edac/amd64_edac.h 	if (pvt->fam == 0x15 && pvt->model >= 0x30)
pvt               441 drivers/edac/amd64_edac.h 		return (((pvt->dct_sel_hi >> 9) & 0x1) << 2) |
pvt               442 drivers/edac/amd64_edac.h 			((pvt->dct_sel_lo >> 6) & 0x3);
pvt               444 drivers/edac/amd64_edac.h 	return	((pvt)->dct_sel_lo >> 6) & 0x3;
pvt               472 drivers/edac/amd64_edac.h 	int (*early_channel_count)	(struct amd64_pvt *pvt);
pvt               475 drivers/edac/amd64_edac.h 	int (*dbam_to_cs)		(struct amd64_pvt *pvt, u8 dct,
pvt               513 drivers/edac/amd64_edac.h static inline u8 dram_intlv_en(struct amd64_pvt *pvt, unsigned int i)
pvt               515 drivers/edac/amd64_edac.h 	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
pvt               517 drivers/edac/amd64_edac.h 		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_LIMIT, &tmp);
pvt               520 drivers/edac/amd64_edac.h 	return (u8) (pvt->ranges[i].base.lo >> 8) & 0x7;
pvt               523 drivers/edac/amd64_edac.h static inline u8 dhar_valid(struct amd64_pvt *pvt)
pvt               525 drivers/edac/amd64_edac.h 	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
pvt               527 drivers/edac/amd64_edac.h 		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
pvt               530 drivers/edac/amd64_edac.h 	return (pvt)->dhar & BIT(0);
pvt               533 drivers/edac/amd64_edac.h static inline u32 dct_sel_baseaddr(struct amd64_pvt *pvt)
pvt               535 drivers/edac/amd64_edac.h 	if (pvt->fam == 0x15 && pvt->model >= 0x30) {
pvt               537 drivers/edac/amd64_edac.h 		amd64_read_pci_cfg(pvt->F1, DRAM_CONT_BASE, &tmp);
pvt               540 drivers/edac/amd64_edac.h 	return (pvt)->dct_sel_lo & 0xFFFFF800;
pvt                10 drivers/edac/amd64_edac_dbg.c 	struct amd64_pvt *pvt = mci->pvt_info;				\
pvt                11 drivers/edac/amd64_edac_dbg.c 		return sprintf(data, "0x%016llx\n", (u64)pvt->reg);	\
pvt                 9 drivers/edac/amd64_edac_inj.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt                10 drivers/edac/amd64_edac_inj.c 	return sprintf(buf, "0x%x\n", pvt->injection.section);
pvt                24 drivers/edac/amd64_edac_inj.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt                37 drivers/edac/amd64_edac_inj.c 	pvt->injection.section = (u32) value;
pvt                46 drivers/edac/amd64_edac_inj.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt                47 drivers/edac/amd64_edac_inj.c 	return sprintf(buf, "0x%x\n", pvt->injection.word);
pvt                61 drivers/edac/amd64_edac_inj.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt                74 drivers/edac/amd64_edac_inj.c 	pvt->injection.word = (u32) value;
pvt                83 drivers/edac/amd64_edac_inj.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt                84 drivers/edac/amd64_edac_inj.c 	return sprintf(buf, "0x%x\n", pvt->injection.bit_map);
pvt                97 drivers/edac/amd64_edac_inj.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt               110 drivers/edac/amd64_edac_inj.c 	pvt->injection.bit_map = (u32) value;
pvt               123 drivers/edac/amd64_edac_inj.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt               133 drivers/edac/amd64_edac_inj.c 	section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
pvt               135 drivers/edac/amd64_edac_inj.c 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
pvt               137 drivers/edac/amd64_edac_inj.c 	word_bits = SET_NB_DRAM_INJECTION_READ(pvt->injection);
pvt               140 drivers/edac/amd64_edac_inj.c 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
pvt               156 drivers/edac/amd64_edac_inj.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt               166 drivers/edac/amd64_edac_inj.c 	section = F10_NB_ARRAY_DRAM | SET_NB_ARRAY_ADDR(pvt->injection.section);
pvt               168 drivers/edac/amd64_edac_inj.c 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_ADDR, section);
pvt               170 drivers/edac/amd64_edac_inj.c 	word_bits = SET_NB_DRAM_INJECTION_WRITE(pvt->injection);
pvt               179 drivers/edac/amd64_edac_inj.c 	amd64_write_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, word_bits);
pvt               183 drivers/edac/amd64_edac_inj.c 	amd64_read_pci_cfg(pvt->F3, F10_NB_ARRAY_DATA, &tmp);
pvt               225 drivers/edac/amd64_edac_inj.c 	struct amd64_pvt *pvt = mci->pvt_info;
pvt               227 drivers/edac/amd64_edac_inj.c 	if (pvt->fam < 0x10)
pvt               308 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
pvt               312 drivers/edac/e752x_edac.c 	if (page < pvt->tolm)
pvt               315 drivers/edac/e752x_edac.c 	if ((page >= 0x100000) && (page < pvt->remapbase))
pvt               318 drivers/edac/e752x_edac.c 	remap = (page - pvt->tolm) + pvt->remapbase;
pvt               320 drivers/edac/e752x_edac.c 	if (remap < pvt->remaplimit)
pvt               324 drivers/edac/e752x_edac.c 	return pvt->tolm - 1;
pvt               334 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
pvt               342 drivers/edac/e752x_edac.c 	if (pvt->mc_symmetric) {
pvt               347 drivers/edac/e752x_edac.c 			pvt->map[0], pvt->map[1], pvt->map[2], pvt->map[3],
pvt               348 drivers/edac/e752x_edac.c 			pvt->map[4], pvt->map[5], pvt->map[6],
pvt               349 drivers/edac/e752x_edac.c 			pvt->map[7]);
pvt               353 drivers/edac/e752x_edac.c 			if (pvt->map[i] == row)
pvt               393 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
pvt               403 drivers/edac/e752x_edac.c 		row = pvt->mc_symmetric ?
pvt               422 drivers/edac/e752x_edac.c 		row = pvt->mc_symmetric ?
pvt               465 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt = (struct e752x_pvt *)mci->pvt_info;
pvt               471 drivers/edac/e752x_edac.c 	row = pvt->mc_symmetric ? ((page >> 1) & 3) :
pvt               842 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt;
pvt               845 drivers/edac/e752x_edac.c 	pvt = (struct e752x_pvt *)mci->pvt_info;
pvt               846 drivers/edac/e752x_edac.c 	dev = pvt->dev_d0f1;
pvt               850 drivers/edac/e752x_edac.c 		if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
pvt               892 drivers/edac/e752x_edac.c 			pci_write_bits16(pvt->dev_d0f1, E752X_DRAM_FERR,
pvt               902 drivers/edac/e752x_edac.c 		if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
pvt               937 drivers/edac/e752x_edac.c 			pci_write_bits16(pvt->dev_d0f1, E752X_DRAM_NERR,
pvt               992 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
pvt               993 drivers/edac/e752x_edac.c 	struct pci_dev *pdev = pvt->dev_d0f0;
pvt               996 drivers/edac/e752x_edac.c 	if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0)
pvt              1021 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt = (struct e752x_pvt *) mci->pvt_info;
pvt              1022 drivers/edac/e752x_edac.c 	struct pci_dev *pdev = pvt->dev_d0f0;
pvt              1026 drivers/edac/e752x_edac.c 	if (pvt->dev_info->ctl_dev == PCI_DEVICE_ID_INTEL_3100_0)
pvt              1058 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt = mci->pvt_info;
pvt              1060 drivers/edac/e752x_edac.c 	if (!pvt->map_type)
pvt              1140 drivers/edac/e752x_edac.c 				struct e752x_pvt *pvt)
pvt              1153 drivers/edac/e752x_edac.c 			pvt->map[index] = 0xff;
pvt              1154 drivers/edac/e752x_edac.c 			pvt->map[index + 1] = 0xff;
pvt              1156 drivers/edac/e752x_edac.c 			pvt->map[index] = row;
pvt              1167 drivers/edac/e752x_edac.c 			pvt->map[index + 1] = (value == last) ? 0xff :	row;
pvt              1176 drivers/edac/e752x_edac.c 			struct e752x_pvt *pvt)
pvt              1178 drivers/edac/e752x_edac.c 	pvt->dev_d0f1 = pci_get_device(PCI_VENDOR_ID_INTEL,
pvt              1179 drivers/edac/e752x_edac.c 				pvt->dev_info->err_dev, NULL);
pvt              1181 drivers/edac/e752x_edac.c 	if (pvt->dev_d0f1 == NULL) {
pvt              1182 drivers/edac/e752x_edac.c 		pvt->dev_d0f1 = pci_scan_single_device(pdev->bus,
pvt              1184 drivers/edac/e752x_edac.c 		pci_dev_get(pvt->dev_d0f1);
pvt              1187 drivers/edac/e752x_edac.c 	if (pvt->dev_d0f1 == NULL) {
pvt              1194 drivers/edac/e752x_edac.c 	pvt->dev_d0f0 = pci_get_device(PCI_VENDOR_ID_INTEL,
pvt              1198 drivers/edac/e752x_edac.c 	if (pvt->dev_d0f0 == NULL)
pvt              1204 drivers/edac/e752x_edac.c 	pci_dev_put(pvt->dev_d0f1);
pvt              1212 drivers/edac/e752x_edac.c static void e752x_init_sysbus_parity_mask(struct e752x_pvt *pvt)
pvt              1215 drivers/edac/e752x_edac.c 	struct pci_dev *dev = pvt->dev_d0f1;
pvt              1233 drivers/edac/e752x_edac.c static void e752x_init_error_reporting_regs(struct e752x_pvt *pvt)
pvt              1237 drivers/edac/e752x_edac.c 	dev = pvt->dev_d0f1;
pvt              1239 drivers/edac/e752x_edac.c 	if (pvt->dev_info->err_dev == PCI_DEVICE_ID_INTEL_3100_1_ERR) {
pvt              1247 drivers/edac/e752x_edac.c 	e752x_init_sysbus_parity_mask(pvt);
pvt              1262 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt;
pvt              1294 drivers/edac/e752x_edac.c 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
pvt              1308 drivers/edac/e752x_edac.c 	pvt = (struct e752x_pvt *)mci->pvt_info;
pvt              1309 drivers/edac/e752x_edac.c 	pvt->dev_info = &e752x_devs[dev_idx];
pvt              1310 drivers/edac/e752x_edac.c 	pvt->mc_symmetric = ((ddrcsr & 0x10) != 0);
pvt              1312 drivers/edac/e752x_edac.c 	if (e752x_get_devs(pdev, dev_idx, pvt)) {
pvt              1318 drivers/edac/e752x_edac.c 	mci->ctl_name = pvt->dev_info->ctl_name;
pvt              1330 drivers/edac/e752x_edac.c 	pvt->map_type = ((stat8 & 0x0f) > ((stat8 >> 4) & 0x0f));
pvt              1333 drivers/edac/e752x_edac.c 	e752x_init_mem_map_table(pdev, pvt);
pvt              1343 drivers/edac/e752x_edac.c 	pvt->tolm = ((u32) pci_data) << 4;
pvt              1345 drivers/edac/e752x_edac.c 	pvt->remapbase = ((u32) pci_data) << 14;
pvt              1347 drivers/edac/e752x_edac.c 	pvt->remaplimit = ((u32) pci_data) << 14;
pvt              1350 drivers/edac/e752x_edac.c 			pvt->tolm, pvt->remapbase, pvt->remaplimit);
pvt              1360 drivers/edac/e752x_edac.c 	e752x_init_error_reporting_regs(pvt);
pvt              1378 drivers/edac/e752x_edac.c 	pci_dev_put(pvt->dev_d0f0);
pvt              1379 drivers/edac/e752x_edac.c 	pci_dev_put(pvt->dev_d0f1);
pvt              1400 drivers/edac/e752x_edac.c 	struct e752x_pvt *pvt;
pvt              1410 drivers/edac/e752x_edac.c 	pvt = (struct e752x_pvt *)mci->pvt_info;
pvt              1411 drivers/edac/e752x_edac.c 	pci_dev_put(pvt->dev_d0f0);
pvt              1412 drivers/edac/e752x_edac.c 	pci_dev_put(pvt->dev_d0f1);
pvt               186 drivers/edac/e7xxx_edac.c 	struct e7xxx_pvt *pvt = (struct e7xxx_pvt *)mci->pvt_info;
pvt               190 drivers/edac/e7xxx_edac.c 	if ((page < pvt->tolm) ||
pvt               191 drivers/edac/e7xxx_edac.c 		((page >= 0x100000) && (page < pvt->remapbase)))
pvt               194 drivers/edac/e7xxx_edac.c 	remap = (page - pvt->tolm) + pvt->remapbase;
pvt               196 drivers/edac/e7xxx_edac.c 	if (remap < pvt->remaplimit)
pvt               200 drivers/edac/e7xxx_edac.c 	return pvt->tolm - 1;
pvt               259 drivers/edac/e7xxx_edac.c 	struct e7xxx_pvt *pvt;
pvt               261 drivers/edac/e7xxx_edac.c 	pvt = (struct e7xxx_pvt *)mci->pvt_info;
pvt               262 drivers/edac/e7xxx_edac.c 	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_FERR, &info->dram_ferr);
pvt               263 drivers/edac/e7xxx_edac.c 	pci_read_config_byte(pvt->bridge_ck, E7XXX_DRAM_NERR, &info->dram_nerr);
pvt               266 drivers/edac/e7xxx_edac.c 		pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_CELOG_ADD,
pvt               268 drivers/edac/e7xxx_edac.c 		pci_read_config_word(pvt->bridge_ck,
pvt               274 drivers/edac/e7xxx_edac.c 		pci_read_config_dword(pvt->bridge_ck, E7XXX_DRAM_UELOG_ADD,
pvt               278 drivers/edac/e7xxx_edac.c 		pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_FERR, 0x03, 0x03);
pvt               281 drivers/edac/e7xxx_edac.c 		pci_write_bits8(pvt->bridge_ck, E7XXX_DRAM_NERR, 0x03, 0x03);
pvt               426 drivers/edac/e7xxx_edac.c 	struct e7xxx_pvt *pvt = NULL;
pvt               450 drivers/edac/e7xxx_edac.c 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
pvt               462 drivers/edac/e7xxx_edac.c 	pvt = (struct e7xxx_pvt *)mci->pvt_info;
pvt               463 drivers/edac/e7xxx_edac.c 	pvt->dev_info = &e7xxx_devs[dev_idx];
pvt               464 drivers/edac/e7xxx_edac.c 	pvt->bridge_ck = pci_get_device(PCI_VENDOR_ID_INTEL,
pvt               465 drivers/edac/e7xxx_edac.c 					pvt->dev_info->err_dev, pvt->bridge_ck);
pvt               467 drivers/edac/e7xxx_edac.c 	if (!pvt->bridge_ck) {
pvt               475 drivers/edac/e7xxx_edac.c 	mci->ctl_name = pvt->dev_info->ctl_name;
pvt               484 drivers/edac/e7xxx_edac.c 	pvt->tolm = ((u32) pci_data) << 4;
pvt               486 drivers/edac/e7xxx_edac.c 	pvt->remapbase = ((u32) pci_data) << 14;
pvt               488 drivers/edac/e7xxx_edac.c 	pvt->remaplimit = ((u32) pci_data) << 14;
pvt               490 drivers/edac/e7xxx_edac.c 		"tolm = %x, remapbase = %x, remaplimit = %x\n", pvt->tolm,
pvt               491 drivers/edac/e7xxx_edac.c 		pvt->remapbase, pvt->remaplimit);
pvt               520 drivers/edac/e7xxx_edac.c 	pci_dev_put(pvt->bridge_ck);
pvt               541 drivers/edac/e7xxx_edac.c 	struct e7xxx_pvt *pvt;
pvt               551 drivers/edac/e7xxx_edac.c 	pvt = (struct e7xxx_pvt *)mci->pvt_info;
pvt               552 drivers/edac/e7xxx_edac.c 	pci_dev_put(pvt->bridge_ck);
pvt                65 drivers/edac/edac_device.c 	void *pvt, *p;
pvt               100 drivers/edac/edac_device.c 	pvt = edac_align_ptr(&p, sz_private, 1);
pvt               106 drivers/edac/edac_device.c 	total_size = ((unsigned long)pvt) + sz_private;
pvt               126 drivers/edac/edac_device.c 	pvt = sz_private ? (((char *)dev_ctl) + ((unsigned long)pvt)) : NULL;
pvt               132 drivers/edac/edac_device.c 	dev_ctl->pvt_info = pvt;
pvt               142 drivers/edac/edac_device.c 		 dev_ctl, pvt + sz_private);
pvt               319 drivers/edac/edac_mc.c 	void *pvt, *p, *ptr = NULL;
pvt               355 drivers/edac/edac_mc.c 	pvt = edac_align_ptr(&ptr, sz_pvt, 1);
pvt               356 drivers/edac/edac_mc.c 	size = ((unsigned long)pvt) + sz_pvt;
pvt               376 drivers/edac/edac_mc.c 	pvt = sz_pvt ? (((char *)mci) + ((unsigned long)pvt)) : NULL;
pvt               381 drivers/edac/edac_mc.c 	mci->pvt_info = pvt;
pvt                35 drivers/edac/edac_pci.c 	void *p = NULL, *pvt;
pvt                41 drivers/edac/edac_pci.c 	pvt = edac_align_ptr(&p, 1, sz_pvt);
pvt                42 drivers/edac/edac_pci.c 	size = ((unsigned long)pvt) + sz_pvt;
pvt                50 drivers/edac/edac_pci.c 	pvt = sz_pvt ? ((char *)pci) + ((unsigned long)pvt) : NULL;
pvt                52 drivers/edac/edac_pci.c 	pci->pvt_info = pvt;
pvt               209 drivers/edac/ghes_edac.c 	struct ghes_edac_pvt *pvt;
pvt               224 drivers/edac/ghes_edac.c 	pvt = ghes_pvt;
pvt               225 drivers/edac/ghes_edac.c 	if (!pvt)
pvt               228 drivers/edac/ghes_edac.c 	mci = pvt->mci;
pvt               236 drivers/edac/ghes_edac.c 	e->msg = pvt->msg;
pvt               237 drivers/edac/ghes_edac.c 	e->other_detail = pvt->other_detail;
pvt               241 drivers/edac/ghes_edac.c 	*pvt->other_detail = '\0';
pvt               242 drivers/edac/ghes_edac.c 	*pvt->msg = '\0';
pvt               264 drivers/edac/ghes_edac.c 		p = pvt->msg;
pvt               319 drivers/edac/ghes_edac.c 		strcpy(pvt->msg, "unknown error");
pvt               372 drivers/edac/ghes_edac.c 	p = pvt->other_detail;
pvt               443 drivers/edac/ghes_edac.c 	if (p > pvt->other_detail)
pvt               453 drivers/edac/ghes_edac.c 	snprintf(pvt->detail_location, sizeof(pvt->detail_location),
pvt               458 drivers/edac/ghes_edac.c 		       grain_bits, e->syndrome, pvt->detail_location);
pvt               479 drivers/edac/ghes_edac.c 	struct ghes_edac_pvt *pvt;
pvt               523 drivers/edac/ghes_edac.c 	pvt		= mci->pvt_info;
pvt               524 drivers/edac/ghes_edac.c 	pvt->ghes	= ghes;
pvt               525 drivers/edac/ghes_edac.c 	pvt->mci	= mci;
pvt               572 drivers/edac/ghes_edac.c 	ghes_pvt = pvt;
pvt               145 drivers/edac/i10nm_base.c 	struct skx_pvt *pvt = mci->pvt_info;
pvt               146 drivers/edac/i10nm_base.c 	struct skx_imc *imc = pvt->imc;
pvt               388 drivers/edac/i5000_edac.c 	struct i5000_pvt *pvt;
pvt               391 drivers/edac/i5000_edac.c 	pvt = mci->pvt_info;
pvt               394 drivers/edac/i5000_edac.c 	pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
pvt               406 drivers/edac/i5000_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               408 drivers/edac/i5000_edac.c 		pci_read_config_word(pvt->branchmap_werrors,
pvt               410 drivers/edac/i5000_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               414 drivers/edac/i5000_edac.c 		pci_write_config_dword(pvt->branchmap_werrors,
pvt               424 drivers/edac/i5000_edac.c 	pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
pvt               432 drivers/edac/i5000_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               434 drivers/edac/i5000_edac.c 		pci_read_config_word(pvt->branchmap_werrors,
pvt               436 drivers/edac/i5000_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               438 drivers/edac/i5000_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               442 drivers/edac/i5000_edac.c 		pci_write_config_dword(pvt->branchmap_werrors,
pvt               782 drivers/edac/i5000_edac.c 	struct i5000_pvt *pvt;
pvt               785 drivers/edac/i5000_edac.c 	pvt = mci->pvt_info;
pvt               811 drivers/edac/i5000_edac.c 	pvt->branchmap_werrors = pdev;
pvt               828 drivers/edac/i5000_edac.c 			pci_dev_put(pvt->branchmap_werrors);
pvt               837 drivers/edac/i5000_edac.c 	pvt->fsb_error_regs = pdev;
pvt               840 drivers/edac/i5000_edac.c 		 pci_name(pvt->system_address),
pvt               841 drivers/edac/i5000_edac.c 		 pvt->system_address->vendor, pvt->system_address->device);
pvt               843 drivers/edac/i5000_edac.c 		 pci_name(pvt->branchmap_werrors),
pvt               844 drivers/edac/i5000_edac.c 		 pvt->branchmap_werrors->vendor,
pvt               845 drivers/edac/i5000_edac.c 		 pvt->branchmap_werrors->device);
pvt               847 drivers/edac/i5000_edac.c 		 pci_name(pvt->fsb_error_regs),
pvt               848 drivers/edac/i5000_edac.c 		 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
pvt               860 drivers/edac/i5000_edac.c 		pci_dev_put(pvt->branchmap_werrors);
pvt               861 drivers/edac/i5000_edac.c 		pci_dev_put(pvt->fsb_error_regs);
pvt               865 drivers/edac/i5000_edac.c 	pvt->branch_0 = pdev;
pvt               870 drivers/edac/i5000_edac.c 	if (pvt->maxch >= CHANNELS_PER_BRANCH) {
pvt               883 drivers/edac/i5000_edac.c 			pci_dev_put(pvt->branchmap_werrors);
pvt               884 drivers/edac/i5000_edac.c 			pci_dev_put(pvt->fsb_error_regs);
pvt               885 drivers/edac/i5000_edac.c 			pci_dev_put(pvt->branch_0);
pvt               889 drivers/edac/i5000_edac.c 		pvt->branch_1 = pdev;
pvt               901 drivers/edac/i5000_edac.c 	struct i5000_pvt *pvt;
pvt               903 drivers/edac/i5000_edac.c 	pvt = mci->pvt_info;
pvt               905 drivers/edac/i5000_edac.c 	pci_dev_put(pvt->branchmap_werrors);	/* FUNC 1 */
pvt               906 drivers/edac/i5000_edac.c 	pci_dev_put(pvt->fsb_error_regs);	/* FUNC 2 */
pvt               907 drivers/edac/i5000_edac.c 	pci_dev_put(pvt->branch_0);	/* DEV 21 */
pvt               910 drivers/edac/i5000_edac.c 	if (pvt->maxch >= CHANNELS_PER_BRANCH)
pvt               911 drivers/edac/i5000_edac.c 		pci_dev_put(pvt->branch_1);	/* DEV 22 */
pvt               927 drivers/edac/i5000_edac.c static int determine_amb_present_reg(struct i5000_pvt *pvt, int channel)
pvt               933 drivers/edac/i5000_edac.c 			amb_present = pvt->b0_ambpresent1;
pvt               935 drivers/edac/i5000_edac.c 			amb_present = pvt->b0_ambpresent0;
pvt               938 drivers/edac/i5000_edac.c 			amb_present = pvt->b1_ambpresent1;
pvt               940 drivers/edac/i5000_edac.c 			amb_present = pvt->b1_ambpresent0;
pvt               951 drivers/edac/i5000_edac.c static int determine_mtr(struct i5000_pvt *pvt, int slot, int channel)
pvt               956 drivers/edac/i5000_edac.c 		mtr = pvt->b0_mtr[slot];
pvt               958 drivers/edac/i5000_edac.c 		mtr = pvt->b1_mtr[slot];
pvt               992 drivers/edac/i5000_edac.c static void handle_channel(struct i5000_pvt *pvt, int slot, int channel,
pvt               999 drivers/edac/i5000_edac.c 	mtr = determine_mtr(pvt, slot, channel);
pvt              1001 drivers/edac/i5000_edac.c 		amb_present_reg = determine_amb_present_reg(pvt, channel);
pvt              1034 drivers/edac/i5000_edac.c static void calculate_dimm_size(struct i5000_pvt *pvt)
pvt              1055 drivers/edac/i5000_edac.c 	for (slot = pvt->maxdimmperch - 1; slot >= 0; slot--) {
pvt              1072 drivers/edac/i5000_edac.c 		for (channel = 0; channel < pvt->maxch; channel++) {
pvt              1073 drivers/edac/i5000_edac.c 			dinfo = &pvt->dimm_info[slot][channel];
pvt              1074 drivers/edac/i5000_edac.c 			handle_channel(pvt, slot, channel, dinfo);
pvt              1103 drivers/edac/i5000_edac.c 	for (channel = 0; channel < pvt->maxch; channel++) {
pvt              1133 drivers/edac/i5000_edac.c 	struct i5000_pvt *pvt;
pvt              1139 drivers/edac/i5000_edac.c 	pvt = mci->pvt_info;
pvt              1141 drivers/edac/i5000_edac.c 	pci_read_config_dword(pvt->system_address, AMBASE,
pvt              1142 drivers/edac/i5000_edac.c 			&pvt->u.ambase_bottom);
pvt              1143 drivers/edac/i5000_edac.c 	pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
pvt              1144 drivers/edac/i5000_edac.c 			&pvt->u.ambase_top);
pvt              1147 drivers/edac/i5000_edac.c 		 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
pvt              1150 drivers/edac/i5000_edac.c 	pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
pvt              1151 drivers/edac/i5000_edac.c 	pvt->tolm >>= 12;
pvt              1153 drivers/edac/i5000_edac.c 		 pvt->tolm, pvt->tolm);
pvt              1155 drivers/edac/i5000_edac.c 	actual_tolm = pvt->tolm << 28;
pvt              1159 drivers/edac/i5000_edac.c 	pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
pvt              1160 drivers/edac/i5000_edac.c 	pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
pvt              1161 drivers/edac/i5000_edac.c 	pci_read_config_word(pvt->branchmap_werrors, MIR2, &pvt->mir2);
pvt              1164 drivers/edac/i5000_edac.c 	limit = (pvt->mir0 >> 4) & 0x0FFF;
pvt              1165 drivers/edac/i5000_edac.c 	way0 = pvt->mir0 & 0x1;
pvt              1166 drivers/edac/i5000_edac.c 	way1 = pvt->mir0 & 0x2;
pvt              1169 drivers/edac/i5000_edac.c 	limit = (pvt->mir1 >> 4) & 0x0FFF;
pvt              1170 drivers/edac/i5000_edac.c 	way0 = pvt->mir1 & 0x1;
pvt              1171 drivers/edac/i5000_edac.c 	way1 = pvt->mir1 & 0x2;
pvt              1174 drivers/edac/i5000_edac.c 	limit = (pvt->mir2 >> 4) & 0x0FFF;
pvt              1175 drivers/edac/i5000_edac.c 	way0 = pvt->mir2 & 0x1;
pvt              1176 drivers/edac/i5000_edac.c 	way1 = pvt->mir2 & 0x2;
pvt              1184 drivers/edac/i5000_edac.c 		pci_read_config_word(pvt->branch_0, where,
pvt              1185 drivers/edac/i5000_edac.c 				&pvt->b0_mtr[slot_row]);
pvt              1188 drivers/edac/i5000_edac.c 			 slot_row, where, pvt->b0_mtr[slot_row]);
pvt              1190 drivers/edac/i5000_edac.c 		if (pvt->maxch >= CHANNELS_PER_BRANCH) {
pvt              1191 drivers/edac/i5000_edac.c 			pci_read_config_word(pvt->branch_1, where,
pvt              1192 drivers/edac/i5000_edac.c 					&pvt->b1_mtr[slot_row]);
pvt              1194 drivers/edac/i5000_edac.c 				 slot_row, where, pvt->b1_mtr[slot_row]);
pvt              1196 drivers/edac/i5000_edac.c 			pvt->b1_mtr[slot_row] = 0;
pvt              1204 drivers/edac/i5000_edac.c 		decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
pvt              1206 drivers/edac/i5000_edac.c 	pci_read_config_word(pvt->branch_0, AMB_PRESENT_0,
pvt              1207 drivers/edac/i5000_edac.c 			&pvt->b0_ambpresent0);
pvt              1208 drivers/edac/i5000_edac.c 	edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
pvt              1209 drivers/edac/i5000_edac.c 	pci_read_config_word(pvt->branch_0, AMB_PRESENT_1,
pvt              1210 drivers/edac/i5000_edac.c 			&pvt->b0_ambpresent1);
pvt              1211 drivers/edac/i5000_edac.c 	edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
pvt              1214 drivers/edac/i5000_edac.c 	if (pvt->maxch < CHANNELS_PER_BRANCH) {
pvt              1215 drivers/edac/i5000_edac.c 		pvt->b1_ambpresent0 = 0;
pvt              1216 drivers/edac/i5000_edac.c 		pvt->b1_ambpresent1 = 0;
pvt              1221 drivers/edac/i5000_edac.c 			decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
pvt              1223 drivers/edac/i5000_edac.c 		pci_read_config_word(pvt->branch_1, AMB_PRESENT_0,
pvt              1224 drivers/edac/i5000_edac.c 				&pvt->b1_ambpresent0);
pvt              1226 drivers/edac/i5000_edac.c 			 pvt->b1_ambpresent0);
pvt              1227 drivers/edac/i5000_edac.c 		pci_read_config_word(pvt->branch_1, AMB_PRESENT_1,
pvt              1228 drivers/edac/i5000_edac.c 				&pvt->b1_ambpresent1);
pvt              1230 drivers/edac/i5000_edac.c 			 pvt->b1_ambpresent1);
pvt              1235 drivers/edac/i5000_edac.c 	calculate_dimm_size(pvt);
pvt              1249 drivers/edac/i5000_edac.c 	struct i5000_pvt *pvt;
pvt              1258 drivers/edac/i5000_edac.c 	pvt = mci->pvt_info;
pvt              1259 drivers/edac/i5000_edac.c 	max_csrows = pvt->maxdimmperch * 2;
pvt              1271 drivers/edac/i5000_edac.c 		for (channel = 0; channel < pvt->maxch; channel++) {
pvt              1273 drivers/edac/i5000_edac.c 			mtr = determine_mtr(pvt, slot, channel);
pvt              1282 drivers/edac/i5000_edac.c 			csrow_megs = pvt->dimm_info[slot][channel].megabytes;
pvt              1310 drivers/edac/i5000_edac.c 	struct i5000_pvt *pvt;
pvt              1313 drivers/edac/i5000_edac.c 	pvt = mci->pvt_info;
pvt              1316 drivers/edac/i5000_edac.c 	pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
pvt              1322 drivers/edac/i5000_edac.c 	pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
pvt              1359 drivers/edac/i5000_edac.c 	struct i5000_pvt *pvt;
pvt              1401 drivers/edac/i5000_edac.c 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
pvt              1409 drivers/edac/i5000_edac.c 	pvt = mci->pvt_info;
pvt              1410 drivers/edac/i5000_edac.c 	pvt->system_address = pdev;	/* Record this device in our private */
pvt              1411 drivers/edac/i5000_edac.c 	pvt->maxch = num_channels;
pvt              1412 drivers/edac/i5000_edac.c 	pvt->maxdimmperch = num_dimms_per_channel;
pvt               438 drivers/edac/i5400_edac.c 	struct i5400_pvt *pvt;
pvt               441 drivers/edac/i5400_edac.c 	pvt = mci->pvt_info;
pvt               444 drivers/edac/i5400_edac.c 	pci_read_config_dword(pvt->branchmap_werrors, FERR_FAT_FBD, &value);
pvt               457 drivers/edac/i5400_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               459 drivers/edac/i5400_edac.c 		pci_read_config_word(pvt->branchmap_werrors,
pvt               461 drivers/edac/i5400_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               465 drivers/edac/i5400_edac.c 		pci_write_config_dword(pvt->branchmap_werrors,
pvt               475 drivers/edac/i5400_edac.c 	pci_read_config_dword(pvt->branchmap_werrors, FERR_NF_FBD, &value);
pvt               483 drivers/edac/i5400_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               485 drivers/edac/i5400_edac.c 		pci_read_config_word(pvt->branchmap_werrors,
pvt               487 drivers/edac/i5400_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               489 drivers/edac/i5400_edac.c 		pci_read_config_dword(pvt->branchmap_werrors,
pvt               493 drivers/edac/i5400_edac.c 		pci_write_config_dword(pvt->branchmap_werrors,
pvt               700 drivers/edac/i5400_edac.c 	struct i5400_pvt *pvt;
pvt               702 drivers/edac/i5400_edac.c 	pvt = mci->pvt_info;
pvt               705 drivers/edac/i5400_edac.c 	pci_dev_put(pvt->branch_1);
pvt               706 drivers/edac/i5400_edac.c 	pci_dev_put(pvt->branch_0);
pvt               707 drivers/edac/i5400_edac.c 	pci_dev_put(pvt->fsb_error_regs);
pvt               708 drivers/edac/i5400_edac.c 	pci_dev_put(pvt->branchmap_werrors);
pvt               719 drivers/edac/i5400_edac.c 	struct i5400_pvt *pvt;
pvt               722 drivers/edac/i5400_edac.c 	pvt = mci->pvt_info;
pvt               723 drivers/edac/i5400_edac.c 	pvt->branchmap_werrors = NULL;
pvt               724 drivers/edac/i5400_edac.c 	pvt->fsb_error_regs = NULL;
pvt               725 drivers/edac/i5400_edac.c 	pvt->branch_0 = NULL;
pvt               726 drivers/edac/i5400_edac.c 	pvt->branch_1 = NULL;
pvt               749 drivers/edac/i5400_edac.c 	pvt->branchmap_werrors = pdev;
pvt               765 drivers/edac/i5400_edac.c 			pci_dev_put(pvt->branchmap_werrors);
pvt               773 drivers/edac/i5400_edac.c 	pvt->fsb_error_regs = pdev;
pvt               776 drivers/edac/i5400_edac.c 		 pci_name(pvt->system_address),
pvt               777 drivers/edac/i5400_edac.c 		 pvt->system_address->vendor, pvt->system_address->device);
pvt               779 drivers/edac/i5400_edac.c 		 pci_name(pvt->branchmap_werrors),
pvt               780 drivers/edac/i5400_edac.c 		 pvt->branchmap_werrors->vendor,
pvt               781 drivers/edac/i5400_edac.c 		 pvt->branchmap_werrors->device);
pvt               783 drivers/edac/i5400_edac.c 		 pci_name(pvt->fsb_error_regs),
pvt               784 drivers/edac/i5400_edac.c 		 pvt->fsb_error_regs->vendor, pvt->fsb_error_regs->device);
pvt               786 drivers/edac/i5400_edac.c 	pvt->branch_0 = pci_get_device(PCI_VENDOR_ID_INTEL,
pvt               788 drivers/edac/i5400_edac.c 	if (!pvt->branch_0) {
pvt               794 drivers/edac/i5400_edac.c 		pci_dev_put(pvt->fsb_error_regs);
pvt               795 drivers/edac/i5400_edac.c 		pci_dev_put(pvt->branchmap_werrors);
pvt               802 drivers/edac/i5400_edac.c 	if (pvt->maxch < CHANNELS_PER_BRANCH)
pvt               805 drivers/edac/i5400_edac.c 	pvt->branch_1 = pci_get_device(PCI_VENDOR_ID_INTEL,
pvt               807 drivers/edac/i5400_edac.c 	if (!pvt->branch_1) {
pvt               815 drivers/edac/i5400_edac.c 		pci_dev_put(pvt->branch_0);
pvt               816 drivers/edac/i5400_edac.c 		pci_dev_put(pvt->fsb_error_regs);
pvt               817 drivers/edac/i5400_edac.c 		pci_dev_put(pvt->branchmap_werrors);
pvt               837 drivers/edac/i5400_edac.c static int determine_amb_present_reg(struct i5400_pvt *pvt, int channel)
pvt               843 drivers/edac/i5400_edac.c 			amb_present = pvt->b0_ambpresent1;
pvt               845 drivers/edac/i5400_edac.c 			amb_present = pvt->b0_ambpresent0;
pvt               848 drivers/edac/i5400_edac.c 			amb_present = pvt->b1_ambpresent1;
pvt               850 drivers/edac/i5400_edac.c 			amb_present = pvt->b1_ambpresent0;
pvt               861 drivers/edac/i5400_edac.c static int determine_mtr(struct i5400_pvt *pvt, int dimm, int channel)
pvt               878 drivers/edac/i5400_edac.c 		mtr = pvt->b0_mtr[n];
pvt               880 drivers/edac/i5400_edac.c 		mtr = pvt->b1_mtr[n];
pvt               918 drivers/edac/i5400_edac.c static void handle_channel(struct i5400_pvt *pvt, int dimm, int channel,
pvt               925 drivers/edac/i5400_edac.c 	mtr = determine_mtr(pvt, dimm, channel);
pvt               927 drivers/edac/i5400_edac.c 		amb_present_reg = determine_amb_present_reg(pvt, channel);
pvt               956 drivers/edac/i5400_edac.c static void calculate_dimm_size(struct i5400_pvt *pvt)
pvt               978 drivers/edac/i5400_edac.c 	max_dimms = pvt->maxdimmperch;
pvt               996 drivers/edac/i5400_edac.c 		for (channel = 0; channel < pvt->maxch; channel++) {
pvt               997 drivers/edac/i5400_edac.c 			dinfo = &pvt->dimm_info[dimm][channel];
pvt               998 drivers/edac/i5400_edac.c 			handle_channel(pvt, dimm, channel, dinfo);
pvt              1021 drivers/edac/i5400_edac.c 	for (channel = 0; channel < pvt->maxch; channel++) {
pvt              1053 drivers/edac/i5400_edac.c 	struct i5400_pvt *pvt;
pvt              1061 drivers/edac/i5400_edac.c 	pvt = mci->pvt_info;
pvt              1063 drivers/edac/i5400_edac.c 	pci_read_config_dword(pvt->system_address, AMBASE,
pvt              1064 drivers/edac/i5400_edac.c 			&pvt->u.ambase_bottom);
pvt              1065 drivers/edac/i5400_edac.c 	pci_read_config_dword(pvt->system_address, AMBASE + sizeof(u32),
pvt              1066 drivers/edac/i5400_edac.c 			&pvt->u.ambase_top);
pvt              1068 drivers/edac/i5400_edac.c 	maxdimmperch = pvt->maxdimmperch;
pvt              1069 drivers/edac/i5400_edac.c 	maxch = pvt->maxch;
pvt              1072 drivers/edac/i5400_edac.c 		 (long unsigned int)pvt->ambase, pvt->maxch, pvt->maxdimmperch);
pvt              1075 drivers/edac/i5400_edac.c 	pci_read_config_word(pvt->branchmap_werrors, TOLM, &pvt->tolm);
pvt              1076 drivers/edac/i5400_edac.c 	pvt->tolm >>= 12;
pvt              1078 drivers/edac/i5400_edac.c 		 pvt->tolm, pvt->tolm);
pvt              1080 drivers/edac/i5400_edac.c 	actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
pvt              1082 drivers/edac/i5400_edac.c 		 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
pvt              1084 drivers/edac/i5400_edac.c 	pci_read_config_word(pvt->branchmap_werrors, MIR0, &pvt->mir0);
pvt              1085 drivers/edac/i5400_edac.c 	pci_read_config_word(pvt->branchmap_werrors, MIR1, &pvt->mir1);
pvt              1088 drivers/edac/i5400_edac.c 	limit = (pvt->mir0 >> 4) & 0x0fff;
pvt              1089 drivers/edac/i5400_edac.c 	way0 = pvt->mir0 & 0x1;
pvt              1090 drivers/edac/i5400_edac.c 	way1 = pvt->mir0 & 0x2;
pvt              1093 drivers/edac/i5400_edac.c 	limit = (pvt->mir1 >> 4) & 0xfff;
pvt              1094 drivers/edac/i5400_edac.c 	way0 = pvt->mir1 & 0x1;
pvt              1095 drivers/edac/i5400_edac.c 	way1 = pvt->mir1 & 0x2;
pvt              1104 drivers/edac/i5400_edac.c 		pci_read_config_word(pvt->branch_0, where,
pvt              1105 drivers/edac/i5400_edac.c 				&pvt->b0_mtr[slot_row]);
pvt              1108 drivers/edac/i5400_edac.c 			 slot_row, where, pvt->b0_mtr[slot_row]);
pvt              1110 drivers/edac/i5400_edac.c 		if (pvt->maxch < CHANNELS_PER_BRANCH) {
pvt              1111 drivers/edac/i5400_edac.c 			pvt->b1_mtr[slot_row] = 0;
pvt              1116 drivers/edac/i5400_edac.c 		pci_read_config_word(pvt->branch_1, where,
pvt              1117 drivers/edac/i5400_edac.c 				&pvt->b1_mtr[slot_row]);
pvt              1119 drivers/edac/i5400_edac.c 			 slot_row, where, pvt->b1_mtr[slot_row]);
pvt              1126 drivers/edac/i5400_edac.c 		decode_mtr(slot_row, pvt->b0_mtr[slot_row]);
pvt              1128 drivers/edac/i5400_edac.c 	pci_read_config_word(pvt->branch_0, AMBPRESENT_0,
pvt              1129 drivers/edac/i5400_edac.c 			&pvt->b0_ambpresent0);
pvt              1130 drivers/edac/i5400_edac.c 	edac_dbg(2, "\t\tAMB-Branch 0-present0 0x%x:\n", pvt->b0_ambpresent0);
pvt              1131 drivers/edac/i5400_edac.c 	pci_read_config_word(pvt->branch_0, AMBPRESENT_1,
pvt              1132 drivers/edac/i5400_edac.c 			&pvt->b0_ambpresent1);
pvt              1133 drivers/edac/i5400_edac.c 	edac_dbg(2, "\t\tAMB-Branch 0-present1 0x%x:\n", pvt->b0_ambpresent1);
pvt              1136 drivers/edac/i5400_edac.c 	if (pvt->maxch < CHANNELS_PER_BRANCH) {
pvt              1137 drivers/edac/i5400_edac.c 		pvt->b1_ambpresent0 = 0;
pvt              1138 drivers/edac/i5400_edac.c 		pvt->b1_ambpresent1 = 0;
pvt              1143 drivers/edac/i5400_edac.c 			decode_mtr(slot_row, pvt->b1_mtr[slot_row]);
pvt              1145 drivers/edac/i5400_edac.c 		pci_read_config_word(pvt->branch_1, AMBPRESENT_0,
pvt              1146 drivers/edac/i5400_edac.c 				&pvt->b1_ambpresent0);
pvt              1148 drivers/edac/i5400_edac.c 			 pvt->b1_ambpresent0);
pvt              1149 drivers/edac/i5400_edac.c 		pci_read_config_word(pvt->branch_1, AMBPRESENT_1,
pvt              1150 drivers/edac/i5400_edac.c 				&pvt->b1_ambpresent1);
pvt              1152 drivers/edac/i5400_edac.c 			 pvt->b1_ambpresent1);
pvt              1157 drivers/edac/i5400_edac.c 	calculate_dimm_size(pvt);
pvt              1171 drivers/edac/i5400_edac.c 	struct i5400_pvt *pvt;
pvt              1179 drivers/edac/i5400_edac.c 	pvt = mci->pvt_info;
pvt              1181 drivers/edac/i5400_edac.c 	channel_count = pvt->maxch;
pvt              1182 drivers/edac/i5400_edac.c 	max_dimms = pvt->maxdimmperch;
pvt              1193 drivers/edac/i5400_edac.c 			mtr = determine_mtr(pvt, slot, channel);
pvt              1202 drivers/edac/i5400_edac.c 			size_mb =  pvt->dimm_info[slot][channel].megabytes;
pvt              1239 drivers/edac/i5400_edac.c 	struct i5400_pvt *pvt;
pvt              1242 drivers/edac/i5400_edac.c 	pvt = mci->pvt_info;
pvt              1245 drivers/edac/i5400_edac.c 	pci_read_config_dword(pvt->branchmap_werrors, EMASK_FBD,
pvt              1251 drivers/edac/i5400_edac.c 	pci_write_config_dword(pvt->branchmap_werrors, EMASK_FBD,
pvt              1265 drivers/edac/i5400_edac.c 	struct i5400_pvt *pvt;
pvt              1293 drivers/edac/i5400_edac.c 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
pvt              1301 drivers/edac/i5400_edac.c 	pvt = mci->pvt_info;
pvt              1302 drivers/edac/i5400_edac.c 	pvt->system_address = pdev;	/* Record this device in our private */
pvt              1303 drivers/edac/i5400_edac.c 	pvt->maxch = MAX_CHANNELS;
pvt              1304 drivers/edac/i5400_edac.c 	pvt->maxdimmperch = DIMMS_PER_CHANNEL;
pvt               353 drivers/edac/i7300_edac.c 	struct i7300_pvt *pvt;
pvt               359 drivers/edac/i7300_edac.c 	pvt = mci->pvt_info;
pvt               362 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
pvt               372 drivers/edac/i7300_edac.c 		pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
pvt               378 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
pvt               388 drivers/edac/i7300_edac.c 		pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
pvt               408 drivers/edac/i7300_edac.c 	struct i7300_pvt *pvt;
pvt               418 drivers/edac/i7300_edac.c 	pvt = mci->pvt_info;
pvt               421 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               430 drivers/edac/i7300_edac.c 		pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
pvt               435 drivers/edac/i7300_edac.c 		pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               442 drivers/edac/i7300_edac.c 		pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               445 drivers/edac/i7300_edac.c 		snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
pvt               452 drivers/edac/i7300_edac.c 				     pvt->tmp_prt_buffer);
pvt               457 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               466 drivers/edac/i7300_edac.c 		pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               469 drivers/edac/i7300_edac.c 		pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map,
pvt               474 drivers/edac/i7300_edac.c 		pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               480 drivers/edac/i7300_edac.c 		pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               488 drivers/edac/i7300_edac.c 		pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               492 drivers/edac/i7300_edac.c 		snprintf(pvt->tmp_prt_buffer, PAGE_SIZE,
pvt               500 drivers/edac/i7300_edac.c 				     pvt->tmp_prt_buffer);
pvt               521 drivers/edac/i7300_edac.c 	struct i7300_pvt *pvt = mci->pvt_info;
pvt               529 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
pvt               531 drivers/edac/i7300_edac.c 	pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
pvt               534 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
pvt               536 drivers/edac/i7300_edac.c 	pci_write_config_dword(pvt->pci_dev_16_2_fsb_err_regs,
pvt               540 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               542 drivers/edac/i7300_edac.c 	pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               545 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               547 drivers/edac/i7300_edac.c 	pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               558 drivers/edac/i7300_edac.c 	struct i7300_pvt *pvt = mci->pvt_info;
pvt               562 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               568 drivers/edac/i7300_edac.c 	pci_write_config_dword(pvt->pci_dev_16_1_fsb_addr_map,
pvt               585 drivers/edac/i7300_edac.c static int decode_mtr(struct i7300_pvt *pvt,
pvt               594 drivers/edac/i7300_edac.c 	mtr = pvt->mtr[slot][branch];
pvt               652 drivers/edac/i7300_edac.c 	if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
pvt               666 drivers/edac/i7300_edac.c 			 IS_SCRBALGO_ENHANCED(pvt->mc_settings) ?
pvt               682 drivers/edac/i7300_edac.c static void print_dimm_size(struct i7300_pvt *pvt)
pvt               691 drivers/edac/i7300_edac.c 	p = pvt->tmp_prt_buffer;
pvt               701 drivers/edac/i7300_edac.c 	edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
pvt               702 drivers/edac/i7300_edac.c 	p = pvt->tmp_prt_buffer;
pvt               708 drivers/edac/i7300_edac.c 	edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
pvt               709 drivers/edac/i7300_edac.c 	p = pvt->tmp_prt_buffer;
pvt               718 drivers/edac/i7300_edac.c 			dinfo = &pvt->dimm_info[slot][channel];
pvt               724 drivers/edac/i7300_edac.c 		edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
pvt               725 drivers/edac/i7300_edac.c 		p = pvt->tmp_prt_buffer;
pvt               733 drivers/edac/i7300_edac.c 	edac_dbg(2, "%s\n", pvt->tmp_prt_buffer);
pvt               734 drivers/edac/i7300_edac.c 	p = pvt->tmp_prt_buffer;
pvt               747 drivers/edac/i7300_edac.c 	struct i7300_pvt *pvt;
pvt               754 drivers/edac/i7300_edac.c 	pvt = mci->pvt_info;
pvt               758 drivers/edac/i7300_edac.c 	if (IS_SINGLE_MODE(pvt->mc_settings_a)) {
pvt               770 drivers/edac/i7300_edac.c 		pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
pvt               772 drivers/edac/i7300_edac.c 				&pvt->ambpresent[channel]);
pvt               774 drivers/edac/i7300_edac.c 			 channel, pvt->ambpresent[channel]);
pvt               780 drivers/edac/i7300_edac.c 		pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
pvt               782 drivers/edac/i7300_edac.c 				&pvt->ambpresent[channel]);
pvt               784 drivers/edac/i7300_edac.c 			 channel, pvt->ambpresent[channel]);
pvt               791 drivers/edac/i7300_edac.c 			pci_read_config_word(pvt->pci_dev_2x_0_fbd_branch[branch],
pvt               793 drivers/edac/i7300_edac.c 					&pvt->mtr[slot][branch]);
pvt               800 drivers/edac/i7300_edac.c 				dinfo = &pvt->dimm_info[slot][channel];
pvt               802 drivers/edac/i7300_edac.c 				mtr = decode_mtr(pvt, slot, ch, branch,
pvt               841 drivers/edac/i7300_edac.c 	struct i7300_pvt *pvt;
pvt               845 drivers/edac/i7300_edac.c 	pvt = mci->pvt_info;
pvt               847 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_0_fsb_ctlr, AMBASE,
pvt               848 drivers/edac/i7300_edac.c 			(u32 *) &pvt->ambase);
pvt               850 drivers/edac/i7300_edac.c 	edac_dbg(2, "AMBASE= 0x%lx\n", (long unsigned int)pvt->ambase);
pvt               853 drivers/edac/i7300_edac.c 	pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, TOLM, &pvt->tolm);
pvt               854 drivers/edac/i7300_edac.c 	pvt->tolm >>= 12;
pvt               856 drivers/edac/i7300_edac.c 		 pvt->tolm, pvt->tolm);
pvt               858 drivers/edac/i7300_edac.c 	actual_tolm = (u32) ((1000l * pvt->tolm) >> (30 - 28));
pvt               860 drivers/edac/i7300_edac.c 		 actual_tolm/1000, actual_tolm % 1000, pvt->tolm << 28);
pvt               863 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS,
pvt               864 drivers/edac/i7300_edac.c 			     &pvt->mc_settings);
pvt               865 drivers/edac/i7300_edac.c 	pci_read_config_dword(pvt->pci_dev_16_1_fsb_addr_map, MC_SETTINGS_A,
pvt               866 drivers/edac/i7300_edac.c 			     &pvt->mc_settings_a);
pvt               868 drivers/edac/i7300_edac.c 	if (IS_SINGLE_MODE(pvt->mc_settings_a))
pvt               872 drivers/edac/i7300_edac.c 			 IS_MIRRORED(pvt->mc_settings) ? "" : "non-");
pvt               875 drivers/edac/i7300_edac.c 		 IS_ECC_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
pvt               877 drivers/edac/i7300_edac.c 		 IS_RETRY_ENABLED(pvt->mc_settings) ? "enabled" : "disabled");
pvt               880 drivers/edac/i7300_edac.c 	pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR0,
pvt               881 drivers/edac/i7300_edac.c 			     &pvt->mir[0]);
pvt               882 drivers/edac/i7300_edac.c 	pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR1,
pvt               883 drivers/edac/i7300_edac.c 			     &pvt->mir[1]);
pvt               884 drivers/edac/i7300_edac.c 	pci_read_config_word(pvt->pci_dev_16_1_fsb_addr_map, MIR2,
pvt               885 drivers/edac/i7300_edac.c 			     &pvt->mir[2]);
pvt               889 drivers/edac/i7300_edac.c 		decode_mir(i, pvt->mir);
pvt               897 drivers/edac/i7300_edac.c 	print_dimm_size(pvt);
pvt               912 drivers/edac/i7300_edac.c 	struct i7300_pvt *pvt;
pvt               915 drivers/edac/i7300_edac.c 	pvt = mci->pvt_info;
pvt               919 drivers/edac/i7300_edac.c 		pci_dev_put(pvt->pci_dev_2x_0_fbd_branch[branch]);
pvt               920 drivers/edac/i7300_edac.c 	pci_dev_put(pvt->pci_dev_16_2_fsb_err_regs);
pvt               921 drivers/edac/i7300_edac.c 	pci_dev_put(pvt->pci_dev_16_1_fsb_addr_map);
pvt               937 drivers/edac/i7300_edac.c 	struct i7300_pvt *pvt;
pvt               940 drivers/edac/i7300_edac.c 	pvt = mci->pvt_info;
pvt               950 drivers/edac/i7300_edac.c 			if (!pvt->pci_dev_16_1_fsb_addr_map)
pvt               951 drivers/edac/i7300_edac.c 				pvt->pci_dev_16_1_fsb_addr_map =
pvt               955 drivers/edac/i7300_edac.c 			if (!pvt->pci_dev_16_2_fsb_err_regs)
pvt               956 drivers/edac/i7300_edac.c 				pvt->pci_dev_16_2_fsb_err_regs =
pvt               962 drivers/edac/i7300_edac.c 	if (!pvt->pci_dev_16_1_fsb_addr_map ||
pvt               963 drivers/edac/i7300_edac.c 	    !pvt->pci_dev_16_2_fsb_err_regs) {
pvt               974 drivers/edac/i7300_edac.c 		 pci_name(pvt->pci_dev_16_0_fsb_ctlr),
pvt               975 drivers/edac/i7300_edac.c 		 pvt->pci_dev_16_0_fsb_ctlr->vendor,
pvt               976 drivers/edac/i7300_edac.c 		 pvt->pci_dev_16_0_fsb_ctlr->device);
pvt               978 drivers/edac/i7300_edac.c 		 pci_name(pvt->pci_dev_16_1_fsb_addr_map),
pvt               979 drivers/edac/i7300_edac.c 		 pvt->pci_dev_16_1_fsb_addr_map->vendor,
pvt               980 drivers/edac/i7300_edac.c 		 pvt->pci_dev_16_1_fsb_addr_map->device);
pvt               982 drivers/edac/i7300_edac.c 		 pci_name(pvt->pci_dev_16_2_fsb_err_regs),
pvt               983 drivers/edac/i7300_edac.c 		 pvt->pci_dev_16_2_fsb_err_regs->vendor,
pvt               984 drivers/edac/i7300_edac.c 		 pvt->pci_dev_16_2_fsb_err_regs->device);
pvt               986 drivers/edac/i7300_edac.c 	pvt->pci_dev_2x_0_fbd_branch[0] = pci_get_device(PCI_VENDOR_ID_INTEL,
pvt               989 drivers/edac/i7300_edac.c 	if (!pvt->pci_dev_2x_0_fbd_branch[0]) {
pvt               997 drivers/edac/i7300_edac.c 	pvt->pci_dev_2x_0_fbd_branch[1] = pci_get_device(PCI_VENDOR_ID_INTEL,
pvt              1000 drivers/edac/i7300_edac.c 	if (!pvt->pci_dev_2x_0_fbd_branch[1]) {
pvt              1026 drivers/edac/i7300_edac.c 	struct i7300_pvt *pvt;
pvt              1052 drivers/edac/i7300_edac.c 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
pvt              1060 drivers/edac/i7300_edac.c 	pvt = mci->pvt_info;
pvt              1061 drivers/edac/i7300_edac.c 	pvt->pci_dev_16_0_fsb_ctlr = pdev;	/* Record this device in our private */
pvt              1063 drivers/edac/i7300_edac.c 	pvt->tmp_prt_buffer = kmalloc(PAGE_SIZE, GFP_KERNEL);
pvt              1064 drivers/edac/i7300_edac.c 	if (!pvt->tmp_prt_buffer) {
pvt              1125 drivers/edac/i7300_edac.c 	kfree(pvt->tmp_prt_buffer);
pvt               396 drivers/edac/i7core_edac.c #define CH_ACTIVE(pvt, ch)	((pvt)->info.mc_control & (1 << (8 + ch)))
pvt               397 drivers/edac/i7core_edac.c #define ECCx8(pvt)		((pvt)->info.mc_control & (1 << 1))
pvt               400 drivers/edac/i7core_edac.c #define ECC_ENABLED(pvt)	((pvt)->info.mc_status & (1 << 4))
pvt               401 drivers/edac/i7core_edac.c #define CH_DISABLED(pvt, ch)	((pvt)->info.mc_status & (1 << ch))
pvt               489 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt               497 drivers/edac/i7core_edac.c 	pdev = pvt->pci_mcr[0];
pvt               502 drivers/edac/i7core_edac.c 	pci_read_config_dword(pdev, MC_CONTROL, &pvt->info.mc_control);
pvt               503 drivers/edac/i7core_edac.c 	pci_read_config_dword(pdev, MC_STATUS, &pvt->info.mc_status);
pvt               504 drivers/edac/i7core_edac.c 	pci_read_config_dword(pdev, MC_MAX_DOD, &pvt->info.max_dod);
pvt               505 drivers/edac/i7core_edac.c 	pci_read_config_dword(pdev, MC_CHANNEL_MAPPER, &pvt->info.ch_map);
pvt               508 drivers/edac/i7core_edac.c 		 pvt->i7core_dev->socket, pvt->info.mc_control,
pvt               509 drivers/edac/i7core_edac.c 		 pvt->info.mc_status, pvt->info.max_dod, pvt->info.ch_map);
pvt               511 drivers/edac/i7core_edac.c 	if (ECC_ENABLED(pvt)) {
pvt               512 drivers/edac/i7core_edac.c 		edac_dbg(0, "ECC enabled with x%d SDCC\n", ECCx8(pvt) ? 8 : 4);
pvt               513 drivers/edac/i7core_edac.c 		if (ECCx8(pvt))
pvt               524 drivers/edac/i7core_edac.c 		 numdimms(pvt->info.max_dod),
pvt               525 drivers/edac/i7core_edac.c 		 numrank(pvt->info.max_dod >> 2),
pvt               526 drivers/edac/i7core_edac.c 		 numbank(pvt->info.max_dod >> 4),
pvt               527 drivers/edac/i7core_edac.c 		 numrow(pvt->info.max_dod >> 6),
pvt               528 drivers/edac/i7core_edac.c 		 numcol(pvt->info.max_dod >> 9));
pvt               533 drivers/edac/i7core_edac.c 		if (!pvt->pci_ch[i][0])
pvt               536 drivers/edac/i7core_edac.c 		if (!CH_ACTIVE(pvt, i)) {
pvt               540 drivers/edac/i7core_edac.c 		if (CH_DISABLED(pvt, i)) {
pvt               546 drivers/edac/i7core_edac.c 		pci_read_config_dword(pvt->pci_ch[i][0],
pvt               551 drivers/edac/i7core_edac.c 			pvt->channel[i].is_3dimms_present = true;
pvt               554 drivers/edac/i7core_edac.c 			pvt->channel[i].is_single_4rank = true;
pvt               557 drivers/edac/i7core_edac.c 			pvt->channel[i].has_4rank = true;
pvt               565 drivers/edac/i7core_edac.c 		pci_read_config_dword(pvt->pci_ch[i][1],
pvt               567 drivers/edac/i7core_edac.c 		pci_read_config_dword(pvt->pci_ch[i][1],
pvt               569 drivers/edac/i7core_edac.c 		pci_read_config_dword(pvt->pci_ch[i][1],
pvt               574 drivers/edac/i7core_edac.c 			 RDLCH(pvt->info.ch_map, i), WRLCH(pvt->info.ch_map, i),
pvt               576 drivers/edac/i7core_edac.c 			 pvt->channel[i].is_3dimms_present ? "3DIMMS " : "",
pvt               577 drivers/edac/i7core_edac.c 			 pvt->channel[i].is_3dimms_present ? "SINGLE_4R " : "",
pvt               578 drivers/edac/i7core_edac.c 			 pvt->channel[i].has_4rank ? "HAS_4R " : "",
pvt               623 drivers/edac/i7core_edac.c 				 pvt->i7core_dev->socket, i, j);
pvt               663 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt               665 drivers/edac/i7core_edac.c 	pvt->inject.enable = 0;
pvt               667 drivers/edac/i7core_edac.c 	if (!pvt->pci_ch[pvt->inject.channel][0])
pvt               670 drivers/edac/i7core_edac.c 	pci_write_config_dword(pvt->pci_ch[pvt->inject.channel][0],
pvt               688 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt               692 drivers/edac/i7core_edac.c 	if (pvt->inject.enable)
pvt               699 drivers/edac/i7core_edac.c 	pvt->inject.section = (u32) value;
pvt               708 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt               709 drivers/edac/i7core_edac.c 	return sprintf(data, "0x%08x\n", pvt->inject.section);
pvt               725 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt               729 drivers/edac/i7core_edac.c 	if (pvt->inject.enable)
pvt               736 drivers/edac/i7core_edac.c 	pvt->inject.type = (u32) value;
pvt               745 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt               747 drivers/edac/i7core_edac.c 	return sprintf(data, "0x%08x\n", pvt->inject.type);
pvt               765 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt               769 drivers/edac/i7core_edac.c 	if (pvt->inject.enable)
pvt               776 drivers/edac/i7core_edac.c 	pvt->inject.eccmask = (u32) value;
pvt               785 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt               787 drivers/edac/i7core_edac.c 	return sprintf(data, "0x%08x\n", pvt->inject.eccmask);
pvt               808 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt;					\
pvt               813 drivers/edac/i7core_edac.c 	pvt = mci->pvt_info;					\
pvt               815 drivers/edac/i7core_edac.c 	if (pvt->inject.enable)					\
pvt               826 drivers/edac/i7core_edac.c 	pvt->inject.param = value;				\
pvt               837 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt;					\
pvt               839 drivers/edac/i7core_edac.c 	pvt = mci->pvt_info;					\
pvt               840 drivers/edac/i7core_edac.c 	edac_dbg(1, "pvt=%p\n", pvt);				\
pvt               841 drivers/edac/i7core_edac.c 	if (pvt->inject.param < 0)				\
pvt               844 drivers/edac/i7core_edac.c 		return sprintf(data, "%d\n", pvt->inject.param);\
pvt               916 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt               922 drivers/edac/i7core_edac.c 	if (!pvt->pci_ch[pvt->inject.channel][0])
pvt               930 drivers/edac/i7core_edac.c 		pvt->inject.enable = 1;
pvt               937 drivers/edac/i7core_edac.c 	if (pvt->inject.dimm < 0)
pvt               940 drivers/edac/i7core_edac.c 		if (pvt->channel[pvt->inject.channel].dimms > 2)
pvt               941 drivers/edac/i7core_edac.c 			mask |= (pvt->inject.dimm & 0x3LL) << 35;
pvt               943 drivers/edac/i7core_edac.c 			mask |= (pvt->inject.dimm & 0x1LL) << 36;
pvt               947 drivers/edac/i7core_edac.c 	if (pvt->inject.rank < 0)
pvt               950 drivers/edac/i7core_edac.c 		if (pvt->channel[pvt->inject.channel].dimms > 2)
pvt               951 drivers/edac/i7core_edac.c 			mask |= (pvt->inject.rank & 0x1LL) << 34;
pvt               953 drivers/edac/i7core_edac.c 			mask |= (pvt->inject.rank & 0x3LL) << 34;
pvt               957 drivers/edac/i7core_edac.c 	if (pvt->inject.bank < 0)
pvt               960 drivers/edac/i7core_edac.c 		mask |= (pvt->inject.bank & 0x15LL) << 30;
pvt               963 drivers/edac/i7core_edac.c 	if (pvt->inject.page < 0)
pvt               966 drivers/edac/i7core_edac.c 		mask |= (pvt->inject.page & 0xffff) << 14;
pvt               969 drivers/edac/i7core_edac.c 	if (pvt->inject.col < 0)
pvt               972 drivers/edac/i7core_edac.c 		mask |= (pvt->inject.col & 0x3fff);
pvt               981 drivers/edac/i7core_edac.c 	injectmask = (pvt->inject.type & 1) |
pvt               982 drivers/edac/i7core_edac.c 		     (pvt->inject.section & 0x3) << 1 |
pvt               983 drivers/edac/i7core_edac.c 		     (pvt->inject.type & 0x6) << (3 - 1);
pvt               986 drivers/edac/i7core_edac.c 	pci_write_config_dword(pvt->pci_noncore,
pvt               989 drivers/edac/i7core_edac.c 	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
pvt               991 drivers/edac/i7core_edac.c 	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
pvt               994 drivers/edac/i7core_edac.c 	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
pvt               995 drivers/edac/i7core_edac.c 			       MC_CHANNEL_ERROR_MASK, pvt->inject.eccmask);
pvt               997 drivers/edac/i7core_edac.c 	write_and_test(pvt->pci_ch[pvt->inject.channel][0],
pvt              1005 drivers/edac/i7core_edac.c 	pci_write_config_dword(pvt->pci_noncore,
pvt              1009 drivers/edac/i7core_edac.c 		 mask, pvt->inject.eccmask, injectmask);
pvt              1020 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1023 drivers/edac/i7core_edac.c 	if (!pvt->pci_ch[pvt->inject.channel][0])
pvt              1026 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_ch[pvt->inject.channel][0],
pvt              1032 drivers/edac/i7core_edac.c 		pvt->inject.enable = 1;
pvt              1034 drivers/edac/i7core_edac.c 	return sprintf(data, "%d\n", pvt->inject.enable);
pvt              1044 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;			\
pvt              1047 drivers/edac/i7core_edac.c 	if (!pvt->ce_count_available || (pvt->is_registered))	\
pvt              1050 drivers/edac/i7core_edac.c 			pvt->udimm_ce_count[param]);		\
pvt              1160 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1163 drivers/edac/i7core_edac.c 	pvt->addrmatch_dev = kzalloc(sizeof(*pvt->addrmatch_dev), GFP_KERNEL);
pvt              1164 drivers/edac/i7core_edac.c 	if (!pvt->addrmatch_dev)
pvt              1167 drivers/edac/i7core_edac.c 	pvt->addrmatch_dev->type = &addrmatch_type;
pvt              1168 drivers/edac/i7core_edac.c 	pvt->addrmatch_dev->bus = mci->dev.bus;
pvt              1169 drivers/edac/i7core_edac.c 	device_initialize(pvt->addrmatch_dev);
pvt              1170 drivers/edac/i7core_edac.c 	pvt->addrmatch_dev->parent = &mci->dev;
pvt              1171 drivers/edac/i7core_edac.c 	dev_set_name(pvt->addrmatch_dev, "inject_addrmatch");
pvt              1172 drivers/edac/i7core_edac.c 	dev_set_drvdata(pvt->addrmatch_dev, mci);
pvt              1174 drivers/edac/i7core_edac.c 	edac_dbg(1, "creating %s\n", dev_name(pvt->addrmatch_dev));
pvt              1176 drivers/edac/i7core_edac.c 	rc = device_add(pvt->addrmatch_dev);
pvt              1180 drivers/edac/i7core_edac.c 	if (!pvt->is_registered) {
pvt              1181 drivers/edac/i7core_edac.c 		pvt->chancounts_dev = kzalloc(sizeof(*pvt->chancounts_dev),
pvt              1183 drivers/edac/i7core_edac.c 		if (!pvt->chancounts_dev) {
pvt              1188 drivers/edac/i7core_edac.c 		pvt->chancounts_dev->type = &all_channel_counts_type;
pvt              1189 drivers/edac/i7core_edac.c 		pvt->chancounts_dev->bus = mci->dev.bus;
pvt              1190 drivers/edac/i7core_edac.c 		device_initialize(pvt->chancounts_dev);
pvt              1191 drivers/edac/i7core_edac.c 		pvt->chancounts_dev->parent = &mci->dev;
pvt              1192 drivers/edac/i7core_edac.c 		dev_set_name(pvt->chancounts_dev, "all_channel_counts");
pvt              1193 drivers/edac/i7core_edac.c 		dev_set_drvdata(pvt->chancounts_dev, mci);
pvt              1195 drivers/edac/i7core_edac.c 		edac_dbg(1, "creating %s\n", dev_name(pvt->chancounts_dev));
pvt              1197 drivers/edac/i7core_edac.c 		rc = device_add(pvt->chancounts_dev);
pvt              1204 drivers/edac/i7core_edac.c 	put_device(pvt->chancounts_dev);
pvt              1206 drivers/edac/i7core_edac.c 	device_del(pvt->addrmatch_dev);
pvt              1208 drivers/edac/i7core_edac.c 	put_device(pvt->addrmatch_dev);
pvt              1215 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1219 drivers/edac/i7core_edac.c 	if (!pvt->is_registered) {
pvt              1220 drivers/edac/i7core_edac.c 		device_del(pvt->chancounts_dev);
pvt              1221 drivers/edac/i7core_edac.c 		put_device(pvt->chancounts_dev);
pvt              1223 drivers/edac/i7core_edac.c 	device_del(pvt->addrmatch_dev);
pvt              1224 drivers/edac/i7core_edac.c 	put_device(pvt->addrmatch_dev);
pvt              1456 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1461 drivers/edac/i7core_edac.c 	pvt->is_registered = false;
pvt              1462 drivers/edac/i7core_edac.c 	pvt->enable_scrub  = false;
pvt              1473 drivers/edac/i7core_edac.c 			pvt->pci_mcr[func] = pdev;
pvt              1477 drivers/edac/i7core_edac.c 			pvt->pci_ch[slot - 4][func] = pdev;
pvt              1479 drivers/edac/i7core_edac.c 			pvt->pci_noncore = pdev;
pvt              1485 drivers/edac/i7core_edac.c 				pvt->enable_scrub = false;
pvt              1489 drivers/edac/i7core_edac.c 				pvt->enable_scrub = false;
pvt              1493 drivers/edac/i7core_edac.c 				pvt->enable_scrub = false;
pvt              1497 drivers/edac/i7core_edac.c 				pvt->enable_scrub = true;
pvt              1501 drivers/edac/i7core_edac.c 				pvt->enable_scrub = true;
pvt              1505 drivers/edac/i7core_edac.c 				pvt->enable_scrub = false;
pvt              1517 drivers/edac/i7core_edac.c 			pvt->is_registered = true;
pvt              1539 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1542 drivers/edac/i7core_edac.c 	if (pvt->ce_count_available) {
pvt              1545 drivers/edac/i7core_edac.c 		add2 = new2 - pvt->rdimm_last_ce_count[chan][2];
pvt              1546 drivers/edac/i7core_edac.c 		add1 = new1 - pvt->rdimm_last_ce_count[chan][1];
pvt              1547 drivers/edac/i7core_edac.c 		add0 = new0 - pvt->rdimm_last_ce_count[chan][0];
pvt              1551 drivers/edac/i7core_edac.c 		pvt->rdimm_ce_count[chan][2] += add2;
pvt              1555 drivers/edac/i7core_edac.c 		pvt->rdimm_ce_count[chan][1] += add1;
pvt              1559 drivers/edac/i7core_edac.c 		pvt->rdimm_ce_count[chan][0] += add0;
pvt              1561 drivers/edac/i7core_edac.c 		pvt->ce_count_available = 1;
pvt              1564 drivers/edac/i7core_edac.c 	pvt->rdimm_last_ce_count[chan][2] = new2;
pvt              1565 drivers/edac/i7core_edac.c 	pvt->rdimm_last_ce_count[chan][1] = new1;
pvt              1566 drivers/edac/i7core_edac.c 	pvt->rdimm_last_ce_count[chan][0] = new0;
pvt              1585 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1590 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_0,
pvt              1592 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_1,
pvt              1594 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_2,
pvt              1596 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_3,
pvt              1598 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_4,
pvt              1600 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_mcr[2], MC_COR_ECC_CNT_5,
pvt              1606 drivers/edac/i7core_edac.c 		if (pvt->channel[i].dimms > 2) {
pvt              1630 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1634 drivers/edac/i7core_edac.c 	if (!pvt->pci_mcr[4]) {
pvt              1640 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV1, &rcv1);
pvt              1641 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_mcr[4], MC_TEST_ERR_RCV0, &rcv0);
pvt              1649 drivers/edac/i7core_edac.c 	if (pvt->ce_count_available) {
pvt              1653 drivers/edac/i7core_edac.c 		add2 = new2 - pvt->udimm_last_ce_count[2];
pvt              1654 drivers/edac/i7core_edac.c 		add1 = new1 - pvt->udimm_last_ce_count[1];
pvt              1655 drivers/edac/i7core_edac.c 		add0 = new0 - pvt->udimm_last_ce_count[0];
pvt              1659 drivers/edac/i7core_edac.c 		pvt->udimm_ce_count[2] += add2;
pvt              1663 drivers/edac/i7core_edac.c 		pvt->udimm_ce_count[1] += add1;
pvt              1667 drivers/edac/i7core_edac.c 		pvt->udimm_ce_count[0] += add0;
pvt              1674 drivers/edac/i7core_edac.c 		pvt->ce_count_available = 1;
pvt              1677 drivers/edac/i7core_edac.c 	pvt->udimm_last_ce_count[2] = new2;
pvt              1678 drivers/edac/i7core_edac.c 	pvt->udimm_last_ce_count[1] = new1;
pvt              1679 drivers/edac/i7core_edac.c 	pvt->udimm_last_ce_count[0] = new0;
pvt              1698 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1779 drivers/edac/i7core_edac.c 	if (uncorrected_error || !pvt->is_registered)
pvt              1794 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1801 drivers/edac/i7core_edac.c 	if (!pvt->is_registered)
pvt              1959 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              1965 drivers/edac/i7core_edac.c 	pdev = pvt->pci_mcr[2];
pvt              1984 drivers/edac/i7core_edac.c 		const u32 freq_dclk_mhz = pvt->dclk_freq;
pvt              2021 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              2024 drivers/edac/i7core_edac.c 	const u32 freq_dclk_mhz = pvt->dclk_freq;
pvt              2029 drivers/edac/i7core_edac.c 	pdev = pvt->pci_mcr[2];
pvt              2050 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              2054 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
pvt              2056 drivers/edac/i7core_edac.c 	pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
pvt              2065 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt = mci->pvt_info;
pvt              2069 drivers/edac/i7core_edac.c 	pci_read_config_dword(pvt->pci_noncore, MC_CFG_CONTROL, &pci_lock);
pvt              2071 drivers/edac/i7core_edac.c 	pci_write_config_dword(pvt->pci_noncore, MC_CFG_CONTROL,
pvt              2075 drivers/edac/i7core_edac.c static void i7core_pci_ctl_create(struct i7core_pvt *pvt)
pvt              2077 drivers/edac/i7core_edac.c 	pvt->i7core_pci = edac_pci_create_generic_ctl(
pvt              2078 drivers/edac/i7core_edac.c 						&pvt->i7core_dev->pdev[0]->dev,
pvt              2080 drivers/edac/i7core_edac.c 	if (unlikely(!pvt->i7core_pci))
pvt              2085 drivers/edac/i7core_edac.c static void i7core_pci_ctl_release(struct i7core_pvt *pvt)
pvt              2087 drivers/edac/i7core_edac.c 	if (likely(pvt->i7core_pci))
pvt              2088 drivers/edac/i7core_edac.c 		edac_pci_release_generic_ctl(pvt->i7core_pci);
pvt              2092 drivers/edac/i7core_edac.c 				pvt->i7core_dev->socket);
pvt              2093 drivers/edac/i7core_edac.c 	pvt->i7core_pci = NULL;
pvt              2099 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt;
pvt              2108 drivers/edac/i7core_edac.c 	pvt = mci->pvt_info;
pvt              2113 drivers/edac/i7core_edac.c 	if (pvt->enable_scrub)
pvt              2117 drivers/edac/i7core_edac.c 	i7core_pci_ctl_release(pvt);
pvt              2132 drivers/edac/i7core_edac.c 	struct i7core_pvt *pvt;
pvt              2145 drivers/edac/i7core_edac.c 			    sizeof(*pvt));
pvt              2151 drivers/edac/i7core_edac.c 	pvt = mci->pvt_info;
pvt              2152 drivers/edac/i7core_edac.c 	memset(pvt, 0, sizeof(*pvt));
pvt              2155 drivers/edac/i7core_edac.c 	pvt->i7core_dev = i7core_dev;
pvt              2189 drivers/edac/i7core_edac.c 	if (pvt->enable_scrub)
pvt              2210 drivers/edac/i7core_edac.c 	pvt->inject.channel = 0;
pvt              2211 drivers/edac/i7core_edac.c 	pvt->inject.dimm = -1;
pvt              2212 drivers/edac/i7core_edac.c 	pvt->inject.rank = -1;
pvt              2213 drivers/edac/i7core_edac.c 	pvt->inject.bank = -1;
pvt              2214 drivers/edac/i7core_edac.c 	pvt->inject.page = -1;
pvt              2215 drivers/edac/i7core_edac.c 	pvt->inject.col = -1;
pvt              2218 drivers/edac/i7core_edac.c 	i7core_pci_ctl_create(pvt);
pvt              2221 drivers/edac/i7core_edac.c 	pvt->dclk_freq = get_dclk_freq();
pvt               393 drivers/edac/i82875p_edac.c 	struct i82875p_pvt *pvt;
pvt               413 drivers/edac/i82875p_edac.c 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
pvt               430 drivers/edac/i82875p_edac.c 	pvt = (struct i82875p_pvt *)mci->pvt_info;
pvt               431 drivers/edac/i82875p_edac.c 	pvt->ovrfl_pdev = ovrfl_pdev;
pvt               432 drivers/edac/i82875p_edac.c 	pvt->ovrfl_window = ovrfl_window;
pvt               494 drivers/edac/i82875p_edac.c 	struct i82875p_pvt *pvt = NULL;
pvt               504 drivers/edac/i82875p_edac.c 	pvt = (struct i82875p_pvt *)mci->pvt_info;
pvt               506 drivers/edac/i82875p_edac.c 	if (pvt->ovrfl_window)
pvt               507 drivers/edac/i82875p_edac.c 		iounmap(pvt->ovrfl_window);
pvt               509 drivers/edac/i82875p_edac.c 	if (pvt->ovrfl_pdev) {
pvt               511 drivers/edac/i82875p_edac.c 		pci_release_regions(pvt->ovrfl_pdev);
pvt               513 drivers/edac/i82875p_edac.c 		pci_disable_device(pvt->ovrfl_pdev);
pvt               514 drivers/edac/i82875p_edac.c 		pci_dev_put(pvt->ovrfl_pdev);
pvt               469 drivers/edac/i82975x_edac.c 	struct i82975x_pvt *pvt;
pvt               547 drivers/edac/i82975x_edac.c 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
pvt               564 drivers/edac/i82975x_edac.c 	pvt = (struct i82975x_pvt *) mci->pvt_info;
pvt               565 drivers/edac/i82975x_edac.c 	pvt->mch_window = mch_window;
pvt               611 drivers/edac/i82975x_edac.c 	struct i82975x_pvt *pvt;
pvt               619 drivers/edac/i82975x_edac.c 	pvt = mci->pvt_info;
pvt               620 drivers/edac/i82975x_edac.c 	if (pvt->mch_window)
pvt               621 drivers/edac/i82975x_edac.c 		iounmap( pvt->mch_window );
pvt                73 drivers/edac/octeon_edac-lmc.c 	struct octeon_lmc_pvt *pvt = mci->pvt_info;
pvt                78 drivers/edac/octeon_edac-lmc.c 	if (!pvt->inject)
pvt                82 drivers/edac/octeon_edac-lmc.c 		if (pvt->error_type == 1)
pvt                84 drivers/edac/octeon_edac-lmc.c 		if (pvt->error_type == 2)
pvt                90 drivers/edac/octeon_edac-lmc.c 		if (likely(!pvt->inject))
pvt                93 drivers/edac/octeon_edac-lmc.c 			fadr.cn61xx.fdimm = pvt->dimm;
pvt                94 drivers/edac/octeon_edac-lmc.c 			fadr.cn61xx.fbunk = pvt->rank;
pvt                95 drivers/edac/octeon_edac-lmc.c 			fadr.cn61xx.fbank = pvt->bank;
pvt                96 drivers/edac/octeon_edac-lmc.c 			fadr.cn61xx.frow = pvt->row;
pvt                97 drivers/edac/octeon_edac-lmc.c 			fadr.cn61xx.fcol = pvt->col;
pvt               120 drivers/edac/octeon_edac-lmc.c 		if (likely(!pvt->inject))
pvt               123 drivers/edac/octeon_edac-lmc.c 			pvt->inject = 0;
pvt               136 drivers/edac/octeon_edac-lmc.c 	struct octeon_lmc_pvt *pvt = mci->pvt_info;			\
pvt               137 drivers/edac/octeon_edac-lmc.c 	return sprintf(data, "%016llu\n", (u64)pvt->reg);		\
pvt               146 drivers/edac/octeon_edac-lmc.c 	struct octeon_lmc_pvt *pvt = mci->pvt_info;			\
pvt               148 drivers/edac/octeon_edac-lmc.c 		if (!kstrtoul(data, 0, &pvt->reg))			\
pvt               173 drivers/edac/octeon_edac-lmc.c 	struct octeon_lmc_pvt *pvt = mci->pvt_info;
pvt               176 drivers/edac/octeon_edac-lmc.c 		pvt->error_type = 1;
pvt               178 drivers/edac/octeon_edac-lmc.c 		pvt->error_type = 2;
pvt               188 drivers/edac/octeon_edac-lmc.c 	struct octeon_lmc_pvt *pvt = mci->pvt_info;
pvt               189 drivers/edac/octeon_edac-lmc.c 	if (pvt->error_type == 1)
pvt               191 drivers/edac/octeon_edac-lmc.c 	else if (pvt->error_type == 2)
pvt               930 drivers/edac/pnd2_edac.c 	struct pnd2_pvt *pvt = mci->pvt_info;
pvt               931 drivers/edac/pnd2_edac.c 	int g = pvt->dimm_geom[pmiidx];
pvt              1224 drivers/edac/pnd2_edac.c 	struct pnd2_pvt	*pvt = mci->pvt_info;
pvt              1252 drivers/edac/pnd2_edac.c 		pvt->dimm_geom[i] = g;
pvt              1336 drivers/edac/pnd2_edac.c 	struct pnd2_pvt *pvt;
pvt              1350 drivers/edac/pnd2_edac.c 	mci = edac_mc_alloc(0, ARRAY_SIZE(layers), layers, sizeof(*pvt));
pvt              1354 drivers/edac/pnd2_edac.c 	pvt = mci->pvt_info;
pvt              1355 drivers/edac/pnd2_edac.c 	memset(pvt, 0, sizeof(*pvt));
pvt               316 drivers/edac/sb_edac.c 	u64		(*get_tolm)(struct sbridge_pvt *pvt);
pvt               317 drivers/edac/sb_edac.c 	u64		(*get_tohm)(struct sbridge_pvt *pvt);
pvt               326 drivers/edac/sb_edac.c 	u8		(*get_node_id)(struct sbridge_pvt *pvt);
pvt               328 drivers/edac/sb_edac.c 	enum mem_type	(*get_memory_type)(struct sbridge_pvt *pvt);
pvt               329 drivers/edac/sb_edac.c 	enum dev_type	(*get_width)(struct sbridge_pvt *pvt, u32 mtr);
pvt               792 drivers/edac/sb_edac.c static u64 sbridge_get_tolm(struct sbridge_pvt *pvt)
pvt               797 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_sad1, TOLM, &reg);
pvt               801 drivers/edac/sb_edac.c static u64 sbridge_get_tohm(struct sbridge_pvt *pvt)
pvt               805 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_sad1, TOHM, &reg);
pvt               809 drivers/edac/sb_edac.c static u64 ibridge_get_tolm(struct sbridge_pvt *pvt)
pvt               813 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_br1, TOLM, &reg);
pvt               818 drivers/edac/sb_edac.c static u64 ibridge_get_tohm(struct sbridge_pvt *pvt)
pvt               822 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_br1, TOHM, &reg);
pvt               875 drivers/edac/sb_edac.c static enum mem_type get_memory_type(struct sbridge_pvt *pvt)
pvt               880 drivers/edac/sb_edac.c 	if (pvt->pci_ddrio) {
pvt               881 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_ddrio, pvt->info.rankcfgr,
pvt               894 drivers/edac/sb_edac.c static enum mem_type haswell_get_memory_type(struct sbridge_pvt *pvt)
pvt               900 drivers/edac/sb_edac.c 	if (!pvt->pci_ddrio)
pvt               903 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_ddrio,
pvt               909 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_ta, MCMTR, &reg);
pvt               926 drivers/edac/sb_edac.c static enum dev_type knl_get_width(struct sbridge_pvt *pvt, u32 mtr)
pvt               932 drivers/edac/sb_edac.c static enum dev_type sbridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
pvt               960 drivers/edac/sb_edac.c static enum dev_type ibridge_get_width(struct sbridge_pvt *pvt, u32 mtr)
pvt               969 drivers/edac/sb_edac.c static enum dev_type broadwell_get_width(struct sbridge_pvt *pvt, u32 mtr)
pvt               975 drivers/edac/sb_edac.c static enum mem_type knl_get_memory_type(struct sbridge_pvt *pvt)
pvt               981 drivers/edac/sb_edac.c static u8 get_node_id(struct sbridge_pvt *pvt)
pvt               984 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_br0, SAD_CONTROL, &reg);
pvt               988 drivers/edac/sb_edac.c static u8 haswell_get_node_id(struct sbridge_pvt *pvt)
pvt               992 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
pvt               996 drivers/edac/sb_edac.c static u8 knl_get_node_id(struct sbridge_pvt *pvt)
pvt              1000 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_sad1, SAD_CONTROL, &reg);
pvt              1038 drivers/edac/sb_edac.c static u64 haswell_get_tolm(struct sbridge_pvt *pvt)
pvt              1042 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOLM, &reg);
pvt              1046 drivers/edac/sb_edac.c static u64 haswell_get_tohm(struct sbridge_pvt *pvt)
pvt              1051 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_0, &reg);
pvt              1053 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->info.pci_vtd, HASWELL_TOHM_1, &reg);
pvt              1059 drivers/edac/sb_edac.c static u64 knl_get_tolm(struct sbridge_pvt *pvt)
pvt              1063 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOLM, &reg);
pvt              1067 drivers/edac/sb_edac.c static u64 knl_get_tohm(struct sbridge_pvt *pvt)
pvt              1072 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_0, &reg_lo);
pvt              1073 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->knl.pci_mc_info, KNL_TOHM_1, &reg_hi);
pvt              1147 drivers/edac/sb_edac.c static int knl_get_tad(const struct sbridge_pvt *pvt,
pvt              1160 drivers/edac/sb_edac.c 		pci_mc = pvt->knl.pci_mc0;
pvt              1163 drivers/edac/sb_edac.c 		pci_mc = pvt->knl.pci_mc1;
pvt              1341 drivers/edac/sb_edac.c static int knl_get_dimm_capacity(struct sbridge_pvt *pvt, u64 *mc_sizes)
pvt              1368 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->knl.pci_cha[i],
pvt              1394 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->knl.pci_cha[i],
pvt              1417 drivers/edac/sb_edac.c 	for (sad_rule = 0; sad_rule < pvt->info.max_sad; sad_rule++) {
pvt              1421 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_sad0,
pvt              1422 drivers/edac/sb_edac.c 			pvt->info.dram_rule[sad_rule], &dram_rule);
pvt              1429 drivers/edac/sb_edac.c 		sad_limit = pvt->info.sad_limit(dram_rule)+1;
pvt              1432 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_sad0,
pvt              1433 drivers/edac/sb_edac.c 			pvt->info.interleave_list[sad_rule], &interleave_reg);
pvt              1439 drivers/edac/sb_edac.c 		first_pkg = sad_pkg(pvt->info.interleave_pkg,
pvt              1442 drivers/edac/sb_edac.c 			pkg = sad_pkg(pvt->info.interleave_pkg,
pvt              1486 drivers/edac/sb_edac.c 				if (knl_get_tad(pvt,
pvt              1567 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              1570 drivers/edac/sb_edac.c 	if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL ||
pvt              1571 drivers/edac/sb_edac.c 	    pvt->info.type == KNIGHTS_LANDING)
pvt              1572 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_sad1, SAD_TARGET, &reg);
pvt              1574 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_br0, SAD_TARGET, &reg);
pvt              1576 drivers/edac/sb_edac.c 	if (pvt->info.type == KNIGHTS_LANDING)
pvt              1577 drivers/edac/sb_edac.c 		pvt->sbridge_dev->source_id = SOURCE_ID_KNL(reg);
pvt              1579 drivers/edac/sb_edac.c 		pvt->sbridge_dev->source_id = SOURCE_ID(reg);
pvt              1586 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              1587 drivers/edac/sb_edac.c 	int channels = pvt->info.type == KNIGHTS_LANDING ? KNL_MAX_CHANNELS
pvt              1594 drivers/edac/sb_edac.c 	mtype = pvt->info.get_memory_type(pvt);
pvt              1612 drivers/edac/sb_edac.c 		if (pvt->info.type == KNIGHTS_LANDING) {
pvt              1614 drivers/edac/sb_edac.c 			if (!pvt->knl.pci_channel[i])
pvt              1618 drivers/edac/sb_edac.c 			if (!pvt->pci_tad[i])
pvt              1624 drivers/edac/sb_edac.c 			if (pvt->info.type == KNIGHTS_LANDING) {
pvt              1625 drivers/edac/sb_edac.c 				pci_read_config_dword(pvt->knl.pci_channel[i],
pvt              1628 drivers/edac/sb_edac.c 				pci_read_config_dword(pvt->pci_tad[i],
pvt              1633 drivers/edac/sb_edac.c 				if (!IS_ECC_ENABLED(pvt->info.mcmtr)) {
pvt              1635 drivers/edac/sb_edac.c 						       pvt->sbridge_dev->source_id,
pvt              1636 drivers/edac/sb_edac.c 						       pvt->sbridge_dev->dom, i);
pvt              1639 drivers/edac/sb_edac.c 				pvt->channel[i].dimms++;
pvt              1641 drivers/edac/sb_edac.c 				ranks = numrank(pvt->info.type, mtr);
pvt              1643 drivers/edac/sb_edac.c 				if (pvt->info.type == KNIGHTS_LANDING) {
pvt              1657 drivers/edac/sb_edac.c 					 pvt->sbridge_dev->mc, pvt->sbridge_dev->dom, i, j,
pvt              1663 drivers/edac/sb_edac.c 				dimm->dtype = pvt->info.get_width(pvt, mtr);
pvt              1668 drivers/edac/sb_edac.c 						 pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom, i, j);
pvt              1678 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              1683 drivers/edac/sb_edac.c 	pvt->sbridge_dev->node_id = pvt->info.get_node_id(pvt);
pvt              1685 drivers/edac/sb_edac.c 		 pvt->sbridge_dev->mc,
pvt              1686 drivers/edac/sb_edac.c 		 pvt->sbridge_dev->node_id,
pvt              1687 drivers/edac/sb_edac.c 		 pvt->sbridge_dev->source_id);
pvt              1692 drivers/edac/sb_edac.c 	if (pvt->info.type == KNIGHTS_LANDING) {
pvt              1694 drivers/edac/sb_edac.c 		pvt->mirror_mode = NON_MIRRORING;
pvt              1695 drivers/edac/sb_edac.c 		pvt->is_cur_addr_mirrored = false;
pvt              1697 drivers/edac/sb_edac.c 		if (knl_get_dimm_capacity(pvt, knl_mc_sizes) != 0)
pvt              1699 drivers/edac/sb_edac.c 		if (pci_read_config_dword(pvt->pci_ta, KNL_MCMTR, &pvt->info.mcmtr)) {
pvt              1704 drivers/edac/sb_edac.c 		if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
pvt              1705 drivers/edac/sb_edac.c 			if (pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg)) {
pvt              1709 drivers/edac/sb_edac.c 			pvt->is_chan_hash = GET_BITFIELD(reg, 21, 21);
pvt              1711 drivers/edac/sb_edac.c 				pvt->mirror_mode = ADDR_RANGE_MIRRORING;
pvt              1716 drivers/edac/sb_edac.c 		if (pci_read_config_dword(pvt->pci_ras, RASENABLES, &reg)) {
pvt              1721 drivers/edac/sb_edac.c 			pvt->mirror_mode = FULL_MIRRORING;
pvt              1724 drivers/edac/sb_edac.c 			pvt->mirror_mode = NON_MIRRORING;
pvt              1729 drivers/edac/sb_edac.c 		if (pci_read_config_dword(pvt->pci_ta, MCMTR, &pvt->info.mcmtr)) {
pvt              1733 drivers/edac/sb_edac.c 		if (IS_LOCKSTEP_ENABLED(pvt->info.mcmtr)) {
pvt              1736 drivers/edac/sb_edac.c 			pvt->is_lockstep = true;
pvt              1740 drivers/edac/sb_edac.c 			pvt->is_lockstep = false;
pvt              1742 drivers/edac/sb_edac.c 		if (IS_CLOSE_PG(pvt->info.mcmtr)) {
pvt              1744 drivers/edac/sb_edac.c 			pvt->is_close_pg = true;
pvt              1747 drivers/edac/sb_edac.c 			pvt->is_close_pg = false;
pvt              1756 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              1768 drivers/edac/sb_edac.c 	pvt->tolm = pvt->info.get_tolm(pvt);
pvt              1769 drivers/edac/sb_edac.c 	tmp_mb = (1 + pvt->tolm) >> 20;
pvt              1773 drivers/edac/sb_edac.c 		gb, (mb*1000)/1024, (u64)pvt->tolm);
pvt              1776 drivers/edac/sb_edac.c 	pvt->tohm = pvt->info.get_tohm(pvt);
pvt              1777 drivers/edac/sb_edac.c 	tmp_mb = (1 + pvt->tohm) >> 20;
pvt              1781 drivers/edac/sb_edac.c 		gb, (mb*1000)/1024, (u64)pvt->tohm);
pvt              1790 drivers/edac/sb_edac.c 	for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
pvt              1792 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
pvt              1794 drivers/edac/sb_edac.c 		limit = pvt->info.sad_limit(reg);
pvt              1806 drivers/edac/sb_edac.c 			 show_dram_attr(pvt->info.dram_attr(reg)),
pvt              1809 drivers/edac/sb_edac.c 			 get_intlv_mode_str(reg, pvt->info.type),
pvt              1813 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
pvt              1815 drivers/edac/sb_edac.c 		sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
pvt              1817 drivers/edac/sb_edac.c 			u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, j);
pvt              1826 drivers/edac/sb_edac.c 	if (pvt->info.type == KNIGHTS_LANDING)
pvt              1834 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_ha, tad_dram_rule[n_tads], &reg);
pvt              1858 drivers/edac/sb_edac.c 		if (!pvt->channel[i].dimms)
pvt              1861 drivers/edac/sb_edac.c 			pci_read_config_dword(pvt->pci_tad[i],
pvt              1878 drivers/edac/sb_edac.c 		if (!pvt->channel[i].dimms)
pvt              1881 drivers/edac/sb_edac.c 			pci_read_config_dword(pvt->pci_tad[i],
pvt              1888 drivers/edac/sb_edac.c 			tmp_mb = pvt->info.rir_limit(reg) >> 20;
pvt              1899 drivers/edac/sb_edac.c 				pci_read_config_dword(pvt->pci_tad[i],
pvt              1902 drivers/edac/sb_edac.c 				tmp_mb = RIR_OFFSET(pvt->info.type, reg) << 6;
pvt              1909 drivers/edac/sb_edac.c 					 (u32)RIR_RNK_TGT(pvt->info.type, reg),
pvt              1935 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              1956 drivers/edac/sb_edac.c 	if ((addr > (u64) pvt->tolm) && (addr < (1LL << 32))) {
pvt              1960 drivers/edac/sb_edac.c 	if (addr >= (u64)pvt->tohm) {
pvt              1968 drivers/edac/sb_edac.c 	for (n_sads = 0; n_sads < pvt->info.max_sad; n_sads++) {
pvt              1969 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_sad0, pvt->info.dram_rule[n_sads],
pvt              1975 drivers/edac/sb_edac.c 		limit = pvt->info.sad_limit(reg);
pvt              1984 drivers/edac/sb_edac.c 	if (n_sads == pvt->info.max_sad) {
pvt              1989 drivers/edac/sb_edac.c 	*area_type = show_dram_attr(pvt->info.dram_attr(dram_rule));
pvt              1990 drivers/edac/sb_edac.c 	interleave_mode = pvt->info.interleave_mode(dram_rule);
pvt              1992 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_sad0, pvt->info.interleave_list[n_sads],
pvt              1995 drivers/edac/sb_edac.c 	if (pvt->info.type == SANDY_BRIDGE) {
pvt              1996 drivers/edac/sb_edac.c 		sad_interl = sad_pkg(pvt->info.interleave_pkg, reg, 0);
pvt              1998 drivers/edac/sb_edac.c 			u32 pkg = sad_pkg(pvt->info.interleave_pkg, reg, sad_way);
pvt              2006 drivers/edac/sb_edac.c 			 pvt->sbridge_dev->mc,
pvt              2035 drivers/edac/sb_edac.c 	} else if (pvt->info.type == HASWELL || pvt->info.type == BROADWELL) {
pvt              2052 drivers/edac/sb_edac.c 		pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
pvt              2058 drivers/edac/sb_edac.c 			pci_read_config_dword(pvt->pci_ha, HASWELL_HASYSDEFEATURE2, &reg);
pvt              2067 drivers/edac/sb_edac.c 		pkg = sad_pkg(pvt->info.interleave_pkg, reg, idx);
pvt              2087 drivers/edac/sb_edac.c 	pvt = mci->pvt_info;
pvt              2093 drivers/edac/sb_edac.c 	pci_ha = pvt->pci_ha;
pvt              2117 drivers/edac/sb_edac.c 		if (pvt->is_chan_hash)
pvt              2144 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_tad[base_ch], tad_ch_nilv_offset[n_tads], &tad_offset);
pvt              2146 drivers/edac/sb_edac.c 	if (pvt->mirror_mode == FULL_MIRRORING ||
pvt              2147 drivers/edac/sb_edac.c 	    (pvt->mirror_mode == ADDR_RANGE_MIRRORING && n_tads == 0)) {
pvt              2159 drivers/edac/sb_edac.c 		pvt->is_cur_addr_mirrored = true;
pvt              2162 drivers/edac/sb_edac.c 		pvt->is_cur_addr_mirrored = false;
pvt              2165 drivers/edac/sb_edac.c 	if (pvt->is_lockstep)
pvt              2200 drivers/edac/sb_edac.c 		pci_read_config_dword(pvt->pci_tad[base_ch], rir_way_limit[n_rir], &reg);
pvt              2205 drivers/edac/sb_edac.c 		limit = pvt->info.rir_limit(reg);
pvt              2222 drivers/edac/sb_edac.c 	if (pvt->is_close_pg)
pvt              2228 drivers/edac/sb_edac.c 	pci_read_config_dword(pvt->pci_tad[base_ch], rir_offset[n_rir][idx], &reg);
pvt              2229 drivers/edac/sb_edac.c 	*rank = RIR_RNK_TGT(pvt->info.type, reg);
pvt              2248 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt;
pvt              2257 drivers/edac/sb_edac.c 	pvt = mci->pvt_info;
pvt              2258 drivers/edac/sb_edac.c 	if (!pvt->info.get_ha) {
pvt              2262 drivers/edac/sb_edac.c 	*ha = pvt->info.get_ha(m->bank);
pvt              2275 drivers/edac/sb_edac.c 	pvt = new_mci->pvt_info;
pvt              2276 drivers/edac/sb_edac.c 	pci_ha = pvt->pci_ha;
pvt              2281 drivers/edac/sb_edac.c 	if (pvt->mirror_mode == FULL_MIRRORING ||
pvt              2282 drivers/edac/sb_edac.c 	    (pvt->mirror_mode == ADDR_RANGE_MIRRORING && tad0)) {
pvt              2284 drivers/edac/sb_edac.c 		pvt->is_cur_addr_mirrored = true;
pvt              2286 drivers/edac/sb_edac.c 		pvt->is_cur_addr_mirrored = false;
pvt              2289 drivers/edac/sb_edac.c 	if (pvt->is_lockstep)
pvt              2491 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              2503 drivers/edac/sb_edac.c 			pvt->pci_sad0 = pdev;
pvt              2506 drivers/edac/sb_edac.c 			pvt->pci_sad1 = pdev;
pvt              2509 drivers/edac/sb_edac.c 			pvt->pci_br0 = pdev;
pvt              2512 drivers/edac/sb_edac.c 			pvt->pci_ha = pdev;
pvt              2515 drivers/edac/sb_edac.c 			pvt->pci_ta = pdev;
pvt              2518 drivers/edac/sb_edac.c 			pvt->pci_ras = pdev;
pvt              2526 drivers/edac/sb_edac.c 			pvt->pci_tad[id] = pdev;
pvt              2531 drivers/edac/sb_edac.c 			pvt->pci_ddrio = pdev;
pvt              2544 drivers/edac/sb_edac.c 	if (!pvt->pci_sad0 || !pvt->pci_sad1 || !pvt->pci_ha ||
pvt              2545 drivers/edac/sb_edac.c 	    !pvt->pci_ras || !pvt->pci_ta)
pvt              2565 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              2578 drivers/edac/sb_edac.c 			pvt->pci_ha = pdev;
pvt              2582 drivers/edac/sb_edac.c 			pvt->pci_ta = pdev;
pvt              2586 drivers/edac/sb_edac.c 			pvt->pci_ras = pdev;
pvt              2598 drivers/edac/sb_edac.c 			pvt->pci_tad[id] = pdev;
pvt              2603 drivers/edac/sb_edac.c 			pvt->pci_ddrio = pdev;
pvt              2606 drivers/edac/sb_edac.c 			pvt->pci_ddrio = pdev;
pvt              2609 drivers/edac/sb_edac.c 			pvt->pci_sad0 = pdev;
pvt              2612 drivers/edac/sb_edac.c 			pvt->pci_br0 = pdev;
pvt              2615 drivers/edac/sb_edac.c 			pvt->pci_br1 = pdev;
pvt              2628 drivers/edac/sb_edac.c 	if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_br0 ||
pvt              2629 drivers/edac/sb_edac.c 	    !pvt->pci_br1 || !pvt->pci_ras || !pvt->pci_ta)
pvt              2651 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              2657 drivers/edac/sb_edac.c 	if (pvt->info.pci_vtd == NULL)
pvt              2659 drivers/edac/sb_edac.c 		pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
pvt              2670 drivers/edac/sb_edac.c 			pvt->pci_sad0 = pdev;
pvt              2673 drivers/edac/sb_edac.c 			pvt->pci_sad1 = pdev;
pvt              2677 drivers/edac/sb_edac.c 			pvt->pci_ha = pdev;
pvt              2681 drivers/edac/sb_edac.c 			pvt->pci_ta = pdev;
pvt              2685 drivers/edac/sb_edac.c 			pvt->pci_ras = pdev;
pvt              2697 drivers/edac/sb_edac.c 			pvt->pci_tad[id] = pdev;
pvt              2705 drivers/edac/sb_edac.c 			if (!pvt->pci_ddrio)
pvt              2706 drivers/edac/sb_edac.c 				pvt->pci_ddrio = pdev;
pvt              2719 drivers/edac/sb_edac.c 	if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
pvt              2720 drivers/edac/sb_edac.c 	    !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
pvt              2736 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              2742 drivers/edac/sb_edac.c 	if (pvt->info.pci_vtd == NULL)
pvt              2744 drivers/edac/sb_edac.c 		pvt->info.pci_vtd = pci_get_device(PCI_VENDOR_ID_INTEL,
pvt              2755 drivers/edac/sb_edac.c 			pvt->pci_sad0 = pdev;
pvt              2758 drivers/edac/sb_edac.c 			pvt->pci_sad1 = pdev;
pvt              2762 drivers/edac/sb_edac.c 			pvt->pci_ha = pdev;
pvt              2766 drivers/edac/sb_edac.c 			pvt->pci_ta = pdev;
pvt              2770 drivers/edac/sb_edac.c 			pvt->pci_ras = pdev;
pvt              2782 drivers/edac/sb_edac.c 			pvt->pci_tad[id] = pdev;
pvt              2787 drivers/edac/sb_edac.c 			pvt->pci_ddrio = pdev;
pvt              2800 drivers/edac/sb_edac.c 	if (!pvt->pci_sad0 || !pvt->pci_ha || !pvt->pci_sad1 ||
pvt              2801 drivers/edac/sb_edac.c 	    !pvt->pci_ras  || !pvt->pci_ta || !pvt->info.pci_vtd)
pvt              2817 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              2836 drivers/edac/sb_edac.c 				pvt->knl.pci_mc0 = pdev;
pvt              2838 drivers/edac/sb_edac.c 				pvt->knl.pci_mc1 = pdev;
pvt              2848 drivers/edac/sb_edac.c 			pvt->pci_sad0 = pdev;
pvt              2852 drivers/edac/sb_edac.c 			pvt->pci_sad1 = pdev;
pvt              2868 drivers/edac/sb_edac.c 			WARN_ON(pvt->knl.pci_cha[devidx] != NULL);
pvt              2870 drivers/edac/sb_edac.c 			pvt->knl.pci_cha[devidx] = pdev;
pvt              2893 drivers/edac/sb_edac.c 			WARN_ON(pvt->knl.pci_channel[devidx] != NULL);
pvt              2894 drivers/edac/sb_edac.c 			pvt->knl.pci_channel[devidx] = pdev;
pvt              2898 drivers/edac/sb_edac.c 			pvt->knl.pci_mc_info = pdev;
pvt              2902 drivers/edac/sb_edac.c 			pvt->pci_ta = pdev;
pvt              2912 drivers/edac/sb_edac.c 	if (!pvt->knl.pci_mc0  || !pvt->knl.pci_mc1 ||
pvt              2913 drivers/edac/sb_edac.c 	    !pvt->pci_sad0     || !pvt->pci_sad1    ||
pvt              2914 drivers/edac/sb_edac.c 	    !pvt->pci_ta) {
pvt              2919 drivers/edac/sb_edac.c 		if (!pvt->knl.pci_channel[i]) {
pvt              2926 drivers/edac/sb_edac.c 		if (!pvt->knl.pci_cha[i]) {
pvt              2953 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt = mci->pvt_info;
pvt              2976 drivers/edac/sb_edac.c 	if (pvt->info.type != SANDY_BRIDGE)
pvt              3027 drivers/edac/sb_edac.c 	if (pvt->info.type == KNIGHTS_LANDING) {
pvt              3076 drivers/edac/sb_edac.c 	pvt = mci->pvt_info;
pvt              3095 drivers/edac/sb_edac.c 	if (!pvt->is_lockstep && !pvt->is_cur_addr_mirrored && !pvt->is_close_pg)
pvt              3203 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt;
pvt              3212 drivers/edac/sb_edac.c 	pvt = mci->pvt_info;
pvt              3230 drivers/edac/sb_edac.c 	struct sbridge_pvt *pvt;
pvt              3243 drivers/edac/sb_edac.c 			    sizeof(*pvt));
pvt              3251 drivers/edac/sb_edac.c 	pvt = mci->pvt_info;
pvt              3252 drivers/edac/sb_edac.c 	memset(pvt, 0, sizeof(*pvt));
pvt              3255 drivers/edac/sb_edac.c 	pvt->sbridge_dev = sbridge_dev;
pvt              3266 drivers/edac/sb_edac.c 	pvt->info.type = type;
pvt              3269 drivers/edac/sb_edac.c 		pvt->info.rankcfgr = IB_RANK_CFG_A;
pvt              3270 drivers/edac/sb_edac.c 		pvt->info.get_tolm = ibridge_get_tolm;
pvt              3271 drivers/edac/sb_edac.c 		pvt->info.get_tohm = ibridge_get_tohm;
pvt              3272 drivers/edac/sb_edac.c 		pvt->info.dram_rule = ibridge_dram_rule;
pvt              3273 drivers/edac/sb_edac.c 		pvt->info.get_memory_type = get_memory_type;
pvt              3274 drivers/edac/sb_edac.c 		pvt->info.get_node_id = get_node_id;
pvt              3275 drivers/edac/sb_edac.c 		pvt->info.get_ha = ibridge_get_ha;
pvt              3276 drivers/edac/sb_edac.c 		pvt->info.rir_limit = rir_limit;
pvt              3277 drivers/edac/sb_edac.c 		pvt->info.sad_limit = sad_limit;
pvt              3278 drivers/edac/sb_edac.c 		pvt->info.interleave_mode = interleave_mode;
pvt              3279 drivers/edac/sb_edac.c 		pvt->info.dram_attr = dram_attr;
pvt              3280 drivers/edac/sb_edac.c 		pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
pvt              3281 drivers/edac/sb_edac.c 		pvt->info.interleave_list = ibridge_interleave_list;
pvt              3282 drivers/edac/sb_edac.c 		pvt->info.interleave_pkg = ibridge_interleave_pkg;
pvt              3283 drivers/edac/sb_edac.c 		pvt->info.get_width = ibridge_get_width;
pvt              3291 drivers/edac/sb_edac.c 			pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
pvt              3294 drivers/edac/sb_edac.c 		pvt->info.rankcfgr = SB_RANK_CFG_A;
pvt              3295 drivers/edac/sb_edac.c 		pvt->info.get_tolm = sbridge_get_tolm;
pvt              3296 drivers/edac/sb_edac.c 		pvt->info.get_tohm = sbridge_get_tohm;
pvt              3297 drivers/edac/sb_edac.c 		pvt->info.dram_rule = sbridge_dram_rule;
pvt              3298 drivers/edac/sb_edac.c 		pvt->info.get_memory_type = get_memory_type;
pvt              3299 drivers/edac/sb_edac.c 		pvt->info.get_node_id = get_node_id;
pvt              3300 drivers/edac/sb_edac.c 		pvt->info.get_ha = sbridge_get_ha;
pvt              3301 drivers/edac/sb_edac.c 		pvt->info.rir_limit = rir_limit;
pvt              3302 drivers/edac/sb_edac.c 		pvt->info.sad_limit = sad_limit;
pvt              3303 drivers/edac/sb_edac.c 		pvt->info.interleave_mode = interleave_mode;
pvt              3304 drivers/edac/sb_edac.c 		pvt->info.dram_attr = dram_attr;
pvt              3305 drivers/edac/sb_edac.c 		pvt->info.max_sad = ARRAY_SIZE(sbridge_dram_rule);
pvt              3306 drivers/edac/sb_edac.c 		pvt->info.interleave_list = sbridge_interleave_list;
pvt              3307 drivers/edac/sb_edac.c 		pvt->info.interleave_pkg = sbridge_interleave_pkg;
pvt              3308 drivers/edac/sb_edac.c 		pvt->info.get_width = sbridge_get_width;
pvt              3316 drivers/edac/sb_edac.c 			pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
pvt              3320 drivers/edac/sb_edac.c 		pvt->info.get_tolm = haswell_get_tolm;
pvt              3321 drivers/edac/sb_edac.c 		pvt->info.get_tohm = haswell_get_tohm;
pvt              3322 drivers/edac/sb_edac.c 		pvt->info.dram_rule = ibridge_dram_rule;
pvt              3323 drivers/edac/sb_edac.c 		pvt->info.get_memory_type = haswell_get_memory_type;
pvt              3324 drivers/edac/sb_edac.c 		pvt->info.get_node_id = haswell_get_node_id;
pvt              3325 drivers/edac/sb_edac.c 		pvt->info.get_ha = ibridge_get_ha;
pvt              3326 drivers/edac/sb_edac.c 		pvt->info.rir_limit = haswell_rir_limit;
pvt              3327 drivers/edac/sb_edac.c 		pvt->info.sad_limit = sad_limit;
pvt              3328 drivers/edac/sb_edac.c 		pvt->info.interleave_mode = interleave_mode;
pvt              3329 drivers/edac/sb_edac.c 		pvt->info.dram_attr = dram_attr;
pvt              3330 drivers/edac/sb_edac.c 		pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
pvt              3331 drivers/edac/sb_edac.c 		pvt->info.interleave_list = ibridge_interleave_list;
pvt              3332 drivers/edac/sb_edac.c 		pvt->info.interleave_pkg = ibridge_interleave_pkg;
pvt              3333 drivers/edac/sb_edac.c 		pvt->info.get_width = ibridge_get_width;
pvt              3341 drivers/edac/sb_edac.c 			pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
pvt              3345 drivers/edac/sb_edac.c 		pvt->info.get_tolm = haswell_get_tolm;
pvt              3346 drivers/edac/sb_edac.c 		pvt->info.get_tohm = haswell_get_tohm;
pvt              3347 drivers/edac/sb_edac.c 		pvt->info.dram_rule = ibridge_dram_rule;
pvt              3348 drivers/edac/sb_edac.c 		pvt->info.get_memory_type = haswell_get_memory_type;
pvt              3349 drivers/edac/sb_edac.c 		pvt->info.get_node_id = haswell_get_node_id;
pvt              3350 drivers/edac/sb_edac.c 		pvt->info.get_ha = ibridge_get_ha;
pvt              3351 drivers/edac/sb_edac.c 		pvt->info.rir_limit = haswell_rir_limit;
pvt              3352 drivers/edac/sb_edac.c 		pvt->info.sad_limit = sad_limit;
pvt              3353 drivers/edac/sb_edac.c 		pvt->info.interleave_mode = interleave_mode;
pvt              3354 drivers/edac/sb_edac.c 		pvt->info.dram_attr = dram_attr;
pvt              3355 drivers/edac/sb_edac.c 		pvt->info.max_sad = ARRAY_SIZE(ibridge_dram_rule);
pvt              3356 drivers/edac/sb_edac.c 		pvt->info.interleave_list = ibridge_interleave_list;
pvt              3357 drivers/edac/sb_edac.c 		pvt->info.interleave_pkg = ibridge_interleave_pkg;
pvt              3358 drivers/edac/sb_edac.c 		pvt->info.get_width = broadwell_get_width;
pvt              3366 drivers/edac/sb_edac.c 			pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
pvt              3370 drivers/edac/sb_edac.c 		pvt->info.get_tolm = knl_get_tolm;
pvt              3371 drivers/edac/sb_edac.c 		pvt->info.get_tohm = knl_get_tohm;
pvt              3372 drivers/edac/sb_edac.c 		pvt->info.dram_rule = knl_dram_rule;
pvt              3373 drivers/edac/sb_edac.c 		pvt->info.get_memory_type = knl_get_memory_type;
pvt              3374 drivers/edac/sb_edac.c 		pvt->info.get_node_id = knl_get_node_id;
pvt              3375 drivers/edac/sb_edac.c 		pvt->info.get_ha = knl_get_ha;
pvt              3376 drivers/edac/sb_edac.c 		pvt->info.rir_limit = NULL;
pvt              3377 drivers/edac/sb_edac.c 		pvt->info.sad_limit = knl_sad_limit;
pvt              3378 drivers/edac/sb_edac.c 		pvt->info.interleave_mode = knl_interleave_mode;
pvt              3379 drivers/edac/sb_edac.c 		pvt->info.dram_attr = dram_attr_knl;
pvt              3380 drivers/edac/sb_edac.c 		pvt->info.max_sad = ARRAY_SIZE(knl_dram_rule);
pvt              3381 drivers/edac/sb_edac.c 		pvt->info.interleave_list = knl_interleave_list;
pvt              3382 drivers/edac/sb_edac.c 		pvt->info.interleave_pkg = ibridge_interleave_pkg;
pvt              3383 drivers/edac/sb_edac.c 		pvt->info.get_width = knl_get_width;
pvt              3390 drivers/edac/sb_edac.c 			pvt->sbridge_dev->source_id, pvt->sbridge_dev->dom);
pvt               161 drivers/edac/skx_base.c 	struct skx_pvt *pvt = mci->pvt_info;
pvt               163 drivers/edac/skx_base.c 	struct skx_imc *imc = pvt->imc;
pvt               377 drivers/edac/skx_common.c 	struct skx_pvt *pvt;
pvt               397 drivers/edac/skx_common.c 	pvt = mci->pvt_info;
pvt               398 drivers/edac/skx_common.c 	pvt->imc = imc;
pvt              4191 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4233 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4255 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4298 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4320 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4343 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4366 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4389 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4411 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4434 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4477 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4500 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4522 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4573 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4619 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4643 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4690 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4713 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4735 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4758 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4781 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt              4804 drivers/net/dsa/mv88e6xxx/chip.c 		.pvt = true,
pvt               108 drivers/net/dsa/mv88e6xxx/chip.h 	bool pvt;
pvt               604 drivers/net/dsa/mv88e6xxx/chip.h 	return chip->info->pvt;
pvt               182 drivers/s390/crypto/zcrypt_cca_key.h 		struct cca_pvt_ext_CRT_sec pvt;
pvt               214 drivers/s390/crypto/zcrypt_cca_key.h 	key->pvt.section_identifier = CCA_PVT_EXT_CRT_SEC_ID_PVT;
pvt               215 drivers/s390/crypto/zcrypt_cca_key.h 	key->pvt.section_length = sizeof(key->pvt) + key_len;
pvt               216 drivers/s390/crypto/zcrypt_cca_key.h 	key->pvt.key_format = CCA_PVT_EXT_CRT_SEC_FMT_CL;
pvt               217 drivers/s390/crypto/zcrypt_cca_key.h 	key->pvt.key_use_flags[0] = CCA_PVT_USAGE_ALL;
pvt               218 drivers/s390/crypto/zcrypt_cca_key.h 	key->pvt.p_len = key->pvt.dp_len = key->pvt.u_len = long_len;
pvt               219 drivers/s390/crypto/zcrypt_cca_key.h 	key->pvt.q_len = key->pvt.dq_len = short_len;
pvt               220 drivers/s390/crypto/zcrypt_cca_key.h 	key->pvt.mod_len = crt->inputdatalength;
pvt               221 drivers/s390/crypto/zcrypt_cca_key.h 	key->pvt.pad_len = pad_len;
pvt                72 sound/pci/asihpi/hpidspcd.c 	dsp_code->pvt = kmalloc(sizeof(*dsp_code->pvt), GFP_KERNEL);
pvt                73 sound/pci/asihpi/hpidspcd.c 	if (!dsp_code->pvt) {
pvt                78 sound/pci/asihpi/hpidspcd.c 	dsp_code->pvt->dev = dev;
pvt                79 sound/pci/asihpi/hpidspcd.c 	dsp_code->pvt->firmware = firmware;
pvt                96 sound/pci/asihpi/hpidspcd.c 	release_firmware(dsp_code->pvt->firmware);
pvt                97 sound/pci/asihpi/hpidspcd.c 	kfree(dsp_code->pvt);
pvt               113 sound/pci/asihpi/hpidspcd.c 	*pword = ((u32 *)(dsp_code->pvt->firmware->data))[dsp_code->
pvt               127 sound/pci/asihpi/hpidspcd.c 		((u32 *)(dsp_code->pvt->firmware->data)) +
pvt                54 sound/pci/asihpi/hpidspcd.h 	struct dsp_code_private *pvt;