ptei             2472 arch/mips/mm/tlbex.c 	unsigned long pwfield, pwsize, ptei;
ptei             2496 arch/mips/mm/tlbex.c 	ptei = _PAGE_GLOBAL_SHIFT << MIPS_PWFIELD_PTEI_SHIFT;
ptei             2497 arch/mips/mm/tlbex.c 	pwfield |= ptei;
ptei             2503 arch/mips/mm/tlbex.c 		!= ptei) {
ptei             2505 arch/mips/mm/tlbex.c 			ptei);
ptei              198 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		     const struct nvkm_vmm_desc *desc, u32 ptei, u32 ptes)
ptei              204 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	u32 spti = ptei & (sptn - 1), lpti, pteb;
ptei              209 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	for (lpti = ptei >> sptb; ptes; spti = 0, lpti++) {
ptei              219 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	for (ptei = pteb = ptei >> sptb; ptei < lpti; pteb = ptei) {
ptei              222 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			for (ptes = 1, ptei++; ptei < lpti; ptes++, ptei++) {
ptei              223 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 				if (!(pgt->pte[ptei] & NVKM_VMM_PTE_SPTES))
ptei              235 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		pgt->pte[ptei] &= ~NVKM_VMM_PTE_VALID;
ptei              236 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		for (ptes = 1, ptei++; ptei < lpti; ptes++, ptei++) {
ptei              237 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			if (pgt->pte[ptei] & NVKM_VMM_PTE_SPTES)
ptei              239 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			pgt->pte[ptei] &= ~NVKM_VMM_PTE_VALID;
ptei              258 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c nvkm_vmm_unref_ptes(struct nvkm_vmm_iter *it, bool pfn, u32 ptei, u32 ptes)
ptei              267 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		dma = desc->func->pfn_clear(it->vmm, pgt->pt[type], ptei, ptes);
ptei              272 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			desc->func->pfn_unmap(it->vmm, pgt->pt[type], ptei, ptes);
ptei              281 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		nvkm_vmm_unref_sptes(it, pgt, desc, ptei, ptes);
ptei              297 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		   const struct nvkm_vmm_desc *desc, u32 ptei, u32 ptes)
ptei              303 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	u32 spti = ptei & (sptn - 1), lpti, pteb;
ptei              308 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	for (lpti = ptei >> sptb; ptes; spti = 0, lpti++) {
ptei              318 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	for (ptei = pteb = ptei >> sptb; ptei < lpti; pteb = ptei) {
ptei              321 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			for (ptes = 1, ptei++; ptei < lpti; ptes++, ptei++) {
ptei              322 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 				if (!(pgt->pte[ptei] & NVKM_VMM_PTE_VALID))
ptei              334 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		pgt->pte[ptei] |= NVKM_VMM_PTE_VALID;
ptei              335 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		for (ptes = 1, ptei++; ptei < lpti; ptes++, ptei++) {
ptei              336 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			if (pgt->pte[ptei] & NVKM_VMM_PTE_VALID)
ptei              338 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			pgt->pte[ptei] |= NVKM_VMM_PTE_VALID;
ptei              364 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c nvkm_vmm_ref_ptes(struct nvkm_vmm_iter *it, bool pfn, u32 ptei, u32 ptes)
ptei              375 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		nvkm_vmm_ref_sptes(it, pgt, desc, ptei, ptes);
ptei              382 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		     struct nvkm_vmm_pt *pgt, u32 ptei, u32 ptes)
ptei              386 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			pgt->pde[ptei++] = NVKM_VMM_PDE_SPARSE;
ptei              389 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		memset(&pgt->pte[ptei], NVKM_VMM_PTE_SPARSE, ptes);
ptei              394 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c nvkm_vmm_sparse_unref_ptes(struct nvkm_vmm_iter *it, bool pfn, u32 ptei, u32 ptes)
ptei              398 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		memset(&pt->pde[ptei], 0x00, sizeof(pt->pde[0]) * ptes);
ptei              401 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		memset(&pt->pte[ptei], 0x00, sizeof(pt->pte[0]) * ptes);
ptei              402 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	return nvkm_vmm_unref_ptes(it, pfn, ptei, ptes);
ptei              406 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c nvkm_vmm_sparse_ref_ptes(struct nvkm_vmm_iter *it, bool pfn, u32 ptei, u32 ptes)
ptei              408 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	nvkm_vmm_sparse_ptes(it->desc, it->pt[0], ptei, ptes);
ptei              409 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	return nvkm_vmm_ref_ptes(it, pfn, ptei, ptes);
ptei              423 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 	u32 pteb, ptei, ptes;
ptei              447 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		for (ptei = pteb = 0; ptei < pten; pteb = ptei) {
ptei              448 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			bool spte = pgt->pte[ptei] & NVKM_VMM_PTE_SPTES;
ptei              449 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 			for (ptes = 1, ptei++; ptei < pten; ptes++, ptei++) {
ptei              450 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 				bool next = pgt->pte[ptei] & NVKM_VMM_PTE_SPTES;
ptei              535 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		const u32 ptei = it.pte[0];
ptei              536 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		const u32 ptes = min_t(u64, it.cnt, pten - ptei);
ptei              563 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 		if (!REF_PTES || REF_PTES(&it, pfn, ptei, ptes)) {
ptei              567 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 					MAP_PTES(vmm, pt, ptei, ptes, map);
ptei              569 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c 					CLR_PTES(vmm, pt, ptei, ptes);
ptei             1806 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c nvkm_vmm_boot_ptes(struct nvkm_vmm_iter *it, bool pfn, u32 ptei, u32 ptes)
ptei               54 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h 				  struct nvkm_mmu_pt *, u32 ptei, u32 ptes);
ptei               58 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h 				  u32 ptei, u32 ptes, struct nvkm_vmm_map *);
ptei               72 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h 	bool (*pfn_clear)(struct nvkm_vmm *, struct nvkm_mmu_pt *, u32 ptei, u32 ptes);
ptei               33 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
ptei               44 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 			VMM_WO064(pt, vmm, ptei++ * 8, data);
ptei               51 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 			VMM_WO064(pt, vmm, ptei++ * 8, data);
ptei               59 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               61 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 	VMM_MAP_ITER_SGL(vmm, pt, ptei, ptes, map, gf100_vmm_pgt_pte);
ptei               66 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               69 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		VMM_SPAM(vmm, "DMAA %08x %08x PTE(s)", ptei, ptes);
ptei               73 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 			VMM_WO064(pt, vmm, ptei++ * 8, data);
ptei               80 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 	VMM_MAP_ITER_DMA(vmm, pt, ptei, ptes, map, gf100_vmm_pgt_pte);
ptei               85 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               87 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 	VMM_MAP_ITER_MEM(vmm, pt, ptei, ptes, map, gf100_vmm_pgt_pte);
ptei               92 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 		    struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei               94 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.c 	VMM_FO064(pt, vmm, ptei * 8, 0ULL, ptes);
ptei               26 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c 		      struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei               29 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.c 	VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(1) /* PRIV. */, ptes);
ptei               29 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c 		     struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei               32 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.c 	VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(32) /* VOL. */, ptes);
ptei               35 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		    struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei               42 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 0);
ptei               43 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 4);
ptei               49 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		ptei++;
ptei               56 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		    struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei               61 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		u32 datalo = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 0);
ptei               62 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		u32 datahi = nvkm_ro32(pt->memory, pt->base + ptei * 8 + 4);
ptei               65 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 			VMM_WO064(pt, vmm, ptei * 8, data & ~BIT_ULL(0));
ptei               68 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		ptei++;
ptei               76 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei              102 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		VMM_WO064(pt, vmm, ptei++ * 8, data);
ptei              110 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
ptei              117 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		VMM_WO064(pt, vmm, ptei++ * 8, data);
ptei              124 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei              126 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	VMM_MAP_ITER_SGL(vmm, pt, ptei, ptes, map, gp100_vmm_pgt_pte);
ptei              131 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei              134 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		VMM_SPAM(vmm, "DMAA %08x %08x PTE(s)", ptei, ptes);
ptei              138 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 			VMM_WO064(pt, vmm, ptei++ * 8, data);
ptei              145 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	VMM_MAP_ITER_DMA(vmm, pt, ptei, ptes, map, gp100_vmm_pgt_pte);
ptei              150 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei              152 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	VMM_MAP_ITER_MEM(vmm, pt, ptei, ptes, map, gp100_vmm_pgt_pte);
ptei              157 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		     struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei              160 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(3) /* VOL. */, ptes);
ptei              177 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		      struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei              180 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	VMM_FO064(pt, vmm, ptei * 8, BIT_ULL(5) /* PRIV. */, ptes);
ptei              193 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
ptei              200 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		VMM_WO128(pt, vmm, ptei++ * 0x10, data, 0ULL);
ptei              207 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 		  u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei              209 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.c 	VMM_MAP_ITER_MEM(vmm, pt, ptei, ptes, map, gp100_vmm_pd0_pte);
ptei               29 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
ptei               33 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c 		VMM_WO032(pt, vmm, 8 + ptei++ * 4, data);
ptei               40 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               42 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c 	VMM_MAP_ITER_SGL(vmm, pt, ptei, ptes, map, nv04_vmm_pgt_pte);
ptei               47 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               52 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c 		VMM_WO032(pt, vmm, 8 + (ptei++ * 4), *map->dma++ | 0x00000003);
ptei               55 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c 	VMM_MAP_ITER_DMA(vmm, pt, ptei, ptes, map, nv04_vmm_pgt_pte);
ptei               61 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c 		   struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei               63 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.c 	VMM_FO032(pt, vmm, 8 + (ptei * 4), 0, ptes);
ptei               28 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
ptei               32 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c 		VMM_WO032(pt, vmm, ptei++ * 4, data);
ptei               39 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               41 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c 	VMM_MAP_ITER_SGL(vmm, pt, ptei, ptes, map, nv41_vmm_pgt_pte);
ptei               46 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               52 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c 		VMM_WO032(pt, vmm, ptei++ * 4, data);
ptei               56 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c 	VMM_MAP_ITER_DMA(vmm, pt, ptei, ptes, map, nv41_vmm_pgt_pte);
ptei               62 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c 		   struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei               64 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.c 	VMM_FO032(pt, vmm, ptei * 4, 0, ptes);
ptei               28 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		  dma_addr_t *list, u32 ptei, u32 ptes)
ptei               30 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 	u32 pteo = (ptei << 2) & ~0x0000000f;
ptei               40 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		switch (ptei++ & 0x3) {
ptei               74 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
ptei               78 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 	if (ptei & 3) {
ptei               79 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		const u32 pten = min(ptes, 4 - (ptei & 3));
ptei               82 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		nv44_vmm_pgt_fill(vmm, pt, tmp, ptei, pten);
ptei               83 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		ptei += pten;
ptei               90 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, tmp[0] >>  0 | tmp[1] << 27);
ptei               91 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, tmp[1] >>  5 | tmp[2] << 22);
ptei               92 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, tmp[2] >> 10 | tmp[3] << 17);
ptei               93 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, tmp[3] >> 15 | 0x40000000);
ptei              100 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		nv44_vmm_pgt_fill(vmm, pt, tmp, ptei, ptes);
ptei              106 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei              108 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 	VMM_MAP_ITER_SGL(vmm, pt, ptei, ptes, map, nv44_vmm_pgt_pte);
ptei              113 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei              117 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 	if (ptei & 3) {
ptei              118 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		const u32 pten = min(ptes, 4 - (ptei & 3));
ptei              119 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		nv44_vmm_pgt_fill(vmm, pt, map->dma, ptei, pten);
ptei              120 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		ptei += pten;
ptei              129 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, tmp[0] >>  0 | tmp[1] << 27);
ptei              130 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, tmp[1] >>  5 | tmp[2] << 22);
ptei              131 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, tmp[2] >> 10 | tmp[3] << 17);
ptei              132 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, tmp[3] >> 15 | 0x40000000);
ptei              137 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		nv44_vmm_pgt_fill(vmm, pt, map->dma, ptei, ptes);
ptei              142 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 	VMM_MAP_ITER_DMA(vmm, pt, ptei, ptes, map, nv44_vmm_pgt_pte);
ptei              148 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		   struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei              151 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 	if (ptei & 3) {
ptei              152 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		const u32 pten = min(ptes, 4 - (ptei & 3));
ptei              153 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		nv44_vmm_pgt_fill(vmm, pt, NULL, ptei, pten);
ptei              154 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		ptei += pten;
ptei              159 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000);
ptei              160 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000);
ptei              161 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000);
ptei              162 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		VMM_WO032(pt, vmm, ptei++ * 4, 0x00000000);
ptei              167 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.c 		nv44_vmm_pgt_fill(vmm, pt, NULL, ptei, ptes);
ptei               33 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map, u64 addr)
ptei               44 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 			if (ptes >= pten && IS_ALIGNED(ptei, pten))
ptei               53 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 			VMM_WO064(pt, vmm, ptei++ * 8, data);
ptei               59 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               61 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 	VMM_MAP_ITER_SGL(vmm, pt, ptei, ptes, map, nv50_vmm_pgt_pte);
ptei               66 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               69 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		VMM_SPAM(vmm, "DMAA %08x %08x PTE(s)", ptei, ptes);
ptei               73 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 			VMM_WO064(pt, vmm, ptei++ * 8, data);
ptei               80 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 	VMM_MAP_ITER_DMA(vmm, pt, ptei, ptes, map, nv50_vmm_pgt_pte);
ptei               85 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		 u32 ptei, u32 ptes, struct nvkm_vmm_map *map)
ptei               87 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 	VMM_MAP_ITER_MEM(vmm, pt, ptei, ptes, map, nv50_vmm_pgt_pte);
ptei               92 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 		   struct nvkm_mmu_pt *pt, u32 ptei, u32 ptes)
ptei               94 drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.c 	VMM_FO064(pt, vmm, ptei * 8, 0ULL, ptes);
ptei             1860 drivers/isdn/mISDN/layer2.c 	int	psapi, ptei;
ptei             1871 drivers/isdn/mISDN/layer2.c 		ptei = *datap++;
ptei             1872 drivers/isdn/mISDN/layer2.c 		if ((psapi & 1) || !(ptei & 1)) {
ptei             1879 drivers/isdn/mISDN/layer2.c 		ptei >>= 1;
ptei             1889 drivers/isdn/mISDN/layer2.c 		if ((ptei != l2->tei) && (ptei != GROUP_TEI)) {
ptei             1893 drivers/isdn/mISDN/layer2.c 				       mISDNDevName4ch(&l2->ch), ptei, l2->tei);