pte_row_height_linear  563 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
pte_row_height_linear  572 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
pte_row_height_linear 1034 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
pte_row_height_linear 1044 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
pte_row_height_linear  178 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
pte_row_height_linear  181 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer.c 				rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
pte_row_height_linear  217 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_l.pte_row_height_linear, rq_regs->rq_regs_c.chunk_size, rq_regs->rq_regs_c.min_chunk_size,
pte_row_height_linear  220 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_hw_sequencer_debug.c 				rq_regs->rq_regs_c.swath_height, rq_regs->rq_regs_c.pte_row_height_linear);
pte_row_height_linear  211 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
pte_row_height_linear  220 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
pte_row_height_linear 1232 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		PTE_ROW_HEIGHT_LINEAR, &rq_regs->rq_regs_l.pte_row_height_linear);
pte_row_height_linear 1242 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, &rq_regs->rq_regs_c.pte_row_height_linear);
pte_row_height_linear  137 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		PTE_ROW_HEIGHT_LINEAR, rq_regs->rq_regs_l.pte_row_height_linear);
pte_row_height_linear  145 drivers/gpu/drm/amd/display/dc/dcn21/dcn21_hubp.c 		PTE_ROW_HEIGHT_LINEAR_C, rq_regs->rq_regs_c.pte_row_height_linear);
pte_row_height_linear  198 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
pte_row_height_linear  203 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20.c 		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
pte_row_height_linear  198 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_l.dpte_row_height),
pte_row_height_linear  203 drivers/gpu/drm/amd/display/dc/dml/dcn20/display_rq_dlg_calc_20v2.c 		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(dml_log2(rq_param.dlg.rq_c.dpte_row_height),
pte_row_height_linear  177 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 	rq_regs->rq_regs_l.pte_row_height_linear = dml_floor(
pte_row_height_linear  183 drivers/gpu/drm/amd/display/dc/dml/dcn21/display_rq_dlg_calc_21.c 		rq_regs->rq_regs_c.pte_row_height_linear = dml_floor(
pte_row_height_linear  491 drivers/gpu/drm/amd/display/dc/dml/display_mode_structs.h 	unsigned int pte_row_height_linear;
pte_row_height_linear  174 drivers/gpu/drm/amd/display/dc/dml/display_rq_dlg_helpers.c 			rq_regs.pte_row_height_linear);