pt_base 1305 arch/x86/xen/enlighten_pv.c xen_setup_kernel_pagetable((pgd_t *)xen_start_info->pt_base, pt_base 1270 arch/x86/xen/mmu_pv.c addr = xen_start_info->pt_base; pt_base 1274 arch/x86/xen/mmu_pv.c xen_start_info->pt_base = (unsigned long)__va(__pa(xen_start_info->pt_base)); pt_base 1851 arch/x86/xen/mmu_pv.c static void __init check_pt_base(unsigned long *pt_base, unsigned long *pt_end, pt_base 1854 arch/x86/xen/mmu_pv.c if (*pt_base == PFN_DOWN(__pa(addr))) { pt_base 1857 arch/x86/xen/mmu_pv.c (*pt_base)++; pt_base 1880 arch/x86/xen/mmu_pv.c unsigned long pt_base, pt_end; pt_base 1892 arch/x86/xen/mmu_pv.c pt_base = PFN_DOWN(__pa(xen_start_info->pt_base)); pt_base 1893 arch/x86/xen/mmu_pv.c pt_end = pt_base + xen_start_info->nr_pt_frames; pt_base 1944 arch/x86/xen/mmu_pv.c init_top_pgt[i] = ((pgd_t *)xen_start_info->pt_base)[i]; pt_base 1982 arch/x86/xen/mmu_pv.c check_pt_base(&pt_base, &pt_end, addr[i]); pt_base 1985 arch/x86/xen/mmu_pv.c xen_pt_base = PFN_PHYS(pt_base); pt_base 1986 arch/x86/xen/mmu_pv.c xen_pt_size = (pt_end - pt_base) * PAGE_SIZE; pt_base 2220 arch/x86/xen/mmu_pv.c phys_addr_t pt_base, paddr; pt_base 2223 arch/x86/xen/mmu_pv.c pt_base = min(__pa(xen_start_info->pt_base), __pa(pmd)); pt_base 2228 arch/x86/xen/mmu_pv.c pt_base = min(pt_base, paddr); pt_base 2231 arch/x86/xen/mmu_pv.c return pt_base; pt_base 54 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); pt_base 56 drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c gfxhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); pt_base 74 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); pt_base 76 drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.c mmhub_v1_0_setup_vm_pt_regs(adev, 0, pt_base); pt_base 80 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c uint64_t pt_base = amdgpu_gmc_pd_addr(adev->gart.bo); pt_base 82 drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.c mmhub_v9_4_setup_vm_pt_regs(adev, hubid, 0, pt_base); pt_base 63 drivers/gpu/drm/msm/adreno/a2xx_gpu.c dma_addr_t pt_base, tran_error; pt_base 67 drivers/gpu/drm/msm/adreno/a2xx_gpu.c msm_gpummu_params(gpu->aspace->mmu, &pt_base, &tran_error); pt_base 109 drivers/gpu/drm/msm/adreno/a2xx_gpu.c gpu_write(gpu, REG_A2XX_MH_MMU_PT_BASE, pt_base); pt_base 14 drivers/gpu/drm/msm/msm_gpummu.c dma_addr_t pt_base; pt_base 83 drivers/gpu/drm/msm/msm_gpummu.c dma_free_attrs(mmu->dev, TABLE_SIZE, gpummu->table, gpummu->pt_base, pt_base 105 drivers/gpu/drm/msm/msm_gpummu.c gpummu->table = dma_alloc_attrs(dev, TABLE_SIZE + 32, &gpummu->pt_base, pt_base 118 drivers/gpu/drm/msm/msm_gpummu.c void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, pt_base 121 drivers/gpu/drm/msm/msm_gpummu.c dma_addr_t base = to_msm_gpummu(mmu)->pt_base; pt_base 123 drivers/gpu/drm/msm/msm_gpummu.c *pt_base = base; pt_base 45 drivers/gpu/drm/msm/msm_mmu.h void msm_gpummu_params(struct msm_mmu *mmu, dma_addr_t *pt_base, pt_base 654 include/xen/interface/xen.h unsigned long pt_base; /* VIRTUAL address of page directory. */