pstate             44 arch/arm64/include/asm/assembler.h 	.macro	inherit_daif, pstate:req, tmp:req
pstate            138 arch/arm64/include/asm/kvm_emulate.h 	return (unsigned long *)&vcpu_gp_regs(vcpu)->regs.pstate;
pstate            500 arch/arm64/include/asm/kvm_emulate.h 	vcpu->arch.ctxt.gp_regs.regs.pstate = read_sysreg_el2(SYS_SPSR);
pstate            504 arch/arm64/include/asm/kvm_emulate.h 	write_sysreg_el2(vcpu->arch.ctxt.gp_regs.regs.pstate, SYS_SPSR);
pstate            223 arch/arm64/include/asm/perf_event.h 	(regs)->pstate = PSR_MODE_EL1h;	\
pstate            197 arch/arm64/include/asm/processor.h 	regs->pstate |= PSR_SSBS_BIT;
pstate            202 arch/arm64/include/asm/processor.h 	regs->pstate |= PSR_AA32_SSBS_BIT;
pstate            209 arch/arm64/include/asm/processor.h 	regs->pstate = PSR_MODE_EL0t;
pstate            222 arch/arm64/include/asm/processor.h 	regs->pstate = PSR_AA32_MODE_USR;
pstate            224 arch/arm64/include/asm/processor.h 		regs->pstate |= PSR_AA32_T_BIT;
pstate            227 arch/arm64/include/asm/processor.h 	regs->pstate |= PSR_AA32_E_BIT;
pstate            133 arch/arm64/include/asm/ptrace.h 	unsigned long pstate;
pstate            135 arch/arm64/include/asm/ptrace.h 	pstate = psr & ~COMPAT_PSR_DIT_BIT;
pstate            138 arch/arm64/include/asm/ptrace.h 		pstate |= PSR_AA32_DIT_BIT;
pstate            140 arch/arm64/include/asm/ptrace.h 	return pstate;
pstate            143 arch/arm64/include/asm/ptrace.h static inline unsigned long pstate_to_compat_psr(const unsigned long pstate)
pstate            147 arch/arm64/include/asm/ptrace.h 	psr = pstate & ~PSR_AA32_DIT_BIT;
pstate            149 arch/arm64/include/asm/ptrace.h 	if (pstate & PSR_AA32_DIT_BIT)
pstate            167 arch/arm64/include/asm/ptrace.h 			u64 pstate;
pstate            195 arch/arm64/include/asm/ptrace.h #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate)
pstate            201 arch/arm64/include/asm/ptrace.h 	(((regs)->pstate & PSR_AA32_T_BIT))
pstate            207 arch/arm64/include/asm/ptrace.h 	(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
pstate            210 arch/arm64/include/asm/ptrace.h 	(((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
pstate            214 arch/arm64/include/asm/ptrace.h 	((regs)->pstate & PSR_MODE_MASK)
pstate            222 arch/arm64/include/asm/ptrace.h 	(!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
pstate            225 arch/arm64/include/asm/ptrace.h 	(!((regs)->pstate & PSR_F_BIT))
pstate            264 arch/arm64/include/asm/ptrace.h 	case offsetof(struct pt_regs, pstate) >> 3:
pstate            265 arch/arm64/include/asm/ptrace.h 		val = regs->pstate;
pstate             24 arch/arm64/include/asm/sdei.h 				   unsigned long pc, unsigned long pstate);
pstate             30 arch/arm64/include/asm/sdei.h 						   unsigned long pstate);
pstate             79 arch/arm64/include/uapi/asm/ptrace.h 	__u64		pstate;
pstate             34 arch/arm64/include/uapi/asm/sigcontext.h 	__u64 pstate;
pstate            381 arch/arm64/kernel/armv8_deprecated.c 	switch (aarch32_check_condition(instr, regs->pstate)) {
pstate            464 arch/arm64/kernel/armv8_deprecated.c 	switch (aarch32_check_condition(instr, regs->pstate)) {
pstate            567 arch/arm64/kernel/armv8_deprecated.c 		regs->pstate |= PSR_AA32_E_BIT;
pstate            570 arch/arm64/kernel/armv8_deprecated.c 		regs->pstate &= ~PSR_AA32_E_BIT;
pstate             61 arch/arm64/kernel/asm-offsets.c   DEFINE(S_PSTATE,		offsetof(struct pt_regs, pstate));
pstate           1186 arch/arm64/kernel/cpufeature.c 		regs->pstate |= PSR_SSBS_BIT;
pstate           1188 arch/arm64/kernel/cpufeature.c 		regs->pstate &= ~PSR_SSBS_BIT;
pstate            146 arch/arm64/kernel/debug-monitors.c 	regs->pstate |= DBG_SPSR_SS;
pstate            152 arch/arm64/kernel/debug-monitors.c 	regs->pstate &= ~DBG_SPSR_SS;
pstate           1399 arch/arm64/kernel/insn.c static bool __kprobes __check_eq(unsigned long pstate)
pstate           1401 arch/arm64/kernel/insn.c 	return (pstate & PSR_Z_BIT) != 0;
pstate           1404 arch/arm64/kernel/insn.c static bool __kprobes __check_ne(unsigned long pstate)
pstate           1406 arch/arm64/kernel/insn.c 	return (pstate & PSR_Z_BIT) == 0;
pstate           1409 arch/arm64/kernel/insn.c static bool __kprobes __check_cs(unsigned long pstate)
pstate           1411 arch/arm64/kernel/insn.c 	return (pstate & PSR_C_BIT) != 0;
pstate           1414 arch/arm64/kernel/insn.c static bool __kprobes __check_cc(unsigned long pstate)
pstate           1416 arch/arm64/kernel/insn.c 	return (pstate & PSR_C_BIT) == 0;
pstate           1419 arch/arm64/kernel/insn.c static bool __kprobes __check_mi(unsigned long pstate)
pstate           1421 arch/arm64/kernel/insn.c 	return (pstate & PSR_N_BIT) != 0;
pstate           1424 arch/arm64/kernel/insn.c static bool __kprobes __check_pl(unsigned long pstate)
pstate           1426 arch/arm64/kernel/insn.c 	return (pstate & PSR_N_BIT) == 0;
pstate           1429 arch/arm64/kernel/insn.c static bool __kprobes __check_vs(unsigned long pstate)
pstate           1431 arch/arm64/kernel/insn.c 	return (pstate & PSR_V_BIT) != 0;
pstate           1434 arch/arm64/kernel/insn.c static bool __kprobes __check_vc(unsigned long pstate)
pstate           1436 arch/arm64/kernel/insn.c 	return (pstate & PSR_V_BIT) == 0;
pstate           1439 arch/arm64/kernel/insn.c static bool __kprobes __check_hi(unsigned long pstate)
pstate           1441 arch/arm64/kernel/insn.c 	pstate &= ~(pstate >> 1);	/* PSR_C_BIT &= ~PSR_Z_BIT */
pstate           1442 arch/arm64/kernel/insn.c 	return (pstate & PSR_C_BIT) != 0;
pstate           1445 arch/arm64/kernel/insn.c static bool __kprobes __check_ls(unsigned long pstate)
pstate           1447 arch/arm64/kernel/insn.c 	pstate &= ~(pstate >> 1);	/* PSR_C_BIT &= ~PSR_Z_BIT */
pstate           1448 arch/arm64/kernel/insn.c 	return (pstate & PSR_C_BIT) == 0;
pstate           1451 arch/arm64/kernel/insn.c static bool __kprobes __check_ge(unsigned long pstate)
pstate           1453 arch/arm64/kernel/insn.c 	pstate ^= (pstate << 3);	/* PSR_N_BIT ^= PSR_V_BIT */
pstate           1454 arch/arm64/kernel/insn.c 	return (pstate & PSR_N_BIT) == 0;
pstate           1457 arch/arm64/kernel/insn.c static bool __kprobes __check_lt(unsigned long pstate)
pstate           1459 arch/arm64/kernel/insn.c 	pstate ^= (pstate << 3);	/* PSR_N_BIT ^= PSR_V_BIT */
pstate           1460 arch/arm64/kernel/insn.c 	return (pstate & PSR_N_BIT) != 0;
pstate           1463 arch/arm64/kernel/insn.c static bool __kprobes __check_gt(unsigned long pstate)
pstate           1466 arch/arm64/kernel/insn.c 	unsigned long temp = pstate ^ (pstate << 3);
pstate           1468 arch/arm64/kernel/insn.c 	temp |= (pstate << 1);	/*PSR_N_BIT |= PSR_Z_BIT */
pstate           1472 arch/arm64/kernel/insn.c static bool __kprobes __check_le(unsigned long pstate)
pstate           1475 arch/arm64/kernel/insn.c 	unsigned long temp = pstate ^ (pstate << 3);
pstate           1477 arch/arm64/kernel/insn.c 	temp |= (pstate << 1);	/*PSR_N_BIT |= PSR_Z_BIT */
pstate           1481 arch/arm64/kernel/insn.c static bool __kprobes __check_al(unsigned long pstate)
pstate             62 arch/arm64/kernel/kgdb.c 	{ "pstate", 4, offsetof(struct pt_regs, pstate)
pstate            182 arch/arm64/kernel/probes/kprobes.c 	kcb->saved_irqflag = regs->pstate & DAIF_MASK;
pstate            183 arch/arm64/kernel/probes/kprobes.c 	regs->pstate |= PSR_I_BIT;
pstate            185 arch/arm64/kernel/probes/kprobes.c 	regs->pstate &= ~PSR_D_BIT;
pstate            191 arch/arm64/kernel/probes/kprobes.c 	regs->pstate &= ~DAIF_MASK;
pstate            192 arch/arm64/kernel/probes/kprobes.c 	regs->pstate |= kcb->saved_irqflag;
pstate            121 arch/arm64/kernel/probes/simulate-insn.c 	if (aarch32_opcode_cond_checks[opcode & 0xf](regs->pstate & 0xffffffff))
pstate            214 arch/arm64/kernel/process.c 	u64 pstate = regs->pstate;
pstate            218 arch/arm64/kernel/process.c 			pstate,
pstate            219 arch/arm64/kernel/process.c 			pstate & PSR_AA32_N_BIT ? 'N' : 'n',
pstate            220 arch/arm64/kernel/process.c 			pstate & PSR_AA32_Z_BIT ? 'Z' : 'z',
pstate            221 arch/arm64/kernel/process.c 			pstate & PSR_AA32_C_BIT ? 'C' : 'c',
pstate            222 arch/arm64/kernel/process.c 			pstate & PSR_AA32_V_BIT ? 'V' : 'v',
pstate            223 arch/arm64/kernel/process.c 			pstate & PSR_AA32_Q_BIT ? 'Q' : 'q',
pstate            224 arch/arm64/kernel/process.c 			pstate & PSR_AA32_T_BIT ? "T32" : "A32",
pstate            225 arch/arm64/kernel/process.c 			pstate & PSR_AA32_E_BIT ? "BE" : "LE",
pstate            226 arch/arm64/kernel/process.c 			pstate & PSR_AA32_A_BIT ? 'A' : 'a',
pstate            227 arch/arm64/kernel/process.c 			pstate & PSR_AA32_I_BIT ? 'I' : 'i',
pstate            228 arch/arm64/kernel/process.c 			pstate & PSR_AA32_F_BIT ? 'F' : 'f');
pstate            231 arch/arm64/kernel/process.c 			pstate,
pstate            232 arch/arm64/kernel/process.c 			pstate & PSR_N_BIT ? 'N' : 'n',
pstate            233 arch/arm64/kernel/process.c 			pstate & PSR_Z_BIT ? 'Z' : 'z',
pstate            234 arch/arm64/kernel/process.c 			pstate & PSR_C_BIT ? 'C' : 'c',
pstate            235 arch/arm64/kernel/process.c 			pstate & PSR_V_BIT ? 'V' : 'v',
pstate            236 arch/arm64/kernel/process.c 			pstate & PSR_D_BIT ? 'D' : 'd',
pstate            237 arch/arm64/kernel/process.c 			pstate & PSR_A_BIT ? 'A' : 'a',
pstate            238 arch/arm64/kernel/process.c 			pstate & PSR_I_BIT ? 'I' : 'i',
pstate            239 arch/arm64/kernel/process.c 			pstate & PSR_F_BIT ? 'F' : 'f',
pstate            240 arch/arm64/kernel/process.c 			pstate & PSR_PAN_BIT ? '+' : '-',
pstate            241 arch/arm64/kernel/process.c 			pstate & PSR_UAO_BIT ? '+' : '-');
pstate            404 arch/arm64/kernel/process.c 		childregs->pstate = PSR_MODE_EL1h;
pstate            407 arch/arm64/kernel/process.c 			childregs->pstate |= PSR_UAO_BIT;
pstate             92 arch/arm64/kernel/ptrace.c 	REG_OFFSET_NAME(pstate),
pstate           1267 arch/arm64/kernel/ptrace.c 			reg = task_pt_regs(target)->pstate;
pstate           1337 arch/arm64/kernel/ptrace.c 			newregs.pstate = reg;
pstate           1884 arch/arm64/kernel/ptrace.c 	regs->pstate &= ~SPSR_EL1_AARCH32_RES0_BITS;
pstate           1888 arch/arm64/kernel/ptrace.c 			regs->pstate |= PSR_AA32_E_BIT;
pstate           1890 arch/arm64/kernel/ptrace.c 			regs->pstate &= ~PSR_AA32_E_BIT;
pstate           1893 arch/arm64/kernel/ptrace.c 	if (user_mode(regs) && (regs->pstate & PSR_MODE32_BIT) &&
pstate           1894 arch/arm64/kernel/ptrace.c 	    (regs->pstate & PSR_AA32_A_BIT) == 0 &&
pstate           1895 arch/arm64/kernel/ptrace.c 	    (regs->pstate & PSR_AA32_I_BIT) == 0 &&
pstate           1896 arch/arm64/kernel/ptrace.c 	    (regs->pstate & PSR_AA32_F_BIT) == 0) {
pstate           1904 arch/arm64/kernel/ptrace.c 	regs->pstate &= PSR_AA32_N_BIT | PSR_AA32_Z_BIT |
pstate           1909 arch/arm64/kernel/ptrace.c 	regs->pstate |= PSR_MODE32_BIT;
pstate           1916 arch/arm64/kernel/ptrace.c 	regs->pstate &= ~SPSR_EL1_AARCH64_RES0_BITS;
pstate           1918 arch/arm64/kernel/ptrace.c 	if (user_mode(regs) && !(regs->pstate & PSR_MODE32_BIT) &&
pstate           1919 arch/arm64/kernel/ptrace.c 	    (regs->pstate & PSR_D_BIT) == 0 &&
pstate           1920 arch/arm64/kernel/ptrace.c 	    (regs->pstate & PSR_A_BIT) == 0 &&
pstate           1921 arch/arm64/kernel/ptrace.c 	    (regs->pstate & PSR_I_BIT) == 0 &&
pstate           1922 arch/arm64/kernel/ptrace.c 	    (regs->pstate & PSR_F_BIT) == 0) {
pstate           1927 arch/arm64/kernel/ptrace.c 	regs->pstate &= PSR_N_BIT | PSR_Z_BIT | PSR_C_BIT | PSR_V_BIT;
pstate           1939 arch/arm64/kernel/ptrace.c 		regs->pstate &= ~DBG_SPSR_SS;
pstate            223 arch/arm64/kernel/sdei.c 	mode = regs->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK);
pstate            498 arch/arm64/kernel/signal.c 	__get_user_error(regs->pstate, &sf->uc.uc_mcontext.pstate, err);
pstate            620 arch/arm64/kernel/signal.c 	__put_user_error(regs->pstate, &sf->uc.uc_mcontext.pstate, err);
pstate            216 arch/arm64/kernel/signal32.c 	regs->pstate = compat_psr_to_pstate(psr);
pstate            324 arch/arm64/kernel/signal32.c 	compat_ulong_t spsr = regs->pstate & ~(PSR_f | PSR_AA32_E_BIT);
pstate            383 arch/arm64/kernel/signal32.c 	regs->pstate	= spsr;
pstate            390 arch/arm64/kernel/signal32.c 	unsigned long psr = pstate_to_compat_psr(regs->pstate);
pstate             20 arch/arm64/kernel/ssbd.c 	task_pt_regs(task)->pstate |= val;
pstate             28 arch/arm64/kernel/ssbd.c 	task_pt_regs(task)->pstate &= ~val;
pstate            342 arch/arm64/kernel/traps.c 			(regs->pstate & hook->pstate_mask) == hook->pstate_val)
pstate            573 arch/arm64/kernel/traps.c 	u32 it, pstate = regs->pstate;
pstate            575 arch/arm64/kernel/traps.c 	it  = (pstate & PSTATE_IT_1_0_MASK) >> PSTATE_IT_1_0_SHIFT;
pstate            576 arch/arm64/kernel/traps.c 	it |= ((pstate & PSTATE_IT_7_2_MASK) >> PSTATE_IT_7_2_SHIFT) << 2;
pstate            588 arch/arm64/kernel/traps.c 	regs->pstate &= ~PSR_AA32_IT_MASK;
pstate            589 arch/arm64/kernel/traps.c 	regs->pstate |= pstate_it;
pstate            609 arch/arm64/kernel/traps.c 	return aarch32_opcode_cond_checks[cond](regs->pstate);
pstate            617 arch/arm64/kernel/traps.c 	if (!(regs->pstate & PSR_AA32_T_BIT) ||
pstate            618 arch/arm64/kernel/traps.c 	    !(regs->pstate & PSR_AA32_IT_MASK))
pstate             71 arch/arm64/kvm/guest.c 	case KVM_REG_ARM_CORE_REG(regs.pstate):
pstate            177 arch/arm64/kvm/guest.c 	if (off == KVM_REG_ARM_CORE_REG(regs.pstate)) {
pstate             72 arch/arm64/kvm/hyp/sysreg-sr.c 	ctxt->gp_regs.regs.pstate	= read_sysreg_el2(SYS_SPSR);
pstate            146 arch/arm64/kvm/hyp/sysreg-sr.c 	u64 pstate = ctxt->gp_regs.regs.pstate;
pstate            147 arch/arm64/kvm/hyp/sysreg-sr.c 	u64 mode = pstate & PSR_AA32_MODE_MASK;
pstate            161 arch/arm64/kvm/hyp/sysreg-sr.c 		pstate = PSR_MODE_EL2h | PSR_IL_BIT;
pstate            164 arch/arm64/kvm/hyp/sysreg-sr.c 	write_sysreg_el2(pstate,			SYS_SPSR);
pstate             40 arch/arm64/kvm/reset.c 	.regs.pstate = (PSR_MODE_EL1h | PSR_A_BIT | PSR_I_BIT |
pstate             45 arch/arm64/kvm/reset.c 	.regs.pstate = (PSR_AA32_MODE_SVC | PSR_AA32_A_BIT |
pstate            249 arch/arm64/mm/fault.c 			(regs->pstate & PSR_PAN_BIT);
pstate            891 arch/arm64/mm/fault.c 	regs->pstate |= PSR_D_BIT;
pstate             67 arch/s390/boot/pgm_check_info.c 	*p++ = hex_asc_lo(psw->pstate);
pstate             42 arch/s390/include/asm/ptrace.h 	unsigned long pstate :	1; /* Problem State */
pstate            158 arch/s390/kernel/dumpstack.c 	       psw->key, psw->mcheck, psw->wait, psw->pstate, psw->as, psw->cc, psw->pm);
pstate           1096 arch/s390/kernel/perf_cpum_sf.c 	psw_bits(regs.psw).pstate = basic->P;
pstate            430 arch/s390/kvm/priv.c 	if (psw_bits(vcpu->arch.sie_block->gpsw).pstate)
pstate             17 arch/sparc/include/asm/hibernate.h 	unsigned long pstate;
pstate             38 arch/sparc/kernel/asm-offsets.c 	OFFSET(SC_REG_PSTATE, saved_context, pstate);
pstate            816 arch/sparc/kernel/irq_64.c 	unsigned long pstate, bucket_pa;
pstate            831 arch/sparc/kernel/irq_64.c 			     : "=&r" (pstate), "=&r" (bucket_pa)
pstate             68 arch/sparc/kernel/process_64.c 		unsigned long pstate;
pstate             79 arch/sparc/kernel/process_64.c 			: "=&r" (pstate)
pstate             95 arch/sparc/kernel/process_64.c 			: "=&r" (pstate)
pstate            299 arch/sparc/kernel/signal32.c 	unsigned long pstate, paddr;
pstate            314 arch/sparc/kernel/signal32.c 	__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
pstate            316 arch/sparc/kernel/signal32.c 				: : "r" (pstate), "i" (PSTATE_IE));
pstate            344 arch/sparc/kernel/signal32.c 	__asm__ __volatile__("wrpr %0, 0x0, %%pstate" : : "r" (pstate));
pstate            399 arch/sparc/kernel/smp_64.c static void spitfire_xcall_helper(u64 data0, u64 data1, u64 data2, u64 pstate, unsigned long cpu)
pstate            434 arch/sparc/kernel/smp_64.c 	: "r" (pstate), "i" (PSTATE_IE), "i" (ASI_INTR_W),
pstate            447 arch/sparc/kernel/smp_64.c 					     : : "r" (pstate));
pstate            455 arch/sparc/kernel/smp_64.c 			     : : "r" (pstate));
pstate            469 arch/sparc/kernel/smp_64.c 	u64 pstate;
pstate            472 arch/sparc/kernel/smp_64.c 	__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
pstate            479 arch/sparc/kernel/smp_64.c 		spitfire_xcall_helper(data0, data1, data2, pstate, cpu_list[i]);
pstate            489 arch/sparc/kernel/smp_64.c 	u64 *mondo, pstate, ver, busy_mask;
pstate            503 arch/sparc/kernel/smp_64.c 	__asm__ __volatile__("rdpr %%pstate, %0" : "=r" (pstate));
pstate            508 arch/sparc/kernel/smp_64.c 			     : : "r" (pstate), "i" (PSTATE_IE));
pstate            566 arch/sparc/kernel/smp_64.c 						     : : "r" (pstate));
pstate            586 arch/sparc/kernel/smp_64.c 				     : : "r" (pstate));
pstate           1342 arch/sparc/kernel/smp_64.c 	unsigned long pstate;
pstate           1367 arch/sparc/kernel/smp_64.c 		: "=r" (pstate)
pstate            744 arch/sparc/kernel/time_64.c 	unsigned long pstate;
pstate            751 arch/sparc/kernel/time_64.c 			     : "=r" (pstate)
pstate            759 arch/sparc/kernel/time_64.c 			     : "r" (pstate));
pstate           2834 arch/sparc/mm/init_64.c 	unsigned long pstate;
pstate           2840 arch/sparc/mm/init_64.c 			     : "=r" (pstate)
pstate           2887 arch/sparc/mm/init_64.c 			     : : "r" (pstate));
pstate            155 arch/x86/kernel/cpu/mce/therm_throt.c 	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
pstate            160 arch/x86/kernel/cpu/mce/therm_throt.c 			state = &pstate->core_throttle;
pstate            162 arch/x86/kernel/cpu/mce/therm_throt.c 			state = &pstate->core_power_limit;
pstate            167 arch/x86/kernel/cpu/mce/therm_throt.c 			state = &pstate->package_throttle;
pstate            169 arch/x86/kernel/cpu/mce/therm_throt.c 			state = &pstate->package_power_limit;
pstate            209 arch/x86/kernel/cpu/mce/therm_throt.c 	struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
pstate            213 arch/x86/kernel/cpu/mce/therm_throt.c 		state = (event == 0) ? &pstate->pkg_thresh0 :
pstate            214 arch/x86/kernel/cpu/mce/therm_throt.c 						&pstate->pkg_thresh1;
pstate            216 arch/x86/kernel/cpu/mce/therm_throt.c 		state = (event == 0) ? &pstate->core_thresh0 :
pstate            217 arch/x86/kernel/cpu/mce/therm_throt.c 						&pstate->core_thresh1;
pstate            365 drivers/cpufreq/brcmstb-avs-cpufreq.c static int brcm_avs_get_pstate(struct private_data *priv, unsigned int *pstate)
pstate            373 drivers/cpufreq/brcmstb-avs-cpufreq.c 	*pstate = args[0];
pstate            378 drivers/cpufreq/brcmstb-avs-cpufreq.c static int brcm_avs_set_pstate(struct private_data *priv, unsigned int pstate)
pstate            382 drivers/cpufreq/brcmstb-avs-cpufreq.c 	args[0] = pstate;
pstate            405 drivers/cpufreq/brcmstb-avs-cpufreq.c 	unsigned int pstate;
pstate            409 drivers/cpufreq/brcmstb-avs-cpufreq.c 	ret = brcm_avs_get_pstate(priv, &pstate);
pstate            428 drivers/cpufreq/brcmstb-avs-cpufreq.c 	ret = brcm_avs_set_pstate(priv, pstate);
pstate            596 drivers/cpufreq/brcmstb-avs-cpufreq.c 		unsigned int pstate;
pstate            598 drivers/cpufreq/brcmstb-avs-cpufreq.c 		ret = brcm_avs_get_pstate(priv, &pstate);
pstate            600 drivers/cpufreq/brcmstb-avs-cpufreq.c 			policy->cur = freq_table[pstate].frequency;
pstate            614 drivers/cpufreq/brcmstb-avs-cpufreq.c 	unsigned int pstate;
pstate            616 drivers/cpufreq/brcmstb-avs-cpufreq.c 	if (brcm_avs_get_pstate(priv, &pstate))
pstate            619 drivers/cpufreq/brcmstb-avs-cpufreq.c 	return sprintf(buf, "%u\n", pstate);
pstate            240 drivers/cpufreq/intel_pstate.c 	struct pstate_data pstate;
pstate            291 drivers/cpufreq/intel_pstate.c 	u64 (*get_val)(struct cpudata*, int pstate);
pstate            510 drivers/cpufreq/intel_pstate.c 		 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
pstate            516 drivers/cpufreq/intel_pstate.c 	int turbo_pstate = cpu->pstate.turbo_pstate;
pstate            519 drivers/cpufreq/intel_pstate.c 		(cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
pstate            740 drivers/cpufreq/intel_pstate.c 	return sprintf(buf, "%d\n", ratio * cpu->pstate.scaling);
pstate            907 drivers/cpufreq/intel_pstate.c 			cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
pstate            986 drivers/cpufreq/intel_pstate.c 	total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
pstate            987 drivers/cpufreq/intel_pstate.c 	no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
pstate           1010 drivers/cpufreq/intel_pstate.c 	total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
pstate           1071 drivers/cpufreq/intel_pstate.c 		int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
pstate           1111 drivers/cpufreq/intel_pstate.c 			turbo_max = cpu->pstate.turbo_pstate;
pstate           1121 drivers/cpufreq/intel_pstate.c 		freq *= cpu->pstate.scaling;
pstate           1333 drivers/cpufreq/intel_pstate.c static u64 atom_get_val(struct cpudata *cpudata, int pstate)
pstate           1339 drivers/cpufreq/intel_pstate.c 	val = (u64)pstate << 8;
pstate           1344 drivers/cpufreq/intel_pstate.c 		int_tofp(pstate - cpudata->pstate.min_pstate),
pstate           1350 drivers/cpufreq/intel_pstate.c 	if (pstate > cpudata->pstate.max_pstate)
pstate           1396 drivers/cpufreq/intel_pstate.c 		int_tofp(cpudata->pstate.max_pstate -
pstate           1397 drivers/cpufreq/intel_pstate.c 			cpudata->pstate.min_pstate));
pstate           1505 drivers/cpufreq/intel_pstate.c static u64 core_get_val(struct cpudata *cpudata, int pstate)
pstate           1509 drivers/cpufreq/intel_pstate.c 	val = (u64)pstate << 8;
pstate           1534 drivers/cpufreq/intel_pstate.c static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
pstate           1536 drivers/cpufreq/intel_pstate.c 	trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
pstate           1537 drivers/cpufreq/intel_pstate.c 	cpu->pstate.current_pstate = pstate;
pstate           1544 drivers/cpufreq/intel_pstate.c 		      pstate_funcs.get_val(cpu, pstate));
pstate           1549 drivers/cpufreq/intel_pstate.c 	intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
pstate           1554 drivers/cpufreq/intel_pstate.c 	int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
pstate           1557 drivers/cpufreq/intel_pstate.c 	intel_pstate_set_pstate(cpu, pstate);
pstate           1562 drivers/cpufreq/intel_pstate.c 	cpu->pstate.min_pstate = pstate_funcs.get_min();
pstate           1563 drivers/cpufreq/intel_pstate.c 	cpu->pstate.max_pstate = pstate_funcs.get_max();
pstate           1564 drivers/cpufreq/intel_pstate.c 	cpu->pstate.max_pstate_physical = pstate_funcs.get_max_physical();
pstate           1565 drivers/cpufreq/intel_pstate.c 	cpu->pstate.turbo_pstate = pstate_funcs.get_turbo();
pstate           1566 drivers/cpufreq/intel_pstate.c 	cpu->pstate.scaling = pstate_funcs.get_scaling();
pstate           1567 drivers/cpufreq/intel_pstate.c 	cpu->pstate.max_freq = cpu->pstate.max_pstate * cpu->pstate.scaling;
pstate           1573 drivers/cpufreq/intel_pstate.c 		cpu->pstate.turbo_freq = phy_max * cpu->pstate.scaling;
pstate           1575 drivers/cpufreq/intel_pstate.c 		cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
pstate           1753 drivers/cpufreq/intel_pstate.c 	return mul_ext_fp(cpu->pstate.max_pstate_physical,
pstate           1772 drivers/cpufreq/intel_pstate.c 			cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
pstate           1775 drivers/cpufreq/intel_pstate.c 	if (target < cpu->pstate.min_pstate)
pstate           1776 drivers/cpufreq/intel_pstate.c 		target = cpu->pstate.min_pstate;
pstate           1792 drivers/cpufreq/intel_pstate.c static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
pstate           1794 drivers/cpufreq/intel_pstate.c 	int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
pstate           1797 drivers/cpufreq/intel_pstate.c 	return clamp_t(int, pstate, min_pstate, max_pstate);
pstate           1800 drivers/cpufreq/intel_pstate.c static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
pstate           1802 drivers/cpufreq/intel_pstate.c 	if (pstate == cpu->pstate.current_pstate)
pstate           1805 drivers/cpufreq/intel_pstate.c 	cpu->pstate.current_pstate = pstate;
pstate           1806 drivers/cpufreq/intel_pstate.c 	wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
pstate           1811 drivers/cpufreq/intel_pstate.c 	int from = cpu->pstate.current_pstate;
pstate           1819 drivers/cpufreq/intel_pstate.c 	trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
pstate           1826 drivers/cpufreq/intel_pstate.c 		cpu->pstate.current_pstate,
pstate           2036 drivers/cpufreq/intel_pstate.c 			cpu->pstate.max_freq : cpu->pstate.turbo_freq;
pstate           2056 drivers/cpufreq/intel_pstate.c 			cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
pstate           2057 drivers/cpufreq/intel_pstate.c 		turbo_max = cpu->pstate.turbo_pstate;
pstate           2150 drivers/cpufreq/intel_pstate.c 	    cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
pstate           2152 drivers/cpufreq/intel_pstate.c 	    policy->max > cpu->pstate.max_freq) {
pstate           2212 drivers/cpufreq/intel_pstate.c 	policy->min = cpu->pstate.min_pstate * cpu->pstate.scaling;
pstate           2213 drivers/cpufreq/intel_pstate.c 	policy->max = cpu->pstate.turbo_pstate * cpu->pstate.scaling;
pstate           2216 drivers/cpufreq/intel_pstate.c 	policy->cpuinfo.min_freq = cpu->pstate.min_pstate * cpu->pstate.scaling;
pstate           2220 drivers/cpufreq/intel_pstate.c 			cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
pstate           2221 drivers/cpufreq/intel_pstate.c 	policy->cpuinfo.max_freq *= cpu->pstate.scaling;
pstate           2227 drivers/cpufreq/intel_pstate.c 			cpu->pstate.max_freq : cpu->pstate.turbo_freq;
pstate           2312 drivers/cpufreq/intel_pstate.c 		cpu->pstate.current_pstate,
pstate           2336 drivers/cpufreq/intel_pstate.c 		target_pstate = DIV_ROUND_UP(freqs.new, cpu->pstate.scaling);
pstate           2339 drivers/cpufreq/intel_pstate.c 		target_pstate = freqs.new / cpu->pstate.scaling;
pstate           2342 drivers/cpufreq/intel_pstate.c 		target_pstate = DIV_ROUND_CLOSEST(freqs.new, cpu->pstate.scaling);
pstate           2346 drivers/cpufreq/intel_pstate.c 	old_pstate = cpu->pstate.current_pstate;
pstate           2347 drivers/cpufreq/intel_pstate.c 	if (target_pstate != cpu->pstate.current_pstate) {
pstate           2348 drivers/cpufreq/intel_pstate.c 		cpu->pstate.current_pstate = target_pstate;
pstate           2352 drivers/cpufreq/intel_pstate.c 	freqs.new = target_pstate * cpu->pstate.scaling;
pstate           2367 drivers/cpufreq/intel_pstate.c 	target_pstate = DIV_ROUND_UP(target_freq, cpu->pstate.scaling);
pstate           2369 drivers/cpufreq/intel_pstate.c 	old_pstate = cpu->pstate.current_pstate;
pstate           2372 drivers/cpufreq/intel_pstate.c 	return target_pstate * cpu->pstate.scaling;
pstate           2406 drivers/cpufreq/intel_pstate.c 		turbo_max = cpu->pstate.turbo_pstate;
pstate           2409 drivers/cpufreq/intel_pstate.c 	min_freq *= cpu->pstate.scaling;
pstate           2411 drivers/cpufreq/intel_pstate.c 	max_freq *= cpu->pstate.scaling;
pstate            200 drivers/cpufreq/powernv-cpufreq.c static unsigned int pstate_to_idx(u8 pstate)
pstate            202 drivers/cpufreq/powernv-cpufreq.c 	unsigned int key = pstate % POWERNV_MAX_PSTATES;
pstate            206 drivers/cpufreq/powernv-cpufreq.c 		if (revmap_data->pstate_id == pstate)
pstate            210 drivers/cpufreq/powernv-cpufreq.c 	pr_warn_once("pstate_to_idx: pstate 0x%x not found\n", pstate);
pstate            324 drivers/firmware/arm_scpi.c 	u8 pstate;
pstate            760 drivers/firmware/arm_scpi.c 	u8 pstate;
pstate            764 drivers/firmware/arm_scpi.c 				sizeof(id), &pstate, sizeof(pstate));
pstate            765 drivers/firmware/arm_scpi.c 	return ret ? ret : pstate;
pstate            768 drivers/firmware/arm_scpi.c static int scpi_device_set_power_state(u16 dev_id, u8 pstate)
pstate            773 drivers/firmware/arm_scpi.c 		.pstate = pstate,
pstate            536 drivers/gpu/drm/amd/amdgpu/amdgpu_dpm.c 				adev->pm.dpm.vce_states[i].pstate =
pstate            266 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 	tmp->pstate = -1;
pstate            272 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate)
pstate            280 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 	if (hive->pstate == pstate)
pstate            283 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 	dev_dbg(adev->dev, "Set xgmi pstate %d.\n", pstate);
pstate            286 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c 		ret = smu_set_xgmi_pstate(&adev->smu, pstate);
pstate             35 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h 	int pstate; /*0 -- low , 1 -- high , -1 unknown*/
pstate             42 drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.h int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
pstate             37 drivers/gpu/drm/amd/include/kgd_pp_interface.h 	u8 pstate;
pstate            781 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	const ATOM_PPLIB_STATE_V2 *pstate;
pstate            783 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	pstate = pstate_arrays->states;
pstate            786 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			pstate = (ATOM_PPLIB_STATE_V2 *)(
pstate            787 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 						  (unsigned long)pstate +
pstate            788 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 			     size_of_entry_v2(pstate->ucNumDPMLevels));
pstate            790 drivers/gpu/drm/amd/powerplay/hwmgr/processpptables.c 	return pstate;
pstate            533 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 	int (*set_xgmi_pstate)(struct smu_context *smu, uint32_t pstate);
pstate            737 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h #define smu_set_xgmi_pstate(smu, pstate) \
pstate            738 drivers/gpu/drm/amd/powerplay/inc/amdgpu_smu.h 		((smu)->funcs->set_xgmi_pstate ? (smu)->funcs->set_xgmi_pstate((smu), (pstate)) : 0)
pstate            454 drivers/gpu/drm/amd/powerplay/inc/smu71.h     uint8_t pstate;
pstate           1512 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 				     uint32_t pstate)
pstate           1518 drivers/gpu/drm/amd/powerplay/smu_v11_0.c 					  pstate ? XGMI_STATE_D0 : XGMI_STATE_D3);
pstate            256 drivers/gpu/drm/arm/malidp_crtc.c 	const struct drm_plane_state *pstate;
pstate            271 drivers/gpu/drm/arm/malidp_crtc.c 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
pstate            282 drivers/gpu/drm/arm/malidp_crtc.c 		h_upscale_factor = div_u64((u64)pstate->crtc_w << 32,
pstate            283 drivers/gpu/drm/arm/malidp_crtc.c 					   pstate->src_w);
pstate            284 drivers/gpu/drm/arm/malidp_crtc.c 		v_upscale_factor = div_u64((u64)pstate->crtc_h << 32,
pstate            285 drivers/gpu/drm/arm/malidp_crtc.c 					   pstate->src_h);
pstate            290 drivers/gpu/drm/arm/malidp_crtc.c 		if (pstate->rotation & MALIDP_ROTATED_MASK) {
pstate            291 drivers/gpu/drm/arm/malidp_crtc.c 			s->input_w = pstate->src_h >> 16;
pstate            292 drivers/gpu/drm/arm/malidp_crtc.c 			s->input_h = pstate->src_w >> 16;
pstate            294 drivers/gpu/drm/arm/malidp_crtc.c 			s->input_w = pstate->src_w >> 16;
pstate            295 drivers/gpu/drm/arm/malidp_crtc.c 			s->input_h = pstate->src_h >> 16;
pstate            298 drivers/gpu/drm/arm/malidp_crtc.c 		s->output_w = pstate->crtc_w;
pstate            299 drivers/gpu/drm/arm/malidp_crtc.c 		s->output_h = pstate->crtc_h;
pstate            343 drivers/gpu/drm/arm/malidp_crtc.c 	const struct drm_plane_state *pstate;
pstate            374 drivers/gpu/drm/arm/malidp_crtc.c 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
pstate            375 drivers/gpu/drm/arm/malidp_crtc.c 		struct drm_framebuffer *fb = pstate->fb;
pstate            377 drivers/gpu/drm/arm/malidp_crtc.c 		if ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier)
pstate            390 drivers/gpu/drm/arm/malidp_crtc.c 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
pstate            392 drivers/gpu/drm/arm/malidp_crtc.c 		struct malidp_plane_state *ms = to_malidp_plane_state(pstate);
pstate            393 drivers/gpu/drm/arm/malidp_crtc.c 		struct drm_framebuffer *fb = pstate->fb;
pstate            395 drivers/gpu/drm/arm/malidp_crtc.c 		if ((pstate->rotation & MALIDP_ROTATED_MASK) || fb->modifier) {
pstate            151 drivers/gpu/drm/mcde/mcde_display.c 			      struct drm_plane_state *pstate,
pstate            156 drivers/gpu/drm/mcde/mcde_display.c 	struct drm_framebuffer *fb = pstate->fb;
pstate            159 drivers/gpu/drm/mcde/mcde_display.c 		u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
pstate           1014 drivers/gpu/drm/mcde/mcde_display.c 	struct drm_plane_state *pstate = plane->state;
pstate           1015 drivers/gpu/drm/mcde/mcde_display.c 	struct drm_framebuffer *fb = pstate->fb;
pstate           1050 drivers/gpu/drm/mcde/mcde_display.c 		mcde_set_extsrc(mcde, drm_fb_cma_get_gem_addr(fb, pstate, 0));
pstate             64 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		struct dpu_plane_state *pstate, struct dpu_format *format)
pstate             81 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	lm->ops.setup_blend_config(lm, pstate->stage,
pstate            122 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	struct dpu_plane_state *pstate = NULL;
pstate            137 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		pstate = to_dpu_plane_state(state);
pstate            144 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 				pstate->stage,
pstate            149 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		format = to_dpu_format(msm_framebuffer_format(pstate->base.fb));
pstate            151 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		if (pstate->stage == DPU_STAGE_BASE && format->alpha_enable)
pstate            154 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		stage_idx = zpos_cnt[pstate->stage]++;
pstate            155 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		stage_cfg->stage[pstate->stage][stage_idx] =
pstate            157 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		stage_cfg->multirect_index[pstate->stage][stage_idx] =
pstate            158 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 					pstate->multirect_index;
pstate            161 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 					   state, pstate, stage_idx,
pstate            169 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 						pstate, format);
pstate            177 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 						1 << pstate->stage;
pstate            818 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	const struct drm_plane_state *pstate;
pstate            863 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
pstate            866 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		if (IS_ERR_OR_NULL(pstate)) {
pstate            867 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 			rc = PTR_ERR(pstate);
pstate            875 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate);
pstate            876 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		pstates[cnt].drm_pstate = pstate;
pstate            877 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		pstates[cnt].stage = pstate->normalized_zpos;
pstate            883 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 			multirect_plane[multirect_count].r1 = pstate;
pstate            888 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 			pipe_staged[pstates[cnt].pipe_id] = pstate;
pstate            893 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		dst = drm_plane_state_dest(pstate);
pstate           1079 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 	struct dpu_plane_state *pstate = NULL;
pstate           1120 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		pstate = to_dpu_plane_state(plane->state);
pstate           1123 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 		if (!pstate || !state)
pstate           1127 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 			pstate->stage);
pstate           1163 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c 			pstate->multirect_mode, pstate->multirect_index);
pstate            140 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate;
pstate            150 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate = to_dpu_plane_state(plane->state);
pstate            175 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) {
pstate            417 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		struct dpu_plane_state *pstate,
pstate            434 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					    pstate->multirect_index);
pstate            436 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 						pstate->multirect_index);
pstate            441 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		struct dpu_plane_state *pstate,
pstate            450 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	memset(&pstate->pixel_ext, 0, sizeof(struct dpu_hw_pixel_ext));
pstate            482 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate->pixel_ext.num_ext_pxls_top[i] =
pstate            484 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate->pixel_ext.num_ext_pxls_left[i] =
pstate            549 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		struct dpu_plane_state *pstate,
pstate            556 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	_dpu_plane_setup_scaler3(pdpu, pstate,
pstate            561 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			&pstate->scaler3_cfg, fmt,
pstate            577 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate = to_dpu_plane_state(plane->state);
pstate            591 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pstate->multirect_index);
pstate            600 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		_dpu_plane_setup_scaler(pdpu, pstate, fmt, true);
pstate            605 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					pstate->multirect_index);
pstate            610 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					pstate->multirect_index);
pstate            614 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					&pstate->pixel_ext);
pstate            617 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pstate->multirect_index != DPU_SSPP_RECT_1)
pstate            619 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					&pdpu->pipe_cfg, &pstate->pixel_ext,
pstate            620 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 					&pstate->scaler3_cfg);
pstate            628 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate = to_dpu_plane_state(drm_state);
pstate            630 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate->multirect_index = DPU_SSPP_RECT_SOLO;
pstate            631 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE;
pstate            636 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate[R_MAX];
pstate            663 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[i] = to_dpu_plane_state(drm_state[i]);
pstate            666 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		if (pstate[i] == NULL) {
pstate            713 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
pstate            714 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL;
pstate            724 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
pstate            725 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX;
pstate            736 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R0]->multirect_index = DPU_SSPP_RECT_1;
pstate            737 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R1]->multirect_index = DPU_SSPP_RECT_0;
pstate            739 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R0]->multirect_index = DPU_SSPP_RECT_0;
pstate            740 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R1]->multirect_index = DPU_SSPP_RECT_1;
pstate            744 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R0]->multirect_mode, pstate[R0]->multirect_index);
pstate            746 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate[R1]->multirect_mode, pstate[R1]->multirect_index);
pstate            767 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate = to_dpu_plane_state(new_state);
pstate            778 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate->aspace = kms->base.aspace;
pstate            787 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (pstate->aspace) {
pstate            789 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pstate->aspace);
pstate            797 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	ret = dpu_format_populate_layout(pstate->aspace,
pstate            925 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate;
pstate            933 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate = to_dpu_plane_state(plane->state);
pstate            950 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 		pstate->pending = false;
pstate            973 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate = to_dpu_plane_state(state);
pstate            981 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	_dpu_plane_set_scanout(plane, pstate, &pdpu->pipe_cfg, fb);
pstate            983 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate->pending = true;
pstate           1003 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	_dpu_plane_setup_scaler(pdpu, pstate, fmt, false);
pstate           1014 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pstate->multirect_index);
pstate           1018 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			(pstate->multirect_index != DPU_SSPP_RECT_1))
pstate           1020 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				&pstate->pixel_ext);
pstate           1028 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			pstate->multirect_index != DPU_SSPP_RECT_1)
pstate           1030 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				&pdpu->pipe_cfg, &pstate->pixel_ext,
pstate           1031 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				&pstate->scaler3_cfg);
pstate           1036 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pstate->multirect_index,
pstate           1037 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pstate->multirect_mode);
pstate           1057 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pstate->multirect_index);
pstate           1060 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 			struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg;
pstate           1098 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate = to_dpu_plane_state(state);
pstate           1101 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 				pstate->multirect_mode);
pstate           1103 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate->pending = true;
pstate           1176 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate;
pstate           1189 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate = kmemdup(old_state, sizeof(*old_state), GFP_KERNEL);
pstate           1190 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (!pstate) {
pstate           1197 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate->pending = false;
pstate           1199 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	__drm_atomic_helper_plane_duplicate_state(plane, &pstate->base);
pstate           1201 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	return &pstate->base;
pstate           1207 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	struct dpu_plane_state *pstate;
pstate           1223 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
pstate           1224 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	if (!pstate) {
pstate           1229 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	pstate->base.plane = plane;
pstate           1231 drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c 	plane->state = &pstate->base;
pstate            644 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		 struct drm_plane_state *state, struct dpu_plane_state *pstate,
pstate            647 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 	TP_ARGS(crtc_id, plane_id, state, pstate, stage_idx, sspp,
pstate            670 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		__entry->stage = pstate->stage;
pstate            672 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		__entry->multirect_idx = pstate->multirect_index;
pstate            673 drivers/gpu/drm/msm/disp/dpu1/dpu_trace.h 		__entry->multirect_mode = pstate->multirect_mode;
pstate            218 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	struct mdp5_plane_state *pstate, *pstates[STAGE_MAX + 1] = {NULL};
pstate            251 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		pstate = to_mdp5_plane_state(plane->state);
pstate            252 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		pstates[pstate->stage] = pstate;
pstate            253 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
pstate            259 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			r_stage[pstate->stage][PIPE_LEFT] =
pstate            268 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			stage[pstate->stage][PIPE_RIGHT] = right_pipe;
pstate            269 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 			r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
pstate            580 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		struct drm_plane_state *pstate)
pstate            582 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	return (pstate->crtc_x <= 0) && (pstate->crtc_y <= 0) &&
pstate            583 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		((pstate->crtc_x + pstate->crtc_w) >= cstate->mode.hdisplay) &&
pstate            584 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		((pstate->crtc_y + pstate->crtc_h) >= cstate->mode.vdisplay);
pstate            618 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	const struct drm_plane_state *pstate;
pstate            628 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 	drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
pstate            629 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		if (!pstate->visible)
pstate            633 drivers/gpu/drm/msm/disp/mdp5/mdp5_crtc.c 		pstates[cnt].state = to_mdp5_plane_state(pstate);
pstate            104 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct mdp5_plane_state *pstate;
pstate            108 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	pstate = to_mdp5_plane_state(state);
pstate            112 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 			pstate->name = (type)val; \
pstate            132 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct mdp5_plane_state *pstate;
pstate            136 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	pstate = to_mdp5_plane_state(state);
pstate            140 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 			*val = pstate->name; \
pstate            159 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
pstate            162 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	drm_printf(p, "\thwpipe=%s\n", pstate->hwpipe ?
pstate            163 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 			pstate->hwpipe->name : "(null)");
pstate            166 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 			   pstate->r_hwpipe ? pstate->r_hwpipe->name :
pstate            168 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	drm_printf(p, "\tpremultiplied=%u\n", pstate->premultiplied);
pstate            169 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	drm_printf(p, "\tzpos=%u\n", pstate->zpos);
pstate            170 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	drm_printf(p, "\talpha=%u\n", pstate->alpha);
pstate            171 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	drm_printf(p, "\tstage=%s\n", stage2name(pstate->stage));
pstate            219 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct mdp5_plane_state *pstate = to_mdp5_plane_state(state);
pstate            224 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	kfree(pstate);
pstate            917 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct drm_plane_state *pstate = plane->state;
pstate            918 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct mdp5_hw_pipe *hwpipe = to_mdp5_plane_state(pstate)->hwpipe;
pstate            969 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	right_hwpipe = to_mdp5_plane_state(pstate)->r_hwpipe;
pstate           1003 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	rotation = drm_rotation_simplify(pstate->rotation,
pstate           1031 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
pstate           1033 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	if (WARN_ON(!pstate->hwpipe))
pstate           1036 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	return pstate->hwpipe->pipe;
pstate           1041 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
pstate           1043 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	if (!pstate->r_hwpipe)
pstate           1046 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	return pstate->r_hwpipe->pipe;
pstate           1051 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	struct mdp5_plane_state *pstate = to_mdp5_plane_state(plane->state);
pstate           1054 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	if (WARN_ON(!pstate->hwpipe))
pstate           1057 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	mask = pstate->hwpipe->flush_mask;
pstate           1059 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 	if (pstate->r_hwpipe)
pstate           1060 drivers/gpu/drm/msm/disp/mdp5/mdp5_plane.c 		mask |= pstate->r_hwpipe->flush_mask;
pstate             19 drivers/gpu/drm/nouveau/include/nvif/if0001.h 	__s8  pstate; /* out: current pstate index */
pstate              7 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/boost.h 	u8  pstate;
pstate              8 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h 	u8  pstate;
pstate             15 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/cstep.h u32 nvbios_cstepEm(struct nvkm_bios *, u8 pstate, u8 *ver, u8 *hdr,
pstate              8 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/perf.h 	u8  pstate;
pstate             19 drivers/gpu/drm/nouveau/include/nvkm/subdev/bios/vpstate.h 	u8  pstate;
pstate             67 drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h 	u8 pstate;
pstate             99 drivers/gpu/drm/nouveau/include/nvkm/subdev/clk.h 	int pstate; /* current */
pstate            123 drivers/gpu/drm/nouveau/nouveau_debugfs.c 			if (info.pstate == state)
pstate             55 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.pstate = clk->pstate;
pstate             61 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.pstate = NVIF_CONTROL_PSTATE_INFO_V0_PSTATE_UNKNOWN;
pstate             75 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 	struct nvkm_pstate *pstate;
pstate            106 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		list_for_each_entry(pstate, &clk->states, head) {
pstate            111 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		lo = pstate->base.domain[domain->name];
pstate            113 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		list_for_each_entry(cstate, &pstate->list, head) {
pstate            118 drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.c 		args->v0.state = pstate->pstate;
pstate             81 drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c 		info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5;
pstate             89 drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c nvbios_boostEm(struct nvkm_bios *bios, u8 pstate,
pstate             94 drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.c 		if (info->pstate == pstate)
pstate             78 drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c 		info->pstate = (nvbios_rd16(bios, data + 0x00) & 0x01e0) >> 5;
pstate             85 drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c nvbios_cstepEm(struct nvkm_bios *bios, u8 pstate, u8 *ver, u8 *hdr,
pstate             90 drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.c 		if (info->pstate == pstate)
pstate            100 drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.c 	info->pstate = nvbios_rd08(bios, perf + 0x00);
pstate             85 drivers/gpu/drm/nouveau/nvkm/subdev/bios/vpstate.c 	e->pstate    = nvbios_rd08(b, offset);
pstate             42 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		u8 pstate, u8 domain, u32 input)
pstate             49 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	data = nvbios_boostEm(bios, pstate, &ver, &hdr, &cnt, &len, &boostE);
pstate            112 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c nvkm_cstate_find_best(struct nvkm_clk *clk, struct nvkm_pstate *pstate,
pstate            119 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	if (!pstate || !cstate)
pstate            136 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	list_for_each_entry_from_reverse(cstate, &pstate->list, head) {
pstate            145 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c nvkm_cstate_get(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
pstate            149 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		return list_last_entry(&pstate->list, typeof(*cstate), head);
pstate            151 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		list_for_each_entry(cstate, &pstate->list, head) {
pstate            160 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c nvkm_cstate_prog(struct nvkm_clk *clk, struct nvkm_pstate *pstate, int cstatei)
pstate            169 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	if (!list_empty(&pstate->list)) {
pstate            170 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		cstate = nvkm_cstate_get(clk, pstate, cstatei);
pstate            171 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		cstate = nvkm_cstate_find_best(clk, pstate, cstate);
pstate            173 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		cstate = &pstate->base;
pstate            177 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, +1);
pstate            186 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 				       pstate->base.voltage, clk->temp, +1);
pstate            201 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 				       pstate->base.voltage, clk->temp, -1);
pstate            207 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		ret = nvkm_therm_cstate(therm, pstate->fanspeed, -1);
pstate            223 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c nvkm_cstate_new(struct nvkm_clk *clk, int idx, struct nvkm_pstate *pstate)
pstate            244 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	*cstate = pstate->base;
pstate            250 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 			u32 freq = nvkm_clk_adjust(clk, true, pstate->pstate,
pstate            257 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	list_add(&cstate->head, &pstate->list);
pstate            270 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	struct nvkm_pstate *pstate;
pstate            273 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	list_for_each_entry(pstate, &clk->states, head) {
pstate            279 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	clk->pstate = pstatei;
pstate            281 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	nvkm_pcie_set_link(pci, pstate->pcie_speed, pstate->pcie_width);
pstate            285 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		int khz = pstate->base.domain[nv_clk_src_mem];
pstate            294 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	return nvkm_cstate_prog(clk, pstate, NVKM_CLK_CSTATE_HIGHEST);
pstate            302 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	int pstate;
pstate            309 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		   clk->pstate, clk->pwrsrc, clk->ustate_ac, clk->ustate_dc,
pstate            312 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	pstate = clk->pwrsrc ? clk->ustate_ac : clk->ustate_dc;
pstate            313 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	if (clk->state_nr && pstate != -1) {
pstate            314 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		pstate = (pstate < 0) ? clk->astate : pstate;
pstate            315 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		pstate = min(pstate, clk->state_nr - 1);
pstate            316 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		pstate = max(pstate, clk->dstate);
pstate            318 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		pstate = clk->pstate = -1;
pstate            321 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	nvkm_trace(subdev, "-> %d\n", pstate);
pstate            322 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	if (pstate != clk->pstate) {
pstate            323 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		int ret = nvkm_pstate_prog(clk, pstate);
pstate            326 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 				   pstate, ret);
pstate            345 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c nvkm_pstate_info(struct nvkm_clk *clk, struct nvkm_pstate *pstate)
pstate            354 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	if (pstate->pstate != 0xff)
pstate            355 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		snprintf(name, sizeof(name), "%02x", pstate->pstate);
pstate            358 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		u32 lo = pstate->base.domain[clock->name];
pstate            364 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		list_for_each_entry(cstate, &pstate->list, head) {
pstate            388 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c nvkm_pstate_del(struct nvkm_pstate *pstate)
pstate            392 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	list_for_each_entry_safe(cstate, temp, &pstate->list, head) {
pstate            396 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	list_del(&pstate->head);
pstate            397 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	kfree(pstate);
pstate            405 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	struct nvkm_pstate *pstate;
pstate            415 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	if (perfE.pstate == 0xff)
pstate            418 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	pstate = kzalloc(sizeof(*pstate), GFP_KERNEL);
pstate            419 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	cstate = &pstate->base;
pstate            420 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	if (!pstate)
pstate            423 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	INIT_LIST_HEAD(&pstate->list);
pstate            425 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	pstate->pstate = perfE.pstate;
pstate            426 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	pstate->fanspeed = perfE.fanspeed;
pstate            427 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	pstate->pcie_speed = perfE.pcie_speed;
pstate            428 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	pstate->pcie_width = perfE.pcie_width;
pstate            446 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 							 pstate->pstate,
pstate            454 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	data = nvbios_cstepEm(bios, pstate->pstate, &ver, &hdr, &cstepE);
pstate            458 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 			nvkm_cstate_new(clk, idx, pstate);
pstate            462 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	nvkm_pstate_info(clk, pstate);
pstate            463 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	list_add_tail(&pstate->head, &clk->states);
pstate            474 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	struct nvkm_pstate *pstate;
pstate            481 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		list_for_each_entry(pstate, &clk->states, head) {
pstate            482 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 			if (pstate->pstate == req)
pstate            487 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		if (pstate->pstate != req)
pstate            599 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	clk->bstate.pstate = 0xff;
pstate            618 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	clk->pstate = -1;
pstate            628 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	struct nvkm_pstate *pstate, *temp;
pstate            636 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 	list_for_each_entry_safe(pstate, temp, &clk->states, head) {
pstate            637 drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.c 		nvkm_pstate_del(pstate);
pstate            625 drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.c 		func->pstates[i].pstate = i + 1;
pstate             63 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c 	*state = clk->pstate;
pstate             75 drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.c 	level = cur_level = clk->pstate;
pstate             86 drivers/gpu/drm/pl111/pl111_display.c 			       struct drm_plane_state *pstate,
pstate             91 drivers/gpu/drm/pl111/pl111_display.c 	struct drm_framebuffer *fb = pstate->fb;
pstate             97 drivers/gpu/drm/pl111/pl111_display.c 		u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
pstate            397 drivers/gpu/drm/pl111/pl111_display.c 	struct drm_plane_state *pstate = plane->state;
pstate            398 drivers/gpu/drm/pl111/pl111_display.c 	struct drm_framebuffer *fb = pstate->fb;
pstate            401 drivers/gpu/drm/pl111/pl111_display.c 		u32 addr = drm_fb_cma_get_gem_addr(fb, pstate, 0);
pstate           1128 drivers/gpu/drm/radeon/r600_dpm.c 				rdev->pm.dpm.vce_states[i].pstate =
pstate           1531 drivers/gpu/drm/radeon/radeon.h 	u8 pstate;
pstate             71 drivers/gpu/drm/tve200/tve200_display.c 			       struct drm_plane_state *pstate,
pstate             76 drivers/gpu/drm/tve200/tve200_display.c 	struct drm_framebuffer *fb = pstate->fb;
pstate             92 drivers/gpu/drm/tve200/tve200_display.c 		u32 offset = drm_fb_cma_get_gem_addr(fb, pstate, 0);
pstate            247 drivers/gpu/drm/tve200/tve200_display.c 	struct drm_plane_state *pstate = plane->state;
pstate            248 drivers/gpu/drm/tve200/tve200_display.c 	struct drm_framebuffer *fb = pstate->fb;
pstate            252 drivers/gpu/drm/tve200/tve200_display.c 		writel(drm_fb_cma_get_gem_addr(fb, pstate, 0),
pstate            257 drivers/gpu/drm/tve200/tve200_display.c 			writel(drm_fb_cma_get_gem_addr(fb, pstate, 1),
pstate            259 drivers/gpu/drm/tve200/tve200_display.c 			writel(drm_fb_cma_get_gem_addr(fb, pstate, 2),
pstate            261 drivers/gpu/drm/vc4/vc4_plane.c static int vc4_plane_margins_adj(struct drm_plane_state *pstate)
pstate            263 drivers/gpu/drm/vc4/vc4_plane.c 	struct vc4_plane_state *vc4_pstate = to_vc4_plane_state(pstate);
pstate            267 drivers/gpu/drm/vc4/vc4_plane.c 	crtc_state = drm_atomic_get_new_crtc_state(pstate->state,
pstate            268 drivers/gpu/drm/vc4/vc4_plane.c 						   pstate->crtc);
pstate           12783 drivers/infiniband/hw/hfi1/chip.c const char *opa_pstate_name(u32 pstate)
pstate           12799 drivers/infiniband/hw/hfi1/chip.c 	if (pstate < ARRAY_SIZE(port_physical_names))
pstate           12800 drivers/infiniband/hw/hfi1/chip.c 		return port_physical_names[pstate];
pstate            811 drivers/infiniband/hw/hfi1/chip.h const char *opa_pstate_name(u32 pstate);
pstate            534 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c 	tsin->pstate = pinctrl_lookup_state(fei->pinctrl, tsin_pin_name);
pstate            535 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c 	if (IS_ERR(tsin->pstate)) {
pstate            538 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c 		ret = PTR_ERR(tsin->pstate);
pstate            542 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.c 	ret = pinctrl_select_state(fei->pinctrl, tsin->pstate);
pstate             36 drivers/media/platform/sti/c8sectpfe/c8sectpfe-core.h 	struct pinctrl_state *pstate;
pstate           6158 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c 	ramrod_param.pstate = &bp->sp_state;
pstate            258 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	return !!test_bit(o->state, o->pstate);
pstate            264 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	clear_bit(o->state, o->pstate);
pstate            271 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	set_bit(o->state, o->pstate);
pstate            284 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 				   unsigned long *pstate)
pstate            296 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 		if (!test_bit(state, pstate)) {
pstate            320 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	return bnx2x_state_wait(bp, raw->state, raw->pstate);
pstate           2096 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	unsigned long *pstate, bnx2x_obj_type type)
pstate           2104 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	raw->pstate = pstate;
pstate           2114 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	int state, unsigned long *pstate, bnx2x_obj_type type,
pstate           2132 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 			   state, pstate, type);
pstate           2139 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 			unsigned long *pstate, bnx2x_obj_type type,
pstate           2145 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 				   rdata_mapping, state, pstate, type,
pstate           2193 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 			 unsigned long *pstate, bnx2x_obj_type type,
pstate           2199 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 				   rdata_mapping, state, pstate, type, NULL,
pstate           2234 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 			     unsigned long *pstate, bnx2x_obj_type type,
pstate           2242 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 				   rdata_mapping, state, pstate, type,
pstate           2380 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	clear_bit(p->state, p->pstate);
pstate           2549 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	return bnx2x_state_wait(bp, p->state, p->pstate);
pstate           2649 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	if (bnx2x_state_wait(bp, o->sched_state, o->raw.pstate) ||
pstate           4045 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	clear_bit(o->sched_state, o->raw.pstate);
pstate           4052 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	set_bit(o->sched_state, o->raw.pstate);
pstate           4058 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 	return !!test_bit(o->sched_state, o->raw.pstate);
pstate           4070 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 			  int state, unsigned long *pstate, bnx2x_obj_type type)
pstate           4075 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 			   rdata, rdata_mapping, state, pstate, type);
pstate           4631 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 			       int state, unsigned long *pstate,
pstate           4635 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.c 			   rdata_mapping, state, pstate, type);
pstate             89 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h 	unsigned long	*pstate; /* pointer to state buffer */
pstate            477 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h 	unsigned long *pstate;
pstate           1418 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h 			unsigned long *pstate, bnx2x_obj_type type,
pstate           1425 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h 			 unsigned long *pstate, bnx2x_obj_type type,
pstate           1432 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h 			     unsigned long *pstate, bnx2x_obj_type type,
pstate           1472 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h 			  int state, unsigned long *pstate,
pstate           1514 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sp.h 			       int state, unsigned long *pstate,
pstate            622 drivers/net/ethernet/broadcom/bnx2x/bnx2x_sriov.c 	ramrod->pstate = &vf->filter_state;
pstate           1829 drivers/net/ethernet/dec/tulip/tulip_core.c 	pci_power_t pstate;
pstate           1848 drivers/net/ethernet/dec/tulip/tulip_core.c 	pstate = pci_choose_state(pdev, state);
pstate           1849 drivers/net/ethernet/dec/tulip/tulip_core.c 	if (state.event == PM_EVENT_SUSPEND && pstate != PCI_D0) {
pstate           1853 drivers/net/ethernet/dec/tulip/tulip_core.c 		rc = pci_enable_wake(pdev, pstate, tp->wolinfo.wolopts);
pstate           1857 drivers/net/ethernet/dec/tulip/tulip_core.c 	pci_set_power_state(pdev, pstate);
pstate            751 drivers/opp/core.c 	unsigned int pstate;
pstate            759 drivers/opp/core.c 		pstate = likely(opp) ? opp->required_opps[0]->pstate : 0;
pstate            760 drivers/opp/core.c 		ret = dev_pm_genpd_set_performance_state(dev, pstate);
pstate            763 drivers/opp/core.c 				dev_name(dev), pstate, ret);
pstate            777 drivers/opp/core.c 		pstate = likely(opp) ? opp->required_opps[i]->pstate : 0;
pstate            782 drivers/opp/core.c 		ret = dev_pm_genpd_set_performance_state(genpd_virt_devs[i], pstate);
pstate            785 drivers/opp/core.c 				dev_name(genpd_virt_devs[i]), pstate, ret);
pstate           1950 drivers/opp/core.c 				       unsigned int pstate)
pstate           1956 drivers/opp/core.c 	if (!pstate)
pstate           1967 drivers/opp/core.c 		return pstate;
pstate           1983 drivers/opp/core.c 		if (opp->pstate == pstate) {
pstate           1984 drivers/opp/core.c 			dest_pstate = opp->required_opps[i]->pstate;
pstate             91 drivers/opp/debugfs.c 	debugfs_create_u32("performance_state", S_IRUGO, d, &opp->pstate);
pstate            605 drivers/opp/of.c 		new_opp->pstate = pm_genpd_opp_to_performance_state(dev, new_opp);
pstate            694 drivers/opp/of.c 		pstate_count += !!opp->pstate;
pstate            994 drivers/opp/of.c 	int pstate = -EINVAL;
pstate           1009 drivers/opp/of.c 		pstate = opp->pstate;
pstate           1018 drivers/opp/of.c 	return pstate;
pstate             79 drivers/opp/opp.h 	unsigned int pstate;
pstate             86 drivers/regulator/pwm-regulator.c 	struct pwm_state pstate;
pstate             89 drivers/regulator/pwm-regulator.c 	pwm_init_state(drvdata->pwm, &pstate);
pstate             90 drivers/regulator/pwm-regulator.c 	pwm_set_relative_duty_cycle(&pstate,
pstate             93 drivers/regulator/pwm-regulator.c 	ret = pwm_apply_state(drvdata->pwm, &pstate);
pstate            154 drivers/regulator/pwm-regulator.c 	struct pwm_state pstate;
pstate            158 drivers/regulator/pwm-regulator.c 	pwm_get_state(drvdata->pwm, &pstate);
pstate            160 drivers/regulator/pwm-regulator.c 	voltage = pwm_get_relative_duty_cycle(&pstate, duty_unit);
pstate            191 drivers/regulator/pwm-regulator.c 	struct pwm_state pstate;
pstate            196 drivers/regulator/pwm-regulator.c 	pwm_init_state(drvdata->pwm, &pstate);
pstate            217 drivers/regulator/pwm-regulator.c 	pwm_set_relative_duty_cycle(&pstate, dutycycle, duty_unit);
pstate            219 drivers/regulator/pwm-regulator.c 	ret = pwm_apply_state(drvdata->pwm, &pstate);
pstate           1543 drivers/scsi/qla2xxx/qla_attr.c 	uint32_t pstate;
pstate           1546 drivers/scsi/qla2xxx/qla_attr.c 		pstate = qlafx00_fw_state_show(dev, attr, buf);
pstate           1547 drivers/scsi/qla2xxx/qla_attr.c 		return scnprintf(buf, PAGE_SIZE, "0x%x\n", pstate);
pstate            135 include/linux/pm_opp.h int dev_pm_opp_xlate_performance_state(struct opp_table *src_table, struct opp_table *dst_table, unsigned int pstate);
pstate            310 include/linux/pm_opp.h static inline int dev_pm_opp_xlate_performance_state(struct opp_table *src_table, struct opp_table *dst_table, unsigned int pstate)
pstate            106 samples/bpf/cpustat_kern.c 	u64 *cts, *pts, *cstate, *pstate, prev_state, cur_ts, delta;
pstate            131 samples/bpf/cpustat_kern.c 	pstate = bpf_map_lookup_elem(&my_map, &key);
pstate            132 samples/bpf/cpustat_kern.c 	if (!pstate)
pstate            171 samples/bpf/cpustat_kern.c 		pstate_idx = find_cpu_pstate_idx(*pstate);
pstate            214 samples/bpf/cpustat_kern.c 	u64 *pts, *cstate, *pstate, prev_state, cur_ts, delta;
pstate            226 samples/bpf/cpustat_kern.c 	pstate = bpf_map_lookup_elem(&my_map, &key);
pstate            227 samples/bpf/cpustat_kern.c 	if (!pstate)
pstate            235 samples/bpf/cpustat_kern.c 	prev_state = *pstate;
pstate            236 samples/bpf/cpustat_kern.c 	*pstate = ctx->state;
pstate            268 samples/bpf/cpustat_kern.c 	pstate_idx = find_cpu_pstate_idx(*pstate);
pstate             34 samples/bpf/cpustat_user.c 	unsigned long pstate[MAX_PSTATE_ENTRIES];
pstate             72 samples/bpf/cpustat_user.c 			printf("%-11ld ", data->pstate[i] / 1000000);
pstate             93 samples/bpf/cpustat_user.c 			stat_data[c].pstate[i] = value;
pstate             45 samples/kprobes/kprobe_example.c 		p->symbol_name, p->addr, (long)regs->pc, (long)regs->pstate);
pstate             74 samples/kprobes/kprobe_example.c 		p->symbol_name, p->addr, (long)regs->pstate);
pstate             42 tools/power/cpupower/utils/helpers/amd.c static int get_did(int family, union msr_pstate pstate)
pstate             47 tools/power/cpupower/utils/helpers/amd.c 		t = pstate.val & 0xf;
pstate             49 tools/power/cpupower/utils/helpers/amd.c 		t = pstate.fam17h_bits.did;
pstate             51 tools/power/cpupower/utils/helpers/amd.c 		t = pstate.bits.did;
pstate             56 tools/power/cpupower/utils/helpers/amd.c static int get_cof(int family, union msr_pstate pstate)
pstate             61 tools/power/cpupower/utils/helpers/amd.c 	did = get_did(family, pstate);
pstate             63 tools/power/cpupower/utils/helpers/amd.c 		fid = pstate.fam17h_bits.fid;
pstate             67 tools/power/cpupower/utils/helpers/amd.c 		fid = pstate.bits.fid;
pstate             92 tools/power/cpupower/utils/helpers/amd.c 	union msr_pstate pstate;
pstate            120 tools/power/cpupower/utils/helpers/amd.c 		if (read_msr(cpu, MSR_AMD_PSTATE + i, &pstate.val))
pstate            122 tools/power/cpupower/utils/helpers/amd.c 		if ((cpu_family == 0x17) && (!pstate.fam17h_bits.en))
pstate            124 tools/power/cpupower/utils/helpers/amd.c 		else if (!pstate.bits.en)
pstate            127 tools/power/cpupower/utils/helpers/amd.c 		pstates[i] = get_cof(cpu_family, pstate);
pstate            307 tools/testing/selftests/kvm/lib/aarch64/processor.c 	uint64_t pstate, pc;
pstate            309 tools/testing/selftests/kvm/lib/aarch64/processor.c 	get_reg(vm, vcpuid, ARM64_CORE_REG(regs.pstate), &pstate);
pstate            313 tools/testing/selftests/kvm/lib/aarch64/processor.c 		indent, "", pstate, pc);