psr_vsc           992 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	struct dp_sdp psr_vsc;
psr_vsc          1003 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	memset(&psr_vsc, 0, sizeof(psr_vsc));
psr_vsc          1004 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.sdp_header.HB0 = 0;
psr_vsc          1005 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.sdp_header.HB1 = 0x7;
psr_vsc          1006 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.sdp_header.HB2 = 0x2;
psr_vsc          1007 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.sdp_header.HB3 = 0x8;
psr_vsc          1008 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.db[0] = 0;
psr_vsc          1009 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.db[1] = EDP_VSC_PSR_STATE_ACTIVE | EDP_VSC_PSR_CRC_VALUES_VALID;
psr_vsc          1011 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	ret = analogix_dp_send_psr_spd(dp, &psr_vsc, true);
psr_vsc          1020 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	struct dp_sdp psr_vsc;
psr_vsc          1048 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	memset(&psr_vsc, 0, sizeof(psr_vsc));
psr_vsc          1049 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.sdp_header.HB0 = 0;
psr_vsc          1050 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.sdp_header.HB1 = 0x7;
psr_vsc          1051 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.sdp_header.HB2 = 0x2;
psr_vsc          1052 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.sdp_header.HB3 = 0x8;
psr_vsc          1054 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.db[0] = 0;
psr_vsc          1055 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	psr_vsc.db[1] = 0;
psr_vsc          1057 drivers/gpu/drm/bridge/analogix/analogix_dp_core.c 	return analogix_dp_send_psr_spd(dp, &psr_vsc, true);
psr_vsc           346 drivers/gpu/drm/i915/display/intel_psr.c 	struct dp_sdp psr_vsc;
psr_vsc           350 drivers/gpu/drm/i915/display/intel_psr.c 		memset(&psr_vsc, 0, sizeof(psr_vsc));
psr_vsc           351 drivers/gpu/drm/i915/display/intel_psr.c 		psr_vsc.sdp_header.HB0 = 0;
psr_vsc           352 drivers/gpu/drm/i915/display/intel_psr.c 		psr_vsc.sdp_header.HB1 = 0x7;
psr_vsc           354 drivers/gpu/drm/i915/display/intel_psr.c 			psr_vsc.sdp_header.HB2 = 0x5;
psr_vsc           355 drivers/gpu/drm/i915/display/intel_psr.c 			psr_vsc.sdp_header.HB3 = 0x13;
psr_vsc           357 drivers/gpu/drm/i915/display/intel_psr.c 			psr_vsc.sdp_header.HB2 = 0x4;
psr_vsc           358 drivers/gpu/drm/i915/display/intel_psr.c 			psr_vsc.sdp_header.HB3 = 0xe;
psr_vsc           362 drivers/gpu/drm/i915/display/intel_psr.c 		memset(&psr_vsc, 0, sizeof(psr_vsc));
psr_vsc           363 drivers/gpu/drm/i915/display/intel_psr.c 		psr_vsc.sdp_header.HB0 = 0;
psr_vsc           364 drivers/gpu/drm/i915/display/intel_psr.c 		psr_vsc.sdp_header.HB1 = 0x7;
psr_vsc           365 drivers/gpu/drm/i915/display/intel_psr.c 		psr_vsc.sdp_header.HB2 = 0x2;
psr_vsc           366 drivers/gpu/drm/i915/display/intel_psr.c 		psr_vsc.sdp_header.HB3 = 0x8;
psr_vsc           371 drivers/gpu/drm/i915/display/intel_psr.c 					DP_SDP_VSC, &psr_vsc, sizeof(psr_vsc));