psr_state_offset  100 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	uint32_t psr_state_offset = 0xf0;
psr_state_offset  108 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);
psr_state_offset  485 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	uint32_t psr_state_offset = 0xf0;
psr_state_offset  497 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	REG_WRITE(DMCU_IRAM_RD_CTRL, psr_state_offset);