psr_state         175 drivers/gpu/drm/amd/display/dc/dc_link.h bool dc_link_get_psr_state(const struct dc_link *dc_link, uint32_t *psr_state);
psr_state          96 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dce_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
psr_state         111 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
psr_state         126 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	uint32_t psr_state = 0;
psr_state         145 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			dce_get_dmcu_psr_state(dmcu, &psr_state);
psr_state         147 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 				if (psr_state != 0)
psr_state         150 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 				if (psr_state == 0)
psr_state         481 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c static void dcn10_get_dmcu_psr_state(struct dmcu *dmcu, uint32_t *psr_state)
psr_state         500 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	*psr_state = REG_READ(DMCU_IRAM_RD_DATA);
psr_state         515 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	uint32_t psr_state = 0;
psr_state         521 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	dcn10_get_dmcu_psr_state(dmcu, &psr_state);
psr_state         522 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 	if (psr_state == 0 && !enable)
psr_state         546 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 			dcn10_get_dmcu_psr_state(dmcu, &psr_state);
psr_state         548 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 				if (psr_state != 0)
psr_state         551 drivers/gpu/drm/amd/display/dc/dce/dce_dmcu.c 				if (psr_state == 0)
psr_state          67 drivers/gpu/drm/amd/display/dc/inc/hw/dmcu.h 	void (*get_psr_state)(struct dmcu *dmcu, uint32_t *psr_state);
psr_state         142 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 	uint8_t psr_state;						/* 0xf0       */
psr_state         188 drivers/gpu/drm/amd/display/modules/power/power_helpers.c 	uint8_t psr_state;						/* 0xf0       */