psr_mmio_base    1216 drivers/gpu/drm/i915/display/intel_psr.c 	dev_priv->psr_mmio_base = IS_HASWELL(dev_priv) ?
psr_mmio_base    1339 drivers/gpu/drm/i915/i915_drv.h 	u32 psr_mmio_base;
psr_mmio_base    4204 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_CTL				_MMIO(dev_priv->psr_mmio_base + 0)
psr_mmio_base    4241 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_AUX_CTL				_MMIO(dev_priv->psr_mmio_base + 0x10)
psr_mmio_base    4248 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_AUX_DATA(i)			_MMIO(dev_priv->psr_mmio_base + 0x14 + (i) * 4) /* 5 registers */
psr_mmio_base    4250 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_STATUS				_MMIO(dev_priv->psr_mmio_base + 0x40)
psr_mmio_base    4275 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_PERF_CNT		_MMIO(dev_priv->psr_mmio_base + 0x44)
psr_mmio_base    4278 drivers/gpu/drm/i915/i915_reg.h #define EDP_PSR_DEBUG				_MMIO(dev_priv->psr_mmio_base + 0x60) /* PSR_MASK on SKL+ */