priv_uar 370 drivers/infiniband/hw/hns/hns_roce_cq.c uar = &hr_dev->priv_uar; priv_uar 1001 drivers/infiniband/hw/hns/hns_roce_device.h struct hns_roce_uar priv_uar; priv_uar 3289 drivers/infiniband/hw/hns/hns_roce_hw_v1.c DB_REG_OFFSET * hr_dev->priv_uar.index; priv_uar 809 drivers/infiniband/hw/hns/hns_roce_main.c ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar); priv_uar 864 drivers/infiniband/hw/hns/hns_roce_main.c hns_roce_uar_free(hr_dev, &hr_dev->priv_uar); priv_uar 832 drivers/infiniband/hw/hns/hns_roce_qp.c DB_REG_OFFSET * hr_dev->priv_uar.index; priv_uar 834 drivers/infiniband/hw/hns/hns_roce_qp.c DB_REG_OFFSET * hr_dev->priv_uar.index; priv_uar 241 drivers/infiniband/hw/mlx4/cq.c uar = &dev->priv_uar; priv_uar 2653 drivers/infiniband/hw/mlx4/main.c if (mlx4_uar_alloc(dev, &ibdev->priv_uar)) priv_uar 2656 drivers/infiniband/hw/mlx4/main.c ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT, priv_uar 2936 drivers/infiniband/hw/mlx4/main.c mlx4_uar_free(dev, &ibdev->priv_uar); priv_uar 3048 drivers/infiniband/hw/mlx4/main.c mlx4_uar_free(dev, &ibdev->priv_uar); priv_uar 588 drivers/infiniband/hw/mlx4/mlx4_ib.h struct mlx4_uar priv_uar; priv_uar 2257 drivers/infiniband/hw/mlx4/qp.c mlx4_to_hw_uar_index(dev->dev, dev->priv_uar.index)); priv_uar 142 drivers/net/ethernet/mellanox/mlx4/en_cq.c &mdev->priv_uar, cq->wqres.db.dma, &cq->mcq, priv_uar 244 drivers/net/ethernet/mellanox/mlx4/en_main.c mlx4_uar_free(dev, &mdev->priv_uar); priv_uar 285 drivers/net/ethernet/mellanox/mlx4/en_main.c if (mlx4_uar_alloc(dev, &mdev->priv_uar)) priv_uar 288 drivers/net/ethernet/mellanox/mlx4/en_main.c mdev->uar_map = ioremap((phys_addr_t) mdev->priv_uar.pfn << PAGE_SHIFT, priv_uar 345 drivers/net/ethernet/mellanox/mlx4/en_main.c mlx4_uar_free(dev, &mdev->priv_uar); priv_uar 62 drivers/net/ethernet/mellanox/mlx4/en_resources.c mdev->priv_uar.index)); priv_uar 123 drivers/net/ethernet/mellanox/mlx4/en_tx.c ring->bf.uar = &mdev->priv_uar; priv_uar 426 drivers/net/ethernet/mellanox/mlx4/mlx4_en.h struct mlx4_uar priv_uar;