priv_state       1915 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	struct drm_private_state *priv_state;
priv_state       1920 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	priv_state = drm_atomic_get_private_obj_state(state, &dm->atomic_obj);
priv_state       1921 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	if (IS_ERR(priv_state))
priv_state       1922 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 		return PTR_ERR(priv_state);
priv_state       1924 drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c 	*dm_state = to_dm_atomic_state(priv_state);
priv_state         90 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	struct drm_private_state *priv_state;
priv_state         97 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	priv_state = drm_atomic_get_private_obj_state(s, &mdp5_kms->glob_state);
priv_state         98 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	if (IS_ERR(priv_state))
priv_state         99 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 		return ERR_CAST(priv_state);
priv_state        101 drivers/gpu/drm/msm/disp/mdp5/mdp5_kms.c 	return to_mdp5_global_state(priv_state);
priv_state         53 drivers/gpu/drm/vc4/vc4_kms.c 	struct drm_private_state *priv_state;
priv_state         60 drivers/gpu/drm/vc4/vc4_kms.c 	priv_state = drm_atomic_get_private_obj_state(state, manager);
priv_state         61 drivers/gpu/drm/vc4/vc4_kms.c 	if (IS_ERR(priv_state))
priv_state         62 drivers/gpu/drm/vc4/vc4_kms.c 		return ERR_CAST(priv_state);
priv_state         64 drivers/gpu/drm/vc4/vc4_kms.c 	return to_vc4_ctm_state(priv_state);
priv_state        414 drivers/gpu/drm/vc4/vc4_kms.c 	struct drm_private_state *priv_state;
priv_state        418 drivers/gpu/drm/vc4/vc4_kms.c 	priv_state = drm_atomic_get_private_obj_state(state,
priv_state        420 drivers/gpu/drm/vc4/vc4_kms.c 	if (IS_ERR(priv_state))
priv_state        421 drivers/gpu/drm/vc4/vc4_kms.c 		return PTR_ERR(priv_state);
priv_state        423 drivers/gpu/drm/vc4/vc4_kms.c 	load_state = to_vc4_load_tracker_state(priv_state);