priv1             153 arch/powerpc/include/asm/spu.h 	struct spu_priv1 __iomem *priv1;
priv1             232 arch/powerpc/include/asm/spu_csa.h 	struct spu_priv1_collapsed priv1;
priv1              61 arch/powerpc/platforms/cell/spu_manage.c 		iounmap(spu->priv1);
priv1             155 arch/powerpc/platforms/cell/spu_manage.c 		spu->priv1 = spu_map_prop_old(spu, node, "priv1");
priv1             156 arch/powerpc/platforms/cell/spu_manage.c 		if (!spu->priv1)
priv1             240 arch/powerpc/platforms/cell/spu_manage.c 			       (void __iomem**)&spu->priv1, NULL);
priv1             252 arch/powerpc/platforms/cell/spu_manage.c 	pr_debug("  priv1         :                       0x%p\n", spu->priv1);
priv1             332 arch/powerpc/platforms/cell/spu_manage.c 		spu->local_store, spu->problem, spu->priv1,
priv1              31 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
priv1              32 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_mask_RW[class], old_mask & mask);
priv1              39 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	old_mask = in_be64(&spu->priv1->int_mask_RW[class]);
priv1              40 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_mask_RW[class], old_mask | mask);
priv1              45 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_mask_RW[class], mask);
priv1              50 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->int_mask_RW[class]);
priv1              55 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_stat_RW[class], stat);
priv1              60 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->int_stat_RW[class]);
priv1              78 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->int_route_RW, route);
priv1              83 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->mfc_dar_RW);
priv1              88 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->mfc_dsisr_RW);
priv1              93 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->mfc_dsisr_RW, dsisr);
priv1              98 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->mfc_sdr_RW, mfspr(SPRN_SDR1));
priv1             103 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->mfc_sr1_RW, sr1);
priv1             108 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->mfc_sr1_RW);
priv1             113 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->mfc_tclass_id_RW, tclass_id);
priv1             118 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->mfc_tclass_id_RW);
priv1             123 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->tlb_invalidate_entry_W, 0ul);
priv1             128 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->resource_allocation_groupID_RW, id);
priv1             133 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->resource_allocation_groupID_RW);
priv1             138 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	out_be64(&spu->priv1->resource_allocation_enable_RW, enable);
priv1             143 arch/powerpc/platforms/cell/spu_priv1_mmio.c 	return in_be64(&spu->priv1->resource_allocation_enable_RW);
priv1              95 arch/powerpc/platforms/cell/spufs/backing_ops.c 			ctx->csa.priv1.int_stat_class2_RW &=
priv1              97 arch/powerpc/platforms/cell/spufs/backing_ops.c 			ctx->csa.priv1.int_mask_class2_RW |=
priv1             105 arch/powerpc/platforms/cell/spufs/backing_ops.c 			ctx->csa.priv1.int_stat_class2_RW &=
priv1             107 arch/powerpc/platforms/cell/spufs/backing_ops.c 			ctx->csa.priv1.int_mask_class2_RW |=
priv1             132 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.priv1.int_mask_class2_RW |= CLASS2_ENABLE_MAILBOX_INTR;
priv1             162 arch/powerpc/platforms/cell/spufs/backing_ops.c 		ctx->csa.priv1.int_mask_class2_RW |=
priv1             301 arch/powerpc/platforms/cell/spufs/backing_ops.c 	sr1 = csa->priv1.mfc_sr1_RW | MFC_STATE1_MASTER_RUN_CONTROL_MASK;
priv1             302 arch/powerpc/platforms/cell/spufs/backing_ops.c 	csa->priv1.mfc_sr1_RW = sr1;
priv1             312 arch/powerpc/platforms/cell/spufs/backing_ops.c 	sr1 = csa->priv1.mfc_sr1_RW & ~MFC_STATE1_MASTER_RUN_CONTROL_MASK;
priv1             313 arch/powerpc/platforms/cell/spufs/backing_ops.c 	csa->priv1.mfc_sr1_RW = sr1;
priv1             112 arch/powerpc/platforms/cell/spufs/switch.c 		csa->priv1.int_mask_class0_RW = spu_int_mask_get(spu, 0);
priv1             113 arch/powerpc/platforms/cell/spufs/switch.c 		csa->priv1.int_mask_class1_RW = spu_int_mask_get(spu, 1);
priv1             114 arch/powerpc/platforms/cell/spufs/switch.c 		csa->priv1.int_mask_class2_RW = spu_int_mask_get(spu, 2);
priv1             217 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.mfc_sr1_RW = spu_mfc_sr1_get(spu);
priv1             442 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.mfc_tclass_id_RW = spu_mfc_tclass_id_get(spu);
priv1             579 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.resource_allocation_groupID_RW =
priv1             581 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.resource_allocation_enable_RW =
priv1            1233 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv1.resource_allocation_groupID_RW);
priv1            1235 arch/powerpc/platforms/cell/spufs/switch.c 			csa->priv1.resource_allocation_enable_RW);
priv1            1512 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_tclass_id_set(spu, csa->priv1.mfc_tclass_id_RW);
priv1            1694 arch/powerpc/platforms/cell/spufs/switch.c 	spu_mfc_sr1_set(spu, csa->priv1.mfc_sr1_RW);
priv1            1771 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_mask_set(spu, 0, csa->priv1.int_mask_class0_RW);
priv1            1772 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_mask_set(spu, 1, csa->priv1.int_mask_class1_RW);
priv1            1773 arch/powerpc/platforms/cell/spufs/switch.c 	spu_int_mask_set(spu, 2, csa->priv1.int_mask_class2_RW);
priv1            2149 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.mfc_sr1_RW = MFC_STATE1_LOCAL_STORAGE_DECODE_MASK |
priv1            2155 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.int_mask_class0_RW = CLASS0_ENABLE_DMA_ALIGNMENT_INTR |
priv1            2158 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.int_mask_class1_RW = CLASS1_ENABLE_SEGMENT_FAULT_INTR |
priv1            2160 arch/powerpc/platforms/cell/spufs/switch.c 	csa->priv1.int_mask_class2_RW = CLASS2_ENABLE_SPU_STOP_INTR |
priv1            2023 drivers/usb/gadget/function/uvc_configfs.c static int __uvcg_cnt_strm(void *priv1, void *priv2, void *priv3, int n,
priv1            2031 drivers/usb/gadget/function/uvc_configfs.c 		struct uvcg_streaming_header *h = priv1;
priv1            2039 drivers/usb/gadget/function/uvc_configfs.c 		struct uvcg_format *fmt = priv1;
priv1            2058 drivers/usb/gadget/function/uvc_configfs.c 		struct uvcg_frame *frm = priv1;
priv1            2079 drivers/usb/gadget/function/uvc_configfs.c static int __uvcg_fill_strm(void *priv1, void *priv2, void *priv3, int n,
priv1            2092 drivers/usb/gadget/function/uvc_configfs.c 		struct uvcg_streaming_header *h = priv1;
priv1            2107 drivers/usb/gadget/function/uvc_configfs.c 		struct uvcg_format *fmt = priv1;
priv1            2132 drivers/usb/gadget/function/uvc_configfs.c 		struct uvcg_frame *frm = priv1;