pri_val           830 drivers/gpu/drm/i915/i915_drv.h 	u32 pri_val;
pri_val          1212 drivers/gpu/drm/i915/intel_pm.c 			      u32 pri_val);
pri_val          2478 drivers/gpu/drm/i915/intel_pm.c static u32 ilk_wm_fbc(u32 pri_val, u32 horiz_pixels, u8 cpp)
pri_val          2491 drivers/gpu/drm/i915/intel_pm.c 	return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
pri_val          2586 drivers/gpu/drm/i915/intel_pm.c 			      u32 pri_val)
pri_val          2595 drivers/gpu/drm/i915/intel_pm.c 	return ilk_wm_fbc(pri_val, drm_rect_width(&plane_state->base.dst), cpp);
pri_val          2730 drivers/gpu/drm/i915/intel_pm.c 	result->enable = result->pri_val <= max->pri &&
pri_val          2742 drivers/gpu/drm/i915/intel_pm.c 		if (result->pri_val > max->pri)
pri_val          2744 drivers/gpu/drm/i915/intel_pm.c 				      level, result->pri_val, max->pri);
pri_val          2752 drivers/gpu/drm/i915/intel_pm.c 		result->pri_val = min_t(u32, result->pri_val, max->pri);
pri_val          2782 drivers/gpu/drm/i915/intel_pm.c 		result->pri_val = ilk_compute_pri_wm(crtc_state, pristate,
pri_val          2784 drivers/gpu/drm/i915/intel_pm.c 		result->fbc_val = ilk_compute_fbc_wm(crtc_state, pristate, result->pri_val);
pri_val          3227 drivers/gpu/drm/i915/intel_pm.c 		a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
pri_val          3278 drivers/gpu/drm/i915/intel_pm.c 		ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
pri_val          3384 drivers/gpu/drm/i915/intel_pm.c 			(r->pri_val << WM1_LP_SR_SHIFT) |
pri_val          3420 drivers/gpu/drm/i915/intel_pm.c 			(r->pri_val << WM0_PIPE_PLANE_SHIFT) |
pri_val          5860 drivers/gpu/drm/i915/intel_pm.c 		active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;