pri_reg 38 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPWCC, pri_reg 44 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPWCC, pri_reg 50 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPWCC, pri_reg 56 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPZCC, pri_reg 62 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPZCC, pri_reg 68 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPZCC, pri_reg 74 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPZCC, pri_reg 80 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPZCC, pri_reg 86 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPZCC, pri_reg 92 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPRTA, pri_reg 98 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPRTB, pri_reg 104 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPRTB, pri_reg 110 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPRTB, pri_reg 116 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPRTB, pri_reg 122 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPXCC, pri_reg 128 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPXCC, pri_reg 134 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPXCC, pri_reg 140 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPXCC, pri_reg 146 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPXCC, pri_reg 152 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPYCC, pri_reg 158 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPYCC, pri_reg 164 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPYCC, pri_reg 170 drivers/soc/fsl/qe/qe_ic.c .pri_reg = QEIC_CIPYCC, pri_reg 414 drivers/soc/fsl/qe/qe_ic.c if (qe_ic_info[src].pri_reg == 0) pri_reg 417 drivers/soc/fsl/qe/qe_ic.c temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg); pri_reg 427 drivers/soc/fsl/qe/qe_ic.c qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp); pri_reg 445 drivers/soc/fsl/qe/qe_ic.c switch (qe_ic_info[src].pri_reg) { pri_reg 96 drivers/soc/fsl/qe/qe_ic.h u32 pri_reg; /* Group priority register offset */