prcmu_base 22 arch/arm/mach-ux500/pm.c #define PRCM_ARM_WFI_STANDBY (prcmu_base + 0x130) prcmu_base 25 arch/arm/mach-ux500/pm.c #define PRCM_IOCR (prcmu_base + 0x310) prcmu_base 29 arch/arm/mach-ux500/pm.c #define PRCM_A9_MASK_REQ (prcmu_base + 0x328) prcmu_base 32 arch/arm/mach-ux500/pm.c #define PRCM_A9_MASK_ACK (prcmu_base + 0x32c) prcmu_base 33 arch/arm/mach-ux500/pm.c #define PRCM_ARMITMSK31TO0 (prcmu_base + 0x11c) prcmu_base 34 arch/arm/mach-ux500/pm.c #define PRCM_ARMITMSK63TO32 (prcmu_base + 0x120) prcmu_base 35 arch/arm/mach-ux500/pm.c #define PRCM_ARMITMSK95TO64 (prcmu_base + 0x124) prcmu_base 36 arch/arm/mach-ux500/pm.c #define PRCM_ARMITMSK127TO96 (prcmu_base + 0x128) prcmu_base 37 arch/arm/mach-ux500/pm.c #define PRCM_POWER_STATE_VAL (prcmu_base + 0x25C) prcmu_base 38 arch/arm/mach-ux500/pm.c #define PRCM_ARMITVAL31TO0 (prcmu_base + 0x260) prcmu_base 39 arch/arm/mach-ux500/pm.c #define PRCM_ARMITVAL63TO32 (prcmu_base + 0x264) prcmu_base 40 arch/arm/mach-ux500/pm.c #define PRCM_ARMITVAL95TO64 (prcmu_base + 0x268) prcmu_base 41 arch/arm/mach-ux500/pm.c #define PRCM_ARMITVAL127TO96 (prcmu_base + 0x26C) prcmu_base 43 arch/arm/mach-ux500/pm.c static void __iomem *prcmu_base; prcmu_base 182 arch/arm/mach-ux500/pm.c prcmu_base = ioremap(phy_base, size); prcmu_base 183 arch/arm/mach-ux500/pm.c if (!prcmu_base) { prcmu_base 450 drivers/mfd/db8500-prcmu.c static __iomem void *prcmu_base; prcmu_base 628 drivers/mfd/db8500-prcmu.c writel(PRCMU_DSI_CLOCK_SETTING, prcmu_base + PRCM_HDMICLK_MGT); prcmu_base 629 drivers/mfd/db8500-prcmu.c writel(PRCMU_DSI_LP_CLOCK_SETTING, prcmu_base + PRCM_TVCLK_MGT); prcmu_base 630 drivers/mfd/db8500-prcmu.c writel(PRCMU_DPI_CLOCK_SETTING, prcmu_base + PRCM_LCDCLK_MGT); prcmu_base 642 drivers/mfd/db8500-prcmu.c return readl(prcmu_base + reg); prcmu_base 650 drivers/mfd/db8500-prcmu.c writel(value, (prcmu_base + reg)); prcmu_base 660 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + reg); prcmu_base 662 drivers/mfd/db8500-prcmu.c writel(val, (prcmu_base + reg)); prcmu_base 961 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clock_reg[i]); prcmu_base 977 drivers/mfd/db8500-prcmu.c writel(val, prcmu_base + clock_reg[i]); prcmu_base 1331 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clk_mgt[clock].offset); prcmu_base 1338 drivers/mfd/db8500-prcmu.c writel(val, prcmu_base + clk_mgt[clock].offset); prcmu_base 1514 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clk_mgt[clock].offset); prcmu_base 1674 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clk_mgt[clock].offset); prcmu_base 1836 drivers/mfd/db8500-prcmu.c val = readl(prcmu_base + clk_mgt[clock].offset); prcmu_base 1864 drivers/mfd/db8500-prcmu.c writel(val, prcmu_base + clk_mgt[clock].offset); prcmu_base 2743 drivers/mfd/db8500-prcmu.c prcmu_base = ioremap(phy_base, size); prcmu_base 2744 drivers/mfd/db8500-prcmu.c if (!prcmu_base) prcmu_base 3087 drivers/mfd/db8500-prcmu.c prcmu_base = devm_ioremap(&pdev->dev, res->start, resource_size(res)); prcmu_base 3088 drivers/mfd/db8500-prcmu.c if (!prcmu_base) { prcmu_base 51 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ARM_PLLDIVPS (prcmu_base + 0x118) prcmu_base 55 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLARM_LOCKP (prcmu_base + 0x0a8) prcmu_base 58 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ARM_CHGCLKREQ (prcmu_base + 0x114) prcmu_base 62 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLARM_ENABLE (prcmu_base + 0x98) prcmu_base 66 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ARMCLKFIX_MGT (prcmu_base + 0x0) prcmu_base 67 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_A9PL_FORCE_CLKEN (prcmu_base + 0x19C) prcmu_base 68 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_A9_RESETN_CLR (prcmu_base + 0x1f4) prcmu_base 69 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_A9_RESETN_SET (prcmu_base + 0x1f0) prcmu_base 70 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ARM_LS_CLAMP (prcmu_base + 0x30c) prcmu_base 71 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_SRAM_A9 (prcmu_base + 0x308) prcmu_base 77 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MBOX_CPU_VAL (prcmu_base + 0x0fc) prcmu_base 78 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MBOX_CPU_SET (prcmu_base + 0x100) prcmu_base 79 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MBOX_CPU_CLR (prcmu_base + 0x104) prcmu_base 81 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_HOSTACCESS_REQ (prcmu_base + 0x334) prcmu_base 86 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ARM_IT1_CLR (prcmu_base + 0x48C) prcmu_base 87 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ARM_IT1_VAL (prcmu_base + 0x494) prcmu_base 88 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_HOLD_EVT (prcmu_base + 0x174) prcmu_base 90 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MOD_AWAKE_STATUS (prcmu_base + 0x4A0) prcmu_base 95 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ITSTATUS0 (prcmu_base + 0x148) prcmu_base 96 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ITSTATUS1 (prcmu_base + 0x150) prcmu_base 97 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ITSTATUS2 (prcmu_base + 0x158) prcmu_base 98 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ITSTATUS3 (prcmu_base + 0x160) prcmu_base 99 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ITSTATUS4 (prcmu_base + 0x168) prcmu_base 100 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ITSTATUS5 (prcmu_base + 0x484) prcmu_base 101 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ITCLEAR5 (prcmu_base + 0x488) prcmu_base 102 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_ARMIT_MASKXP70_IT (prcmu_base + 0x1018) prcmu_base 105 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_APE_SOFTRST (prcmu_base + 0x228) prcmu_base 108 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MMIP_LS_CLAMP_SET (prcmu_base + 0x420) prcmu_base 109 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_MMIP_LS_CLAMP_CLR (prcmu_base + 0x424) prcmu_base 115 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLSOC0_FREQ (prcmu_base + 0x080) prcmu_base 116 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLSOC1_FREQ (prcmu_base + 0x084) prcmu_base 117 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLARM_FREQ (prcmu_base + 0x088) prcmu_base 118 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLDDR_FREQ (prcmu_base + 0x08C) prcmu_base 128 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLDSI_FREQ (prcmu_base + 0x500) prcmu_base 129 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLDSI_ENABLE (prcmu_base + 0x504) prcmu_base 130 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) prcmu_base 131 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_DSI_PLLOUT_SEL (prcmu_base + 0x530) prcmu_base 132 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_DSITVCLK_DIV (prcmu_base + 0x52C) prcmu_base 133 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_PLLDSI_LOCKP (prcmu_base + 0x508) prcmu_base 134 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_APE_RESETN_SET (prcmu_base + 0x1E4) prcmu_base 135 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_APE_RESETN_CLR (prcmu_base + 0x1E8) prcmu_base 164 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CLKOCR (prcmu_base + 0x1CC) prcmu_base 171 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_EPOD_C_SET (prcmu_base + 0x410) prcmu_base 172 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_SRAM_LS_SLEEP (prcmu_base + 0x304) prcmu_base 175 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_POWER_STATE_SET (prcmu_base + 0x254) prcmu_base 178 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_DSI_SW_RESET (prcmu_base + 0x324) prcmu_base 179 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_GPIOCR (prcmu_base + 0x138) prcmu_base 184 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_SEM (prcmu_base + 0x400) prcmu_base 187 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_TCR (prcmu_base + 0x1C8) prcmu_base 215 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_DDR_SUBSYS_APE_MINBW (prcmu_base + 0x438) prcmu_base 216 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_CGATING_BYPASS (prcmu_base + 0x134) prcmu_base 220 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_RESOUTN_SET (prcmu_base + 0x214) prcmu_base 221 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_RESOUTN_CLR (prcmu_base + 0x218) prcmu_base 224 drivers/mfd/dbx500-prcmu-regs.h #define PRCM_APE_SOFTRST (prcmu_base + 0x228)