PllRange 72 drivers/gpu/drm/amd/powerplay/inc/smu74_discrete.h uint8_t PllRange; PllRange 70 drivers/gpu/drm/amd/powerplay/inc/smu75_discrete.h uint8_t PllRange; PllRange 860 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->PllRange = dividers.ucSclkPllRange; PllRange 876 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->PllRange = i; PllRange 881 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw_int = (uint16_t)((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); PllRange 882 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; PllRange 889 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Pcc_fcw_int = (uint16_t)((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); PllRange 896 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c sclk_setting->Fcw1_int = (uint16_t)((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / ref_clock); PllRange 897 drivers/gpu/drm/amd/powerplay/smumgr/polaris10_smumgr.c temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; PllRange 735 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->PllRange = dividers.ucSclkPllRange; PllRange 751 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c sclk_setting->PllRange = i; PllRange 757 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / PllRange 759 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c temp = clock << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv; PllRange 767 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((pcc_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / PllRange 776 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c ((ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv) / PllRange 778 drivers/gpu/drm/amd/powerplay/smumgr/vegam_smumgr.c temp = ss_target_freq << table->SclkFcwRangeTable[sclk_setting->PllRange].postdiv;