pps_payload        69 drivers/gpu/drm/drm_dsc.c void drm_dsc_pps_payload_pack(struct drm_dsc_picture_parameter_set *pps_payload,
pps_payload        75 drivers/gpu/drm/drm_dsc.c 	BUILD_BUG_ON(sizeof(*pps_payload) !=
pps_payload        78 drivers/gpu/drm/drm_dsc.c 	memset(pps_payload, 0, sizeof(*pps_payload));
pps_payload        81 drivers/gpu/drm/drm_dsc.c 	pps_payload->dsc_version =
pps_payload        88 drivers/gpu/drm/drm_dsc.c 	pps_payload->pps_3 =
pps_payload        93 drivers/gpu/drm/drm_dsc.c 	pps_payload->pps_4 =
pps_payload       102 drivers/gpu/drm/drm_dsc.c 	pps_payload->bits_per_pixel_low =
pps_payload       113 drivers/gpu/drm/drm_dsc.c 	pps_payload->pic_height = cpu_to_be16(dsc_cfg->pic_height);
pps_payload       116 drivers/gpu/drm/drm_dsc.c 	pps_payload->pic_width = cpu_to_be16(dsc_cfg->pic_width);
pps_payload       119 drivers/gpu/drm/drm_dsc.c 	pps_payload->slice_height = cpu_to_be16(dsc_cfg->slice_height);
pps_payload       122 drivers/gpu/drm/drm_dsc.c 	pps_payload->slice_width = cpu_to_be16(dsc_cfg->slice_width);
pps_payload       125 drivers/gpu/drm/drm_dsc.c 	pps_payload->chunk_size = cpu_to_be16(dsc_cfg->slice_chunk_size);
pps_payload       128 drivers/gpu/drm/drm_dsc.c 	pps_payload->initial_xmit_delay_high =
pps_payload       134 drivers/gpu/drm/drm_dsc.c 	pps_payload->initial_xmit_delay_low =
pps_payload       138 drivers/gpu/drm/drm_dsc.c 	pps_payload->initial_dec_delay =
pps_payload       144 drivers/gpu/drm/drm_dsc.c 	pps_payload->initial_scale_value =
pps_payload       148 drivers/gpu/drm/drm_dsc.c 	pps_payload->scale_increment_interval =
pps_payload       152 drivers/gpu/drm/drm_dsc.c 	pps_payload->scale_decrement_interval_high =
pps_payload       158 drivers/gpu/drm/drm_dsc.c 	pps_payload->scale_decrement_interval_low =
pps_payload       164 drivers/gpu/drm/drm_dsc.c 	pps_payload->first_line_bpg_offset =
pps_payload       168 drivers/gpu/drm/drm_dsc.c 	pps_payload->nfl_bpg_offset =
pps_payload       172 drivers/gpu/drm/drm_dsc.c 	pps_payload->slice_bpg_offset =
pps_payload       176 drivers/gpu/drm/drm_dsc.c 	pps_payload->initial_offset =
pps_payload       180 drivers/gpu/drm/drm_dsc.c 	pps_payload->final_offset = cpu_to_be16(dsc_cfg->final_offset);
pps_payload       183 drivers/gpu/drm/drm_dsc.c 	pps_payload->flatness_min_qp = dsc_cfg->flatness_min_qp;
pps_payload       186 drivers/gpu/drm/drm_dsc.c 	pps_payload->flatness_max_qp = dsc_cfg->flatness_max_qp;
pps_payload       189 drivers/gpu/drm/drm_dsc.c 	pps_payload->rc_model_size =
pps_payload       193 drivers/gpu/drm/drm_dsc.c 	pps_payload->rc_edge_factor = DSC_RC_EDGE_FACTOR_CONST;
pps_payload       196 drivers/gpu/drm/drm_dsc.c 	pps_payload->rc_quant_incr_limit0 =
pps_payload       200 drivers/gpu/drm/drm_dsc.c 	pps_payload->rc_quant_incr_limit1 =
pps_payload       204 drivers/gpu/drm/drm_dsc.c 	pps_payload->rc_tgt_offset = DSC_RC_TGT_OFFSET_LO_CONST |
pps_payload       209 drivers/gpu/drm/drm_dsc.c 		pps_payload->rc_buf_thresh[i] =
pps_payload       218 drivers/gpu/drm/drm_dsc.c 		pps_payload->rc_range_parameters[i] =
pps_payload       224 drivers/gpu/drm/drm_dsc.c 		pps_payload->rc_range_parameters[i] =
pps_payload       225 drivers/gpu/drm/drm_dsc.c 			cpu_to_be16(pps_payload->rc_range_parameters[i]);
pps_payload       229 drivers/gpu/drm/drm_dsc.c 	pps_payload->native_422_420 = dsc_cfg->native_422 |
pps_payload       233 drivers/gpu/drm/drm_dsc.c 	pps_payload->second_line_bpg_offset =
pps_payload       237 drivers/gpu/drm/drm_dsc.c 	pps_payload->nsl_bpg_offset =
pps_payload       241 drivers/gpu/drm/drm_dsc.c 	pps_payload->second_line_offset_adj =
pps_payload       895 drivers/gpu/drm/i915/display/intel_vdsc.c 	drm_dsc_pps_payload_pack(&dp_dsc_pps_sdp.pps_payload, vdsc_cfg);
pps_payload       601 include/drm/drm_dsc.h 	struct drm_dsc_picture_parameter_set pps_payload;