pps_idx          15282 drivers/gpu/drm/i915/display/intel_display.c 	int pps_idx;
pps_idx          15295 drivers/gpu/drm/i915/display/intel_display.c 	for (pps_idx = 0; pps_idx < pps_num; pps_idx++) {
pps_idx          15296 drivers/gpu/drm/i915/display/intel_display.c 		u32 val = I915_READ(PP_CONTROL(pps_idx));
pps_idx          15299 drivers/gpu/drm/i915/display/intel_display.c 		I915_WRITE(PP_CONTROL(pps_idx), val);
pps_idx          1025 drivers/gpu/drm/i915/display/intel_dp.c 	int pps_idx = 0;
pps_idx          1030 drivers/gpu/drm/i915/display/intel_dp.c 		pps_idx = bxt_power_sequencer_idx(intel_dp);
pps_idx          1032 drivers/gpu/drm/i915/display/intel_dp.c 		pps_idx = vlv_power_sequencer_pipe(intel_dp);
pps_idx          1034 drivers/gpu/drm/i915/display/intel_dp.c 	regs->pp_ctrl = PP_CONTROL(pps_idx);
pps_idx          1035 drivers/gpu/drm/i915/display/intel_dp.c 	regs->pp_stat = PP_STATUS(pps_idx);
pps_idx          1036 drivers/gpu/drm/i915/display/intel_dp.c 	regs->pp_on = PP_ON_DELAYS(pps_idx);
pps_idx          1037 drivers/gpu/drm/i915/display/intel_dp.c 	regs->pp_off = PP_OFF_DELAYS(pps_idx);
pps_idx          1043 drivers/gpu/drm/i915/display/intel_dp.c 		regs->pp_div = PP_DIVISOR(pps_idx);
pps_idx          4704 drivers/gpu/drm/i915/i915_reg.h #define _MMIO_PPS(pps_idx, reg)		_MMIO(dev_priv->pps_mmio_base -	\
pps_idx          4706 drivers/gpu/drm/i915/i915_reg.h 					      (pps_idx) * 0x100)
pps_idx          4709 drivers/gpu/drm/i915/i915_reg.h #define PP_STATUS(pps_idx)		_MMIO_PPS(pps_idx, _PP_STATUS)
pps_idx          4746 drivers/gpu/drm/i915/i915_reg.h #define PP_CONTROL(pps_idx)		_MMIO_PPS(pps_idx, _PP_CONTROL)
pps_idx          4756 drivers/gpu/drm/i915/i915_reg.h #define PP_ON_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_ON_DELAYS)
pps_idx          4767 drivers/gpu/drm/i915/i915_reg.h #define PP_OFF_DELAYS(pps_idx)		_MMIO_PPS(pps_idx, _PP_OFF_DELAYS)
pps_idx          4772 drivers/gpu/drm/i915/i915_reg.h #define PP_DIVISOR(pps_idx)		_MMIO_PPS(pps_idx, _PP_DIVISOR)