pps 2632 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t pps:1; pps 2670 arch/mips/include/asm/octeon/cvmx-mio-defs.h uint64_t pps:1; pps 31 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps); pps 199 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_log_pps(dsc, &dsc20->reg_vals.pps); pps 215 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c drm_dsc_pps_payload_pack((struct drm_dsc_picture_parameter_set *)dsc_packed_pps, &dsc_reg_vals.pps); pps 216 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_log_pps(dsc, &dsc_reg_vals.pps); pps 253 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c static void dsc_log_pps(struct display_stream_compressor *dsc, struct drm_dsc_config *pps) pps 256 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c int bits_per_pixel = pps->bits_per_pixel; pps 258 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tdsc_version_major %d", pps->dsc_version_major); pps 259 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tdsc_version_minor %d", pps->dsc_version_minor); pps 260 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tbits_per_component %d", pps->bits_per_component); pps 261 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tline_buf_depth %d", pps->line_buf_depth); pps 262 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tblock_pred_enable %d", pps->block_pred_enable); pps 263 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tconvert_rgb %d", pps->convert_rgb); pps 264 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tsimple_422 %d", pps->simple_422); pps 265 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tvbr_enable %d", pps->vbr_enable); pps 267 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tpic_height %d", pps->pic_height); pps 268 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tpic_width %d", pps->pic_width); pps 269 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tslice_height %d", pps->slice_height); pps 270 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tslice_width %d", pps->slice_width); pps 271 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tslice_chunk_size %d", pps->slice_chunk_size); pps 272 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tinitial_xmit_delay %d", pps->initial_xmit_delay); pps 273 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tinitial_dec_delay %d", pps->initial_dec_delay); pps 274 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tinitial_scale_value %d", pps->initial_scale_value); pps 275 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tscale_increment_interval %d", pps->scale_increment_interval); pps 276 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tscale_decrement_interval %d", pps->scale_decrement_interval); pps 277 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tfirst_line_bpg_offset %d", pps->first_line_bpg_offset); pps 278 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tnfl_bpg_offset %d", pps->nfl_bpg_offset); pps 279 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tslice_bpg_offset %d", pps->slice_bpg_offset); pps 280 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tinitial_offset %d", pps->initial_offset); pps 281 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tfinal_offset %d", pps->final_offset); pps 282 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tflatness_min_qp %d", pps->flatness_min_qp); pps 283 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tflatness_max_qp %d", pps->flatness_max_qp); pps 285 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tnative_420 %d", pps->native_420); pps 286 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tnative_422 %d", pps->native_422); pps 287 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tsecond_line_bpg_offset %d", pps->second_line_bpg_offset); pps 288 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tnsl_bpg_offset %d", pps->nsl_bpg_offset); pps 289 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\tsecond_line_offset_adj %d", pps->second_line_offset_adj); pps 290 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_model_size %d", pps->rc_model_size); pps 291 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_edge_factor %d", pps->rc_edge_factor); pps 292 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_quant_incr_limit0 %d", pps->rc_quant_incr_limit0); pps 293 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_quant_incr_limit1 %d", pps->rc_quant_incr_limit1); pps 294 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_tgt_offset_high %d", pps->rc_tgt_offset_high); pps 295 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_tgt_offset_low %d", pps->rc_tgt_offset_low); pps 298 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_buf_thresh[%d] %d", i, pps->rc_buf_thresh[i]); pps 301 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_range_parameters[%d].range_min_qp %d", i, pps->rc_range_params[i].range_min_qp); pps 302 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_range_parameters[%d].range_max_qp %d", i, pps->rc_range_params[i].range_max_qp); pps 303 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DC_LOG_DSC("\trc_range_parameters[%d].range_bpg_offset %d", i, pps->rc_range_params[i].range_bpg_offset); pps 344 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.dsc_version_minor = dsc_cfg->dc_dsc_cfg.version_minor; pps 345 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.pic_width = dsc_cfg->pic_width; pps 346 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.pic_height = dsc_cfg->pic_height; pps 347 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.bits_per_component = dsc_dc_color_depth_to_dsc_bits_per_comp(dsc_cfg->color_depth); pps 348 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.block_pred_enable = dsc_cfg->dc_dsc_cfg.block_pred_enable; pps 349 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.line_buf_depth = dsc_cfg->dc_dsc_cfg.linebuf_depth; pps 350 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->alternate_ich_encoding_en = dsc_reg_vals->pps.dsc_version_minor == 1 ? 0 : 1; pps 354 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.slice_width = dsc_cfg->pic_width / dsc_cfg->dc_dsc_cfg.num_slices_h; pps 355 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.slice_height = dsc_cfg->pic_height / dsc_cfg->dc_dsc_cfg.num_slices_v; pps 357 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c ASSERT(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height); pps 358 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (!(dsc_reg_vals->pps.slice_height * dsc_cfg->dc_dsc_cfg.num_slices_v == dsc_cfg->pic_height)) { pps 365 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32; pps 367 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.bits_per_pixel = dsc_reg_vals->bpp_x32 >> 1; pps 369 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.convert_rgb = dsc_reg_vals->pixel_format == DSC_PIXFMT_RGB ? 1 : 0; pps 370 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.native_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR422); pps 371 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.native_420 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_NATIVE_YCBCR420); pps 372 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_reg_vals->pps.simple_422 = (dsc_reg_vals->pixel_format == DSC_PIXFMT_SIMPLE_YCBCR422); pps 374 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c if (dscc_compute_dsc_parameters(&dsc_reg_vals->pps, &dsc_params)) { pps 382 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c dsc_optc_cfg->slice_width = dsc_reg_vals->pps.slice_width; pps 468 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.dsc_version_minor = 2; pps 469 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.dsc_version_major = 1; pps 470 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.line_buf_depth = 9; pps 471 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.bits_per_component = 8; pps 472 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.block_pred_enable = 1; pps 473 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.slice_chunk_size = 0; pps 474 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.pic_width = 0; pps 475 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.pic_height = 0; pps 476 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.slice_width = 0; pps 477 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.slice_height = 0; pps 478 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.initial_xmit_delay = 170; pps 479 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.initial_dec_delay = 0; pps 480 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.initial_scale_value = 0; pps 481 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.scale_increment_interval = 0; pps 482 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.scale_decrement_interval = 0; pps 483 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.nfl_bpg_offset = 0; pps 484 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.slice_bpg_offset = 0; pps 485 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.nsl_bpg_offset = 0; pps 486 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.initial_offset = 6144; pps 487 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.final_offset = 0; pps 488 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.flatness_min_qp = 3; pps 489 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.flatness_max_qp = 12; pps 490 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_model_size = 8192; pps 491 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_edge_factor = 6; pps 492 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_quant_incr_limit0 = 11; pps 493 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_quant_incr_limit1 = 11; pps 494 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_tgt_offset_low = 3; pps 495 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_tgt_offset_high = 3; pps 506 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps = dsc_params->pps; pps 510 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c reg_vals->pps.rc_buf_thresh[i] = reg_vals->pps.rc_buf_thresh[i] >> 6; pps 530 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSCCIF_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); pps 533 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c PIC_WIDTH, reg_vals->pps.pic_width, pps 534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c PIC_HEIGHT, reg_vals->pps.pic_height); pps 556 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSC_VERSION_MINOR, reg_vals->pps.dsc_version_minor, pps 557 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c LINEBUF_DEPTH, reg_vals->pps.line_buf_depth, pps 558 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c DSCC_PPS_CONFIG0__BITS_PER_COMPONENT, reg_vals->pps.bits_per_component); pps 569 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c BLOCK_PRED_ENABLE, reg_vals->pps.block_pred_enable, pps 572 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c CHUNK_SIZE, reg_vals->pps.slice_chunk_size); pps 575 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c PIC_WIDTH, reg_vals->pps.pic_width, pps 576 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c PIC_HEIGHT, reg_vals->pps.pic_height); pps 579 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SLICE_WIDTH, reg_vals->pps.slice_width, pps 580 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SLICE_HEIGHT, reg_vals->pps.slice_height); pps 583 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INITIAL_XMIT_DELAY, reg_vals->pps.initial_xmit_delay); pps 586 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INITIAL_SCALE_VALUE, reg_vals->pps.initial_scale_value, pps 587 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SCALE_INCREMENT_INTERVAL, reg_vals->pps.scale_increment_interval); pps 590 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SCALE_DECREMENT_INTERVAL, reg_vals->pps.scale_decrement_interval, pps 591 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c FIRST_LINE_BPG_OFFSET, reg_vals->pps.first_line_bpg_offset, pps 592 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SECOND_LINE_BPG_OFFSET, reg_vals->pps.second_line_bpg_offset); pps 595 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c NFL_BPG_OFFSET, reg_vals->pps.nfl_bpg_offset, pps 596 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SLICE_BPG_OFFSET, reg_vals->pps.slice_bpg_offset); pps 599 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c NSL_BPG_OFFSET, reg_vals->pps.nsl_bpg_offset, pps 600 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c SECOND_LINE_OFFSET_ADJ, reg_vals->pps.second_line_offset_adj); pps 603 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c INITIAL_OFFSET, reg_vals->pps.initial_offset, pps 604 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c FINAL_OFFSET, reg_vals->pps.final_offset); pps 607 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c FLATNESS_MIN_QP, reg_vals->pps.flatness_min_qp, pps 608 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c FLATNESS_MAX_QP, reg_vals->pps.flatness_max_qp, pps 609 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_MODEL_SIZE, reg_vals->pps.rc_model_size); pps 612 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_EDGE_FACTOR, reg_vals->pps.rc_edge_factor, pps 613 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_QUANT_INCR_LIMIT0, reg_vals->pps.rc_quant_incr_limit0, pps 614 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_QUANT_INCR_LIMIT1, reg_vals->pps.rc_quant_incr_limit1, pps 615 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_TGT_OFFSET_LO, reg_vals->pps.rc_tgt_offset_low, pps 616 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_TGT_OFFSET_HI, reg_vals->pps.rc_tgt_offset_high); pps 619 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH0, reg_vals->pps.rc_buf_thresh[0], pps 620 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH1, reg_vals->pps.rc_buf_thresh[1], pps 621 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH2, reg_vals->pps.rc_buf_thresh[2], pps 622 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH3, reg_vals->pps.rc_buf_thresh[3]); pps 625 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH4, reg_vals->pps.rc_buf_thresh[4], pps 626 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH5, reg_vals->pps.rc_buf_thresh[5], pps 627 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH6, reg_vals->pps.rc_buf_thresh[6], pps 628 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH7, reg_vals->pps.rc_buf_thresh[7]); pps 631 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH8, reg_vals->pps.rc_buf_thresh[8], pps 632 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH9, reg_vals->pps.rc_buf_thresh[9], pps 633 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH10, reg_vals->pps.rc_buf_thresh[10], pps 634 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH11, reg_vals->pps.rc_buf_thresh[11]); pps 637 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH12, reg_vals->pps.rc_buf_thresh[12], pps 638 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RC_BUF_THRESH13, reg_vals->pps.rc_buf_thresh[13], pps 639 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP0, reg_vals->pps.rc_range_params[0].range_min_qp, pps 640 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP0, reg_vals->pps.rc_range_params[0].range_max_qp, pps 641 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET0, reg_vals->pps.rc_range_params[0].range_bpg_offset); pps 644 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP1, reg_vals->pps.rc_range_params[1].range_min_qp, pps 645 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP1, reg_vals->pps.rc_range_params[1].range_max_qp, pps 646 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET1, reg_vals->pps.rc_range_params[1].range_bpg_offset, pps 647 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP2, reg_vals->pps.rc_range_params[2].range_min_qp, pps 648 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP2, reg_vals->pps.rc_range_params[2].range_max_qp, pps 649 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET2, reg_vals->pps.rc_range_params[2].range_bpg_offset); pps 652 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP3, reg_vals->pps.rc_range_params[3].range_min_qp, pps 653 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP3, reg_vals->pps.rc_range_params[3].range_max_qp, pps 654 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET3, reg_vals->pps.rc_range_params[3].range_bpg_offset, pps 655 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP4, reg_vals->pps.rc_range_params[4].range_min_qp, pps 656 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP4, reg_vals->pps.rc_range_params[4].range_max_qp, pps 657 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET4, reg_vals->pps.rc_range_params[4].range_bpg_offset); pps 660 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP5, reg_vals->pps.rc_range_params[5].range_min_qp, pps 661 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP5, reg_vals->pps.rc_range_params[5].range_max_qp, pps 662 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET5, reg_vals->pps.rc_range_params[5].range_bpg_offset, pps 663 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP6, reg_vals->pps.rc_range_params[6].range_min_qp, pps 664 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP6, reg_vals->pps.rc_range_params[6].range_max_qp, pps 665 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET6, reg_vals->pps.rc_range_params[6].range_bpg_offset); pps 668 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP7, reg_vals->pps.rc_range_params[7].range_min_qp, pps 669 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP7, reg_vals->pps.rc_range_params[7].range_max_qp, pps 670 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET7, reg_vals->pps.rc_range_params[7].range_bpg_offset, pps 671 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP8, reg_vals->pps.rc_range_params[8].range_min_qp, pps 672 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP8, reg_vals->pps.rc_range_params[8].range_max_qp, pps 673 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET8, reg_vals->pps.rc_range_params[8].range_bpg_offset); pps 676 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP9, reg_vals->pps.rc_range_params[9].range_min_qp, pps 677 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP9, reg_vals->pps.rc_range_params[9].range_max_qp, pps 678 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET9, reg_vals->pps.rc_range_params[9].range_bpg_offset, pps 679 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP10, reg_vals->pps.rc_range_params[10].range_min_qp, pps 680 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP10, reg_vals->pps.rc_range_params[10].range_max_qp, pps 681 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET10, reg_vals->pps.rc_range_params[10].range_bpg_offset); pps 684 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP11, reg_vals->pps.rc_range_params[11].range_min_qp, pps 685 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP11, reg_vals->pps.rc_range_params[11].range_max_qp, pps 686 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET11, reg_vals->pps.rc_range_params[11].range_bpg_offset, pps 687 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP12, reg_vals->pps.rc_range_params[12].range_min_qp, pps 688 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP12, reg_vals->pps.rc_range_params[12].range_max_qp, pps 689 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET12, reg_vals->pps.rc_range_params[12].range_bpg_offset); pps 692 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP13, reg_vals->pps.rc_range_params[13].range_min_qp, pps 693 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP13, reg_vals->pps.rc_range_params[13].range_max_qp, pps 694 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET13, reg_vals->pps.rc_range_params[13].range_bpg_offset, pps 695 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MIN_QP14, reg_vals->pps.rc_range_params[14].range_min_qp, pps 696 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_MAX_QP14, reg_vals->pps.rc_range_params[14].range_max_qp, pps 697 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c RANGE_BPG_OFFSET14, reg_vals->pps.rc_range_params[14].range_bpg_offset); pps 709 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.c temp_int = reg_vals->pps.initial_dec_delay; pps 534 drivers/gpu/drm/amd/display/dc/dcn20/dcn20_dsc.h struct drm_dsc_config pps; pps 43 drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h struct drm_dsc_config pps; pps 50 drivers/gpu/drm/amd/display/dc/dsc/dscc_types.h int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_parameters *dsc_params); pps 102 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c int dscc_compute_dsc_parameters(const struct drm_dsc_config *pps, struct dsc_parameters *dsc_params) pps 104 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c enum colour_mode mode = pps->convert_rgb ? CM_RGB : pps 105 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c (pps->simple_422 ? CM_444 : pps 106 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c (pps->native_422 ? CM_422 : pps 107 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c pps->native_420 ? CM_420 : CM_444)); pps 108 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c enum bits_per_comp bpc = (pps->bits_per_component == 8) ? BPC_8 : pps 109 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c (pps->bits_per_component == 10) ? BPC_10 : BPC_12; pps 110 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c float bpp = ((float) pps->bits_per_pixel / 16.0); pps 111 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c int slice_width = pps->slice_width; pps 112 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c int slice_height = pps->slice_height; pps 120 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c if (pps->native_422 || pps->native_420) pps 128 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c if (pps->native_422 || pps->native_420) pps 131 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c calc_rc_params(&rc, mode, bpc, bpp, slice_width, slice_height, pps->dsc_version_minor); pps 132 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_params->pps = *pps; pps 133 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_params->pps.initial_scale_value = 8 * rc.rc_model_size / (rc.rc_model_size - rc.initial_fullness_offset); pps 135 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c copy_pps_fields(&dsc_cfg, &dsc_params->pps); pps 138 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c dsc_cfg.mux_word_size = dsc_params->pps.bits_per_component <= 10 ? 48 : 64; pps 142 drivers/gpu/drm/amd/display/dc/dsc/rc_calc_dpi.c copy_pps_fields(&dsc_params->pps, &dsc_cfg); pps 80 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.pps = *edp_pps; pps 83 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.pps.t1_t3, dev_priv->edp.pps.t8, pps 84 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.pps.t9, dev_priv->edp.pps.t10, pps 85 drivers/gpu/drm/gma500/intel_bios.c dev_priv->edp.pps.t11_t12); pps 607 drivers/gpu/drm/gma500/psb_drv.h struct edp_power_seq pps; pps 595 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.edp.pps = *edp_pps; pps 842 drivers/gpu/drm/i915/display/intel_bios.c const struct mipi_pps_data *pps; pps 875 drivers/gpu/drm/i915/display/intel_bios.c pps = &start->pps[panel_type]; pps 882 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.pps = kmemdup(pps, sizeof(struct mipi_pps_data), GFP_KERNEL); pps 883 drivers/gpu/drm/i915/display/intel_bios.c if (!dev_priv->vbt.dsi.pps) { pps 1914 drivers/gpu/drm/i915/display/intel_bios.c kfree(dev_priv->vbt.dsi.pps); pps 1915 drivers/gpu/drm/i915/display/intel_bios.c dev_priv->vbt.dsi.pps = NULL; pps 6453 drivers/gpu/drm/i915/display/intel_dp.c vbt = dev_priv->vbt.edp.pps; pps 576 drivers/gpu/drm/i915/display/intel_dsi_vbt.c struct mipi_pps_data *pps = dev_priv->vbt.dsi.pps; pps 661 drivers/gpu/drm/i915/display/intel_dsi_vbt.c intel_dsi->backlight_off_delay = pps->bl_disable_delay / 10; pps 662 drivers/gpu/drm/i915/display/intel_dsi_vbt.c intel_dsi->backlight_on_delay = pps->bl_enable_delay / 10; pps 663 drivers/gpu/drm/i915/display/intel_dsi_vbt.c intel_dsi->panel_on_delay = pps->panel_on_delay / 10; pps 664 drivers/gpu/drm/i915/display/intel_dsi_vbt.c intel_dsi->panel_off_delay = pps->panel_off_delay / 10; pps 665 drivers/gpu/drm/i915/display/intel_dsi_vbt.c intel_dsi->panel_pwr_cycle_delay = pps->panel_power_cycle_delay / 10; pps 155 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_lvds_pps *pps) pps 159 drivers/gpu/drm/i915/display/intel_lvds.c pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; pps 162 drivers/gpu/drm/i915/display/intel_lvds.c pps->port = REG_FIELD_GET(PANEL_PORT_SELECT_MASK, val); pps 163 drivers/gpu/drm/i915/display/intel_lvds.c pps->t1_t2 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, val); pps 164 drivers/gpu/drm/i915/display/intel_lvds.c pps->t5 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, val); pps 167 drivers/gpu/drm/i915/display/intel_lvds.c pps->t3 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, val); pps 168 drivers/gpu/drm/i915/display/intel_lvds.c pps->tx = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, val); pps 171 drivers/gpu/drm/i915/display/intel_lvds.c pps->divider = REG_FIELD_GET(PP_REFERENCE_DIVIDER_MASK, val); pps 181 drivers/gpu/drm/i915/display/intel_lvds.c pps->t4 = val * 1000; pps 184 drivers/gpu/drm/i915/display/intel_lvds.c pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { pps 188 drivers/gpu/drm/i915/display/intel_lvds.c pps->t1_t2 = 40 * 10; pps 189 drivers/gpu/drm/i915/display/intel_lvds.c pps->t5 = 200 * 10; pps 191 drivers/gpu/drm/i915/display/intel_lvds.c pps->t3 = 35 * 10; pps 192 drivers/gpu/drm/i915/display/intel_lvds.c pps->tx = 200 * 10; pps 197 drivers/gpu/drm/i915/display/intel_lvds.c pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, pps 198 drivers/gpu/drm/i915/display/intel_lvds.c pps->divider, pps->port, pps->powerdown_on_reset); pps 202 drivers/gpu/drm/i915/display/intel_lvds.c struct intel_lvds_pps *pps) pps 208 drivers/gpu/drm/i915/display/intel_lvds.c if (pps->powerdown_on_reset) pps 213 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_PORT_SELECT_MASK, pps->port) | pps 214 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, pps->t1_t2) | pps 215 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, pps->t5)); pps 218 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, pps->t3) | pps 219 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, pps->tx)); pps 222 drivers/gpu/drm/i915/display/intel_lvds.c REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, pps->divider) | pps 224 drivers/gpu/drm/i915/display/intel_lvds.c DIV_ROUND_UP(pps->t4, 1000) + 1)); pps 799 drivers/gpu/drm/i915/display/intel_vbt_defs.h struct mipi_pps_data pps[MAX_MIPI_CONFIGURATIONS]; pps 776 drivers/gpu/drm/i915/i915_drv.h struct edp_power_seq pps; pps 803 drivers/gpu/drm/i915/i915_drv.h struct mipi_pps_data *pps; pps 502 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h u64 pps; pps 65 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c u64 pps; pps 76 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c pps = params->frame_rate; pps 77 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c pps *= params->width; pps 78 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c pps *= params->height; pps 84 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c if (pps <= tbl->cfg[i].pps) { pps 93 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c pps, *ot_lim); pps 331 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c (u64 *)&cfg->pps); pps 345 drivers/gpu/drm/msm/disp/dpu1/dpu_vbif.c (u64 *)&cfg->pps); pps 4216 drivers/gpu/drm/omapdrm/dss/dsi.c int bl, wc, pps, tot; pps 4219 drivers/gpu/drm/omapdrm/dss/dsi.c pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ pps 4221 drivers/gpu/drm/omapdrm/dss/dsi.c tot = bl + pps; pps 4229 drivers/gpu/drm/omapdrm/dss/dsi.c t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, pps 4230 drivers/gpu/drm/omapdrm/dss/dsi.c bl, pps, tot, pps 4235 drivers/gpu/drm/omapdrm/dss/dsi.c TO_DSI_T(pps), pps 4239 drivers/gpu/drm/omapdrm/dss/dsi.c TO_DSI_T(pps), pps 111 drivers/infiniband/core/security.c static int check_qp_port_pkey_settings(struct ib_ports_pkeys *pps, pps 118 drivers/infiniband/core/security.c if (!pps) pps 121 drivers/infiniband/core/security.c if (pps->main.state != IB_PORT_PKEY_NOT_VALID) { pps 122 drivers/infiniband/core/security.c ret = get_pkey_and_subnet_prefix(&pps->main, pps 135 drivers/infiniband/core/security.c if (pps->alt.state != IB_PORT_PKEY_NOT_VALID) { pps 136 drivers/infiniband/core/security.c ret = get_pkey_and_subnet_prefix(&pps->alt, pps 474 drivers/net/dsa/mv88e6xxx/ptp.c chip->ptp_clock_info.pps = 0; pps 13934 drivers/net/ethernet/broadcom/bnx2x/bnx2x_main.c bp->ptp_clock_info.pps = 0; pps 6345 drivers/net/ethernet/broadcom/tg3.c .pps = 0, pps 192 drivers/net/ethernet/cadence/macb_ptp.c .pps = 1, pps 264 drivers/net/ethernet/cavium/common/cavium_ptp.c .pps = 0, pps 1686 drivers/net/ethernet/cavium/liquidio/lio_main.c lio->ptp_info.pps = 0; pps 405 drivers/net/ethernet/chelsio/cxgb4/cxgb4_ptp.c .pps = 0, pps 2146 drivers/net/ethernet/emulex/benet/be_main.c u32 pps, delta; pps 2184 drivers/net/ethernet/emulex/benet/be_main.c pps = (((u32)(rx_pkts - aic->rx_pkts_prev) * 1000) / delta) + pps 2186 drivers/net/ethernet/emulex/benet/be_main.c eqd = (pps / 15000) << 2; pps 67 drivers/net/ethernet/freescale/dpaa2/dpaa2-ptp.c .pps = 1, pps 21 drivers/net/ethernet/freescale/enetc/enetc_ptp.c .pps = 1, pps 587 drivers/net/ethernet/freescale/fec_ptp.c fep->ptp_caps.pps = 1; pps 262 drivers/net/ethernet/intel/e1000e/ptp.c .pps = 0, pps 708 drivers/net/ethernet/intel/i40e/i40e_ptp.c pf->ptp_caps.pps = 0; pps 6457 drivers/net/ethernet/intel/igb/igb_main.c if (adapter->ptp_caps.pps) pps 1188 drivers/net/ethernet/intel/igb/igb_ptp.c adapter->ptp_caps.pps = 0; pps 1207 drivers/net/ethernet/intel/igb/igb_ptp.c adapter->ptp_caps.pps = 0; pps 1234 drivers/net/ethernet/intel/igb/igb_ptp.c adapter->ptp_caps.pps = 1; pps 1361 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c adapter->ptp_caps.pps = 1; pps 1378 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c adapter->ptp_caps.pps = 0; pps 1394 drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.c adapter->ptp_caps.pps = 1; pps 239 drivers/net/ethernet/mellanox/mlx4/en_clock.c .pps = 0, pps 405 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c .pps = 0, pps 426 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c clock->ptp_info.pps = 1; pps 473 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c int pin = eqe->data.pps.pin; pps 481 drivers/net/ethernet/mellanox/mlx5/core/lib/clock.c be64_to_cpu(eqe->data.pps.time_stamp)); pps 204 drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.h #define MLX5_PPS_CAP(mdev) (MLX5_CAP_GEN((mdev), pps) && \ pps 910 drivers/net/ethernet/microchip/lan743x_ptp.c ptp->ptp_clock_info.pps = 0; pps 1973 drivers/net/ethernet/mscc/ocelot.c .pps = 0, pps 498 drivers/net/ethernet/qlogic/qede/qede_ptp.c ptp->clock_info.pps = 0; pps 1433 drivers/net/ethernet/sfc/ptp.c .pps = 1, pps 233 drivers/net/ethernet/stmicro/stmmac/stmmac.h struct stmmac_pps_cfg pps[STMMAC_PPS_MAX]; pps 147 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c cfg = &priv->pps[rq->perout.index]; pps 177 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c .pps = 0, pps 198 drivers/net/ethernet/stmicro/stmmac/stmmac_ptp.c priv->pps[i].available = true; pps 321 drivers/net/ethernet/ti/cpts.c .pps = 0, pps 1052 drivers/net/phy/dp83640.c clock->caps.pps = 0; pps 175 drivers/net/wireless/intel/iwlegacy/3945-rs.c u32 packet_count, duration, pps; pps 196 drivers/net/wireless/intel/iwlegacy/3945-rs.c pps = (packet_count * 1000) / duration; pps 198 drivers/net/wireless/intel/iwlegacy/3945-rs.c pps = 0; pps 200 drivers/net/wireless/intel/iwlegacy/3945-rs.c if (pps) { pps 201 drivers/net/wireless/intel/iwlegacy/3945-rs.c duration = (IL_AVERAGE_PACKETS * 1000) / pps; pps 30 drivers/pps/clients/pps-gpio.c struct pps_device *pps; /* PPS source device */ pps 59 drivers/pps/clients/pps-gpio.c pps_event(info->pps, &ts, PPS_CAPTUREASSERT, data); pps 63 drivers/pps/clients/pps-gpio.c pps_event(info->pps, &ts, PPS_CAPTURECLEAR, data); pps 69 drivers/pps/clients/pps-gpio.c static void pps_gpio_echo(struct pps_device *pps, int event, void *data) pps 76 drivers/pps/clients/pps-gpio.c if (pps->params.mode & PPS_ECHOASSERT) pps 81 drivers/pps/clients/pps-gpio.c if (pps->params.mode & PPS_ECHOCLEAR) pps 87 drivers/pps/clients/pps-gpio.c if (info->pps->params.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) { pps 219 drivers/pps/clients/pps-gpio.c data->pps = pps_register_source(&data->info, pps_default_params); pps 220 drivers/pps/clients/pps-gpio.c if (IS_ERR(data->pps)) { pps 223 drivers/pps/clients/pps-gpio.c return PTR_ERR(data->pps); pps 230 drivers/pps/clients/pps-gpio.c pps_unregister_source(data->pps); pps 235 drivers/pps/clients/pps-gpio.c dev_info(data->pps->dev, "Registered IRQ %d as PPS source\n", pps 245 drivers/pps/clients/pps-gpio.c pps_unregister_source(data->pps); pps 21 drivers/pps/clients/pps-ktimer.c static struct pps_device *pps; pps 35 drivers/pps/clients/pps-ktimer.c pps_event(pps, &ts, PPS_CAPTUREASSERT, NULL); pps 59 drivers/pps/clients/pps-ktimer.c dev_info(pps->dev, "ktimer PPS source unregistered\n"); pps 62 drivers/pps/clients/pps-ktimer.c pps_unregister_source(pps); pps 67 drivers/pps/clients/pps-ktimer.c pps = pps_register_source(&pps_ktimer_info, pps 69 drivers/pps/clients/pps-ktimer.c if (IS_ERR(pps)) { pps 71 drivers/pps/clients/pps-ktimer.c return PTR_ERR(pps); pps 77 drivers/pps/clients/pps-ktimer.c dev_info(pps->dev, "ktimer PPS source registered\n"); pps 20 drivers/pps/clients/pps-ldisc.c struct pps_device *pps; pps 25 drivers/pps/clients/pps-ldisc.c pps = pps_lookup_dev(tty); pps 30 drivers/pps/clients/pps-ldisc.c if (WARN_ON_ONCE(pps == NULL)) pps 34 drivers/pps/clients/pps-ldisc.c pps_event(pps, &ts, status ? PPS_CAPTUREASSERT : pps 37 drivers/pps/clients/pps-ldisc.c dev_dbg(pps->dev, "PPS %s at %lu\n", pps 48 drivers/pps/clients/pps-ldisc.c struct pps_device *pps; pps 59 drivers/pps/clients/pps-ldisc.c pps = pps_register_source(&info, PPS_CAPTUREBOTH | \ pps 61 drivers/pps/clients/pps-ldisc.c if (IS_ERR(pps)) { pps 63 drivers/pps/clients/pps-ldisc.c return PTR_ERR(pps); pps 65 drivers/pps/clients/pps-ldisc.c pps->lookup_cookie = tty; pps 74 drivers/pps/clients/pps-ldisc.c dev_info(pps->dev, "source \"%s\" added\n", info.path); pps 79 drivers/pps/clients/pps-ldisc.c pps_unregister_source(pps); pps 87 drivers/pps/clients/pps-ldisc.c struct pps_device *pps = pps_lookup_dev(tty); pps 91 drivers/pps/clients/pps-ldisc.c if (WARN_ON(!pps)) pps 94 drivers/pps/clients/pps-ldisc.c dev_info(pps->dev, "removed\n"); pps 95 drivers/pps/clients/pps-ldisc.c pps_unregister_source(pps); pps 43 drivers/pps/clients/pps_parport.c struct pps_device *pps; /* PPS device */ pps 86 drivers/pps/clients/pps_parport.c dev_err(dev->pps->dev, "lost the signal\n"); pps 103 drivers/pps/clients/pps_parport.c dev_err(dev->pps->dev, "disabled clear edge capture after %d" pps 111 drivers/pps/clients/pps_parport.c pps_event(dev->pps, &ts_assert, pps 117 drivers/pps/clients/pps_parport.c pps_event(dev->pps, &ts_assert, pps 120 drivers/pps/clients/pps_parport.c pps_event(dev->pps, &ts_clear, pps 166 drivers/pps/clients/pps_parport.c device->pps = pps_register_source(&info, pps 168 drivers/pps/clients/pps_parport.c if (IS_ERR(device->pps)) { pps 204 drivers/pps/clients/pps_parport.c pps_unregister_source(device->pps); pps 41 drivers/pps/kapi.c static void pps_echo_client_default(struct pps_device *pps, int event, pps 44 drivers/pps/kapi.c dev_info(pps->dev, "echo %s %s\n", pps 68 drivers/pps/kapi.c struct pps_device *pps; pps 86 drivers/pps/kapi.c pps = kzalloc(sizeof(struct pps_device), GFP_KERNEL); pps 87 drivers/pps/kapi.c if (pps == NULL) { pps 95 drivers/pps/kapi.c pps->params.api_version = PPS_API_VERS; pps 96 drivers/pps/kapi.c pps->params.mode = default_params; pps 97 drivers/pps/kapi.c pps->info = *info; pps 100 drivers/pps/kapi.c if ((pps->info.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR)) && pps 101 drivers/pps/kapi.c pps->info.echo == NULL) pps 102 drivers/pps/kapi.c pps->info.echo = pps_echo_client_default; pps 104 drivers/pps/kapi.c init_waitqueue_head(&pps->queue); pps 105 drivers/pps/kapi.c spin_lock_init(&pps->lock); pps 108 drivers/pps/kapi.c err = pps_register_cdev(pps); pps 115 drivers/pps/kapi.c dev_info(pps->dev, "new PPS source %s\n", info->name); pps 117 drivers/pps/kapi.c return pps; pps 120 drivers/pps/kapi.c kfree(pps); pps 136 drivers/pps/kapi.c void pps_unregister_source(struct pps_device *pps) pps 138 drivers/pps/kapi.c pps_kc_remove(pps); pps 139 drivers/pps/kapi.c pps_unregister_cdev(pps); pps 159 drivers/pps/kapi.c void pps_event(struct pps_device *pps, struct pps_event_time *ts, int event, pps 169 drivers/pps/kapi.c dev_dbg(pps->dev, "PPS event at %lld.%09ld\n", pps 174 drivers/pps/kapi.c spin_lock_irqsave(&pps->lock, flags); pps 177 drivers/pps/kapi.c if ((pps->params.mode & (PPS_ECHOASSERT | PPS_ECHOCLEAR))) pps 178 drivers/pps/kapi.c pps->info.echo(pps, event, data); pps 181 drivers/pps/kapi.c pps->current_mode = pps->params.mode; pps 182 drivers/pps/kapi.c if (event & pps->params.mode & PPS_CAPTUREASSERT) { pps 184 drivers/pps/kapi.c if (pps->params.mode & PPS_OFFSETASSERT) pps 186 drivers/pps/kapi.c &pps->params.assert_off_tu); pps 189 drivers/pps/kapi.c pps->assert_tu = ts_real; pps 190 drivers/pps/kapi.c pps->assert_sequence++; pps 191 drivers/pps/kapi.c dev_dbg(pps->dev, "capture assert seq #%u\n", pps 192 drivers/pps/kapi.c pps->assert_sequence); pps 196 drivers/pps/kapi.c if (event & pps->params.mode & PPS_CAPTURECLEAR) { pps 198 drivers/pps/kapi.c if (pps->params.mode & PPS_OFFSETCLEAR) pps 200 drivers/pps/kapi.c &pps->params.clear_off_tu); pps 203 drivers/pps/kapi.c pps->clear_tu = ts_real; pps 204 drivers/pps/kapi.c pps->clear_sequence++; pps 205 drivers/pps/kapi.c dev_dbg(pps->dev, "capture clear seq #%u\n", pps 206 drivers/pps/kapi.c pps->clear_sequence); pps 211 drivers/pps/kapi.c pps_kc_event(pps, ts, event); pps 215 drivers/pps/kapi.c pps->last_ev++; pps 216 drivers/pps/kapi.c wake_up_interruptible_all(&pps->queue); pps 218 drivers/pps/kapi.c kill_fasync(&pps->async_queue, SIGIO, POLL_IN); pps 221 drivers/pps/kapi.c spin_unlock_irqrestore(&pps->lock, flags); pps 36 drivers/pps/kc.c int pps_kc_bind(struct pps_device *pps, struct pps_bind_args *bind_args) pps 42 drivers/pps/kc.c if (pps_kc_hardpps_dev == pps) { pps 46 drivers/pps/kc.c dev_info(pps->dev, "unbound kernel" pps 50 drivers/pps/kc.c dev_err(pps->dev, "selected kernel consumer" pps 56 drivers/pps/kc.c pps_kc_hardpps_dev == pps) { pps 58 drivers/pps/kc.c pps_kc_hardpps_dev = pps; pps 60 drivers/pps/kc.c dev_info(pps->dev, "bound kernel consumer: " pps 64 drivers/pps/kc.c dev_err(pps->dev, "another kernel consumer" pps 79 drivers/pps/kc.c void pps_kc_remove(struct pps_device *pps) pps 82 drivers/pps/kc.c if (pps == pps_kc_hardpps_dev) { pps 86 drivers/pps/kc.c dev_info(pps->dev, "unbound kernel consumer" pps 99 drivers/pps/kc.c void pps_kc_event(struct pps_device *pps, struct pps_event_time *ts, pps 106 drivers/pps/kc.c if (pps == pps_kc_hardpps_dev && event & pps_kc_hardpps_mode) pps 16 drivers/pps/kc.h extern int pps_kc_bind(struct pps_device *pps, pps 18 drivers/pps/kc.h extern void pps_kc_remove(struct pps_device *pps); pps 19 drivers/pps/kc.h extern void pps_kc_event(struct pps_device *pps, pps 25 drivers/pps/kc.h static inline int pps_kc_bind(struct pps_device *pps, pps 27 drivers/pps/kc.h static inline void pps_kc_remove(struct pps_device *pps) {} pps 28 drivers/pps/kc.h static inline void pps_kc_event(struct pps_device *pps, pps 40 drivers/pps/pps.c struct pps_device *pps = file->private_data; pps 42 drivers/pps/pps.c poll_wait(file, &pps->queue, wait); pps 49 drivers/pps/pps.c struct pps_device *pps = file->private_data; pps 50 drivers/pps/pps.c return fasync_helper(fd, file, on, &pps->async_queue); pps 53 drivers/pps/pps.c static int pps_cdev_pps_fetch(struct pps_device *pps, struct pps_fdata *fdata) pps 55 drivers/pps/pps.c unsigned int ev = pps->last_ev; pps 60 drivers/pps/pps.c err = wait_event_interruptible(pps->queue, pps 61 drivers/pps/pps.c ev != pps->last_ev); pps 65 drivers/pps/pps.c dev_dbg(pps->dev, "timeout %lld.%09d\n", pps 73 drivers/pps/pps.c pps->queue, pps 74 drivers/pps/pps.c ev != pps->last_ev, pps 83 drivers/pps/pps.c dev_dbg(pps->dev, "pending signal caught\n"); pps 93 drivers/pps/pps.c struct pps_device *pps = file->private_data; pps 101 drivers/pps/pps.c dev_dbg(pps->dev, "PPS_GETPARAMS\n"); pps 103 drivers/pps/pps.c spin_lock_irq(&pps->lock); pps 106 drivers/pps/pps.c params = pps->params; pps 108 drivers/pps/pps.c spin_unlock_irq(&pps->lock); pps 117 drivers/pps/pps.c dev_dbg(pps->dev, "PPS_SETPARAMS\n"); pps 127 drivers/pps/pps.c dev_dbg(pps->dev, "capture mode unspecified (%x)\n", pps 133 drivers/pps/pps.c if ((params.mode & ~pps->info.mode) != 0) { pps 134 drivers/pps/pps.c dev_dbg(pps->dev, "unsupported capabilities (%x)\n", pps 139 drivers/pps/pps.c spin_lock_irq(&pps->lock); pps 142 drivers/pps/pps.c pps->params = params; pps 147 drivers/pps/pps.c dev_dbg(pps->dev, "time format unspecified (%x)\n", pps 149 drivers/pps/pps.c pps->params.mode |= PPS_TSFMT_TSPEC; pps 151 drivers/pps/pps.c if (pps->info.mode & PPS_CANWAIT) pps 152 drivers/pps/pps.c pps->params.mode |= PPS_CANWAIT; pps 153 drivers/pps/pps.c pps->params.api_version = PPS_API_VERS; pps 160 drivers/pps/pps.c pps->params.assert_off_tu.flags = 0; pps 161 drivers/pps/pps.c pps->params.clear_off_tu.flags = 0; pps 163 drivers/pps/pps.c spin_unlock_irq(&pps->lock); pps 168 drivers/pps/pps.c dev_dbg(pps->dev, "PPS_GETCAP\n"); pps 170 drivers/pps/pps.c err = put_user(pps->info.mode, iuarg); pps 179 drivers/pps/pps.c dev_dbg(pps->dev, "PPS_FETCH\n"); pps 185 drivers/pps/pps.c err = pps_cdev_pps_fetch(pps, &fdata); pps 190 drivers/pps/pps.c spin_lock_irq(&pps->lock); pps 192 drivers/pps/pps.c fdata.info.assert_sequence = pps->assert_sequence; pps 193 drivers/pps/pps.c fdata.info.clear_sequence = pps->clear_sequence; pps 194 drivers/pps/pps.c fdata.info.assert_tu = pps->assert_tu; pps 195 drivers/pps/pps.c fdata.info.clear_tu = pps->clear_tu; pps 196 drivers/pps/pps.c fdata.info.current_mode = pps->current_mode; pps 198 drivers/pps/pps.c spin_unlock_irq(&pps->lock); pps 209 drivers/pps/pps.c dev_dbg(pps->dev, "PPS_KC_BIND\n"); pps 220 drivers/pps/pps.c if ((bind_args.edge & ~pps->info.mode) != 0) { pps 221 drivers/pps/pps.c dev_err(pps->dev, "unsupported capabilities (%x)\n", pps 230 drivers/pps/pps.c dev_err(pps->dev, "invalid kernel consumer bind" pps 235 drivers/pps/pps.c err = pps_kc_bind(pps, &bind_args); pps 252 drivers/pps/pps.c struct pps_device *pps = file->private_data; pps 262 drivers/pps/pps.c dev_dbg(pps->dev, "PPS_FETCH\n"); pps 271 drivers/pps/pps.c err = pps_cdev_pps_fetch(pps, &fdata); pps 276 drivers/pps/pps.c spin_lock_irq(&pps->lock); pps 278 drivers/pps/pps.c compat.info.assert_sequence = pps->assert_sequence; pps 279 drivers/pps/pps.c compat.info.clear_sequence = pps->clear_sequence; pps 280 drivers/pps/pps.c compat.info.current_mode = pps->current_mode; pps 282 drivers/pps/pps.c memcpy(&compat.info.assert_tu, &pps->assert_tu, pps 284 drivers/pps/pps.c memcpy(&compat.info.clear_tu, &pps->clear_tu, pps 287 drivers/pps/pps.c spin_unlock_irq(&pps->lock); pps 301 drivers/pps/pps.c struct pps_device *pps = container_of(inode->i_cdev, pps 303 drivers/pps/pps.c file->private_data = pps; pps 304 drivers/pps/pps.c kobject_get(&pps->dev->kobj); pps 310 drivers/pps/pps.c struct pps_device *pps = container_of(inode->i_cdev, pps 312 drivers/pps/pps.c kobject_put(&pps->dev->kobj); pps 333 drivers/pps/pps.c struct pps_device *pps = dev_get_drvdata(dev); pps 335 drivers/pps/pps.c cdev_del(&pps->cdev); pps 338 drivers/pps/pps.c pr_debug("deallocating pps%d\n", pps->id); pps 340 drivers/pps/pps.c idr_remove(&pps_idr, pps->id); pps 344 drivers/pps/pps.c kfree(pps); pps 347 drivers/pps/pps.c int pps_register_cdev(struct pps_device *pps) pps 357 drivers/pps/pps.c err = idr_alloc(&pps_idr, pps, 0, PPS_MAX_SOURCES, GFP_KERNEL); pps 361 drivers/pps/pps.c pps->info.name); pps 366 drivers/pps/pps.c pps->id = err; pps 369 drivers/pps/pps.c devt = MKDEV(MAJOR(pps_devt), pps->id); pps 371 drivers/pps/pps.c cdev_init(&pps->cdev, &pps_cdev_fops); pps 372 drivers/pps/pps.c pps->cdev.owner = pps->info.owner; pps 374 drivers/pps/pps.c err = cdev_add(&pps->cdev, devt, 1); pps 377 drivers/pps/pps.c pps->info.name, MAJOR(pps_devt), pps->id); pps 380 drivers/pps/pps.c pps->dev = device_create(pps_class, pps->info.dev, devt, pps, pps 381 drivers/pps/pps.c "pps%d", pps->id); pps 382 drivers/pps/pps.c if (IS_ERR(pps->dev)) { pps 383 drivers/pps/pps.c err = PTR_ERR(pps->dev); pps 388 drivers/pps/pps.c pps->dev->release = pps_device_destruct; pps 390 drivers/pps/pps.c pr_debug("source %s got cdev (%d:%d)\n", pps->info.name, pps 391 drivers/pps/pps.c MAJOR(pps_devt), pps->id); pps 396 drivers/pps/pps.c cdev_del(&pps->cdev); pps 400 drivers/pps/pps.c idr_remove(&pps_idr, pps->id); pps 406 drivers/pps/pps.c void pps_unregister_cdev(struct pps_device *pps) pps 408 drivers/pps/pps.c pr_debug("unregistering pps%d\n", pps->id); pps 409 drivers/pps/pps.c pps->lookup_cookie = NULL; pps 410 drivers/pps/pps.c device_destroy(pps_class, pps->dev->devt); pps 433 drivers/pps/pps.c struct pps_device *pps; pps 437 drivers/pps/pps.c idr_for_each_entry(&pps_idr, pps, id) pps 438 drivers/pps/pps.c if (cookie == pps->lookup_cookie) pps 441 drivers/pps/pps.c return pps; pps 21 drivers/pps/sysfs.c struct pps_device *pps = dev_get_drvdata(dev); pps 23 drivers/pps/sysfs.c if (!(pps->info.mode & PPS_CAPTUREASSERT)) pps 27 drivers/pps/sysfs.c (long long) pps->assert_tu.sec, pps->assert_tu.nsec, pps 28 drivers/pps/sysfs.c pps->assert_sequence); pps 35 drivers/pps/sysfs.c struct pps_device *pps = dev_get_drvdata(dev); pps 37 drivers/pps/sysfs.c if (!(pps->info.mode & PPS_CAPTURECLEAR)) pps 41 drivers/pps/sysfs.c (long long) pps->clear_tu.sec, pps->clear_tu.nsec, pps 42 drivers/pps/sysfs.c pps->clear_sequence); pps 49 drivers/pps/sysfs.c struct pps_device *pps = dev_get_drvdata(dev); pps 51 drivers/pps/sysfs.c return sprintf(buf, "%4x\n", pps->info.mode); pps 58 drivers/pps/sysfs.c struct pps_device *pps = dev_get_drvdata(dev); pps 60 drivers/pps/sysfs.c return sprintf(buf, "%d\n", !!pps->info.echo); pps 67 drivers/pps/sysfs.c struct pps_device *pps = dev_get_drvdata(dev); pps 69 drivers/pps/sysfs.c return sprintf(buf, "%s\n", pps->info.name); pps 76 drivers/pps/sysfs.c struct pps_device *pps = dev_get_drvdata(dev); pps 78 drivers/pps/sysfs.c return sprintf(buf, "%s\n", pps->info.path); pps 136 drivers/ptp/ptp_chardev.c caps.pps = ptp->info->pps; pps 240 drivers/ptp/ptp_clock.c if (info->pps) { pps 241 drivers/ptp/ptp_clock.c struct pps_source_info pps; pps 242 drivers/ptp/ptp_clock.c memset(&pps, 0, sizeof(pps)); pps 243 drivers/ptp/ptp_clock.c snprintf(pps.name, PPS_MAX_NAME_LEN, "ptp%d", index); pps 244 drivers/ptp/ptp_clock.c pps.mode = PTP_PPS_MODE; pps 245 drivers/ptp/ptp_clock.c pps.owner = info->owner; pps 246 drivers/ptp/ptp_clock.c ptp->pps_source = pps_register_source(&pps, PTP_PPS_DEFAULTS); pps 231 drivers/ptp/ptp_dte.c .pps = 0, pps 232 drivers/ptp/ptp_ixp46x.c .pps = 0, pps 149 drivers/ptp/ptp_kvm.c .pps = 0, pps 503 drivers/ptp/ptp_pch.c .pps = 0, pps 339 drivers/ptp/ptp_qoriq.c .pps = 1, pps 34 drivers/ptp/ptp_sysfs.c PTP_SHOW_INT(pps_available, pps); pps 184 drivers/ptp/ptp_sysfs.c if (!info->pps) pps 5200 drivers/scsi/be2iscsi/be_main.c unsigned int pps, delta; pps 5223 drivers/scsi/be2iscsi/be_main.c pps = (((u32)(pbe_eq->cq_count - aic->eq_prev) * 1000) / delta); pps 5224 drivers/scsi/be2iscsi/be_main.c eqd = (pps / 1500) << 2; pps 1401 drivers/staging/media/allegro-dvt/allegro-core.c struct nal_h264_pps *pps; pps 1404 drivers/staging/media/allegro-dvt/allegro-core.c pps = kzalloc(sizeof(*pps), GFP_KERNEL); pps 1405 drivers/staging/media/allegro-dvt/allegro-core.c if (!pps) pps 1408 drivers/staging/media/allegro-dvt/allegro-core.c pps->pic_parameter_set_id = 0; pps 1409 drivers/staging/media/allegro-dvt/allegro-core.c pps->seq_parameter_set_id = 0; pps 1410 drivers/staging/media/allegro-dvt/allegro-core.c pps->entropy_coding_mode_flag = 0; pps 1411 drivers/staging/media/allegro-dvt/allegro-core.c pps->bottom_field_pic_order_in_frame_present_flag = 0; pps 1412 drivers/staging/media/allegro-dvt/allegro-core.c pps->num_slice_groups_minus1 = 0; pps 1413 drivers/staging/media/allegro-dvt/allegro-core.c pps->num_ref_idx_l0_default_active_minus1 = 2; pps 1414 drivers/staging/media/allegro-dvt/allegro-core.c pps->num_ref_idx_l1_default_active_minus1 = 2; pps 1415 drivers/staging/media/allegro-dvt/allegro-core.c pps->weighted_pred_flag = 0; pps 1416 drivers/staging/media/allegro-dvt/allegro-core.c pps->weighted_bipred_idc = 0; pps 1417 drivers/staging/media/allegro-dvt/allegro-core.c pps->pic_init_qp_minus26 = 0; pps 1418 drivers/staging/media/allegro-dvt/allegro-core.c pps->pic_init_qs_minus26 = 0; pps 1419 drivers/staging/media/allegro-dvt/allegro-core.c pps->chroma_qp_index_offset = 0; pps 1420 drivers/staging/media/allegro-dvt/allegro-core.c pps->deblocking_filter_control_present_flag = 1; pps 1421 drivers/staging/media/allegro-dvt/allegro-core.c pps->constrained_intra_pred_flag = 0; pps 1422 drivers/staging/media/allegro-dvt/allegro-core.c pps->redundant_pic_cnt_present_flag = 0; pps 1423 drivers/staging/media/allegro-dvt/allegro-core.c pps->transform_8x8_mode_flag = 0; pps 1424 drivers/staging/media/allegro-dvt/allegro-core.c pps->pic_scaling_matrix_present_flag = 0; pps 1425 drivers/staging/media/allegro-dvt/allegro-core.c pps->second_chroma_qp_index_offset = 0; pps 1427 drivers/staging/media/allegro-dvt/allegro-core.c size = nal_h264_write_pps(&dev->plat_dev->dev, dest, n, pps); pps 1429 drivers/staging/media/allegro-dvt/allegro-core.c kfree(pps); pps 679 drivers/staging/media/allegro-dvt/nal-h264.c static void nal_h264_rbsp_pps(struct rbsp *rbsp, struct nal_h264_pps *pps) pps 683 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->pic_parameter_set_id); pps 684 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->seq_parameter_set_id); pps 685 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bit(rbsp, &pps->entropy_coding_mode_flag); pps 686 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bit(rbsp, &pps->bottom_field_pic_order_in_frame_present_flag); pps 687 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->num_slice_groups_minus1); pps 688 drivers/staging/media/allegro-dvt/nal-h264.c if (pps->num_slice_groups_minus1 > 0) { pps 689 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->slice_group_map_type); pps 690 drivers/staging/media/allegro-dvt/nal-h264.c switch (pps->slice_group_map_type) { pps 692 drivers/staging/media/allegro-dvt/nal-h264.c for (i = 0; i < pps->num_slice_groups_minus1; i++) pps 693 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->run_length_minus1[i]); pps 696 drivers/staging/media/allegro-dvt/nal-h264.c for (i = 0; i < pps->num_slice_groups_minus1; i++) { pps 697 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->top_left[i]); pps 698 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->bottom_right[i]); pps 702 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bit(rbsp, &pps->slice_group_change_direction_flag); pps 703 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->slice_group_change_rate_minus1); pps 706 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->pic_size_in_map_units_minus1); pps 707 drivers/staging/media/allegro-dvt/nal-h264.c for (i = 0; i < pps->pic_size_in_map_units_minus1; i++) pps 709 drivers/staging/media/allegro-dvt/nal-h264.c order_base_2(pps->num_slice_groups_minus1 + 1), pps 710 drivers/staging/media/allegro-dvt/nal-h264.c &pps->slice_group_id[i]); pps 716 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->num_ref_idx_l0_default_active_minus1); pps 717 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_uev(rbsp, &pps->num_ref_idx_l1_default_active_minus1); pps 718 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bit(rbsp, &pps->weighted_pred_flag); pps 719 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bits(rbsp, 2, &pps->weighted_bipred_idc); pps 720 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_sev(rbsp, &pps->pic_init_qp_minus26); pps 721 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_sev(rbsp, &pps->pic_init_qs_minus26); pps 722 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_sev(rbsp, &pps->chroma_qp_index_offset); pps 723 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bit(rbsp, &pps->deblocking_filter_control_present_flag); pps 724 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bit(rbsp, &pps->constrained_intra_pred_flag); pps 725 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bit(rbsp, &pps->redundant_pic_cnt_present_flag); pps 727 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bit(rbsp, &pps->transform_8x8_mode_flag); pps 728 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_bit(rbsp, &pps->pic_scaling_matrix_present_flag); pps 729 drivers/staging/media/allegro-dvt/nal-h264.c if (pps->pic_scaling_matrix_present_flag) pps 731 drivers/staging/media/allegro-dvt/nal-h264.c rbsp_sev(rbsp, &pps->second_chroma_qp_index_offset); pps 841 drivers/staging/media/allegro-dvt/nal-h264.c void *dest, size_t n, struct nal_h264_pps *pps) pps 860 drivers/staging/media/allegro-dvt/nal-h264.c nal_h264_rbsp_pps(&rbsp, pps); pps 883 drivers/staging/media/allegro-dvt/nal-h264.c struct nal_h264_pps *pps, void *src, size_t n) pps 897 drivers/staging/media/allegro-dvt/nal-h264.c nal_h264_rbsp_pps(&rbsp, pps); pps 200 drivers/staging/media/allegro-dvt/nal-h264.h void *dest, size_t n, struct nal_h264_pps *pps); pps 202 drivers/staging/media/allegro-dvt/nal-h264.h struct nal_h264_pps *pps, void *src, size_t n); pps 203 drivers/staging/media/allegro-dvt/nal-h264.h void nal_h264_print_pps(const struct device *dev, struct nal_h264_pps *pps); pps 28 drivers/staging/media/hantro/hantro_g1_h264_dec.c const struct v4l2_ctrl_h264_pps *pps = ctrls->pps; pps 60 drivers/staging/media/hantro/hantro_g1_h264_dec.c reg = G1_REG_DEC_CTRL2_CH_QP_OFFSET(pps->chroma_qp_index_offset) | pps 61 drivers/staging/media/hantro/hantro_g1_h264_dec.c G1_REG_DEC_CTRL2_CH_QP_OFFSET2(pps->second_chroma_qp_index_offset); pps 72 drivers/staging/media/hantro/hantro_g1_h264_dec.c G1_REG_DEC_CTRL3_INIT_QP(pps->pic_init_qp_minus26 + 26) | pps 79 drivers/staging/media/hantro/hantro_g1_h264_dec.c G1_REG_DEC_CTRL4_WEIGHT_BIPR_IDC(pps->weighted_bipred_idc); pps 80 drivers/staging/media/hantro/hantro_g1_h264_dec.c if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) pps 86 drivers/staging/media/hantro/hantro_g1_h264_dec.c if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) pps 93 drivers/staging/media/hantro/hantro_g1_h264_dec.c if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) pps 95 drivers/staging/media/hantro/hantro_g1_h264_dec.c if (pps->flags & V4L2_H264_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT) pps 97 drivers/staging/media/hantro/hantro_g1_h264_dec.c if (pps->flags & V4L2_H264_PPS_FLAG_REDUNDANT_PIC_CNT_PRESENT) pps 99 drivers/staging/media/hantro/hantro_g1_h264_dec.c if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) pps 107 drivers/staging/media/hantro/hantro_g1_h264_dec.c G1_REG_DEC_CTRL6_REFIDX0_ACTIVE(pps->num_ref_idx_l0_default_active_minus1 + 1) | pps 108 drivers/staging/media/hantro/hantro_g1_h264_dec.c G1_REG_DEC_CTRL6_REFIDX1_ACTIVE(pps->num_ref_idx_l1_default_active_minus1 + 1) | pps 589 drivers/staging/media/hantro/hantro_h264.c ctrls->pps = pps 591 drivers/staging/media/hantro/hantro_h264.c if (WARN_ON(!ctrls->pps)) pps 62 drivers/staging/media/hantro/hantro_hw.h const struct v4l2_ctrl_h264_pps *pps; pps 59 drivers/staging/media/sunxi/cedrus/cedrus.h const struct v4l2_ctrl_h264_pps *pps; pps 52 drivers/staging/media/sunxi/cedrus/cedrus_dec.c run.h264.pps = cedrus_find_control_data(ctx, pps 301 drivers/staging/media/sunxi/cedrus/cedrus_h264.c const struct v4l2_ctrl_h264_pps *pps = run->h264.pps; pps 330 drivers/staging/media/sunxi/cedrus/cedrus_h264.c if (((pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) && pps 333 drivers/staging/media/sunxi/cedrus/cedrus_h264.c (pps->weighted_bipred_idc == 1 && pps 353 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (pps->weighted_bipred_idc & 0x3) << 2; pps 354 drivers/staging/media/sunxi/cedrus/cedrus_h264.c if (pps->flags & V4L2_H264_PPS_FLAG_ENTROPY_CODING_MODE) pps 356 drivers/staging/media/sunxi/cedrus/cedrus_h264.c if (pps->flags & V4L2_H264_PPS_FLAG_WEIGHTED_PRED) pps 358 drivers/staging/media/sunxi/cedrus/cedrus_h264.c if (pps->flags & V4L2_H264_PPS_FLAG_CONSTRAINED_INTRA_PRED) pps 360 drivers/staging/media/sunxi/cedrus/cedrus_h264.c if (pps->flags & V4L2_H264_PPS_FLAG_TRANSFORM_8X8_MODE) pps 401 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (pps->second_chroma_qp_index_offset & 0x3f) << 16; pps 402 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (pps->chroma_qp_index_offset & 0x3f) << 8; pps 403 drivers/staging/media/sunxi/cedrus/cedrus_h264.c reg |= (pps->pic_init_qp_minus26 + 26 + slice->slice_qp_delta) & 0x3f; pps 428 drivers/staging/sm750fb/sm750_hw.c unsigned int dpms, pps, crtdb; pps 431 drivers/staging/sm750fb/sm750_hw.c pps = 0; pps 438 drivers/staging/sm750fb/sm750_hw.c pps = PANEL_DISPLAY_CTRL_DATA; pps 472 drivers/staging/sm750fb/sm750_hw.c val |= pps; pps 105 drivers/video/fbdev/clps711x-fb.c u32 lcdcon, pps; pps 131 drivers/video/fbdev/clps711x-fb.c pps = clk_get_rate(cfb->clk) / (PICOS2KHZ(info->var.pixclock) * 1000); pps 132 drivers/video/fbdev/clps711x-fb.c if (pps) pps 133 drivers/video/fbdev/clps711x-fb.c pps--; pps 134 drivers/video/fbdev/clps711x-fb.c lcdcon |= (pps & 0x3f) << 19; pps 4320 drivers/video/fbdev/omap2/omapfb/dss/dsi.c int bl, wc, pps, tot; pps 4323 drivers/video/fbdev/omap2/omapfb/dss/dsi.c pps = DIV_ROUND_UP(wc + 6, t->ndl); /* pixel packet size */ pps 4325 drivers/video/fbdev/omap2/omapfb/dss/dsi.c tot = bl + pps; pps 4333 drivers/video/fbdev/omap2/omapfb/dss/dsi.c t->hss, t->hsa, t->hse, t->hbp, pps, t->hfp, pps 4334 drivers/video/fbdev/omap2/omapfb/dss/dsi.c bl, pps, tot, pps 4339 drivers/video/fbdev/omap2/omapfb/dss/dsi.c TO_DSI_T(pps), pps 4343 drivers/video/fbdev/omap2/omapfb/dss/dsi.c TO_DSI_T(pps), pps 706 include/linux/mlx5/device.h struct mlx5_eqe_pps pps; pps 1239 include/linux/mlx5/mlx5_ifc.h u8 pps[0x1]; pps 28 include/linux/pps_kernel.h void (*echo)(struct pps_device *pps, pps 78 include/linux/pps_kernel.h extern int pps_register_cdev(struct pps_device *pps); pps 79 include/linux/pps_kernel.h extern void pps_unregister_cdev(struct pps_device *pps); pps 87 include/linux/pps_kernel.h extern void pps_unregister_source(struct pps_device *pps); pps 88 include/linux/pps_kernel.h extern void pps_event(struct pps_device *pps, pps 127 include/linux/ptp_clock_kernel.h int pps; pps 41 include/uapi/linux/gen_stats.h __u32 pps; pps 51 include/uapi/linux/gen_stats.h __u64 pps; pps 41 include/uapi/linux/pkt_sched.h __u32 pps; /* Current flow packet rate */ pps 88 include/uapi/linux/ptp_clock.h int pps; /* Whether the clock supports a PPS callback. */ pps 2341 net/ceph/osdmap.c u32 pps = raw_pg_to_pps(pi, raw_pgid); pps 2347 net/ceph/osdmap.c *ppps = pps; pps 2364 net/ceph/osdmap.c len = do_crush(osdmap, ruleno, pps, raw->osds, pi->size, pps 2482 net/ceph/osdmap.c u32 pps, pps 2522 net/ceph/osdmap.c pps, osd) >> 16) >= aff) { pps 2609 net/ceph/osdmap.c u32 pps; pps 2614 net/ceph/osdmap.c pg_to_raw_osds(osdmap, pi, raw_pgid, up, &pps); pps 2617 net/ceph/osdmap.c apply_primary_affinity(osdmap, pi, pps, up); pps 261 net/core/gen_estimator.c sample->pps = est->avpps >> 8; pps 260 net/core/gen_stats.c est.pps = sample.pps; pps 264 net/core/gen_stats.c d->tc_stats.pps = est.pps; pps 3144 net/core/pktgen.c __u64 bps, mbps, pps; pps 3157 net/core/pktgen.c pps = div64_u64(pkt_dev->sofar * NSEC_PER_SEC, pps 3160 net/core/pktgen.c bps = pps * 8 * pkt_dev->cur_pkt_size; pps 3165 net/core/pktgen.c (unsigned long long)pps, pps 26 net/netfilter/xt_rateest.c pps1 = info->pps1 >= sample.pps ? info->pps1 - sample.pps : 0; pps 29 net/netfilter/xt_rateest.c pps1 = sample.pps; pps 40 net/netfilter/xt_rateest.c pps2 = info->pps2 >= sample.pps ? info->pps2 - sample.pps : 0; pps 43 net/netfilter/xt_rateest.c pps2 = sample.pps; pps 237 samples/bpf/xdp_monitor_user.c double pps = 0; pps 241 samples/bpf/xdp_monitor_user.c pps = packets / period; pps 243 samples/bpf/xdp_monitor_user.c return pps; pps 249 samples/bpf/xdp_monitor_user.c double pps = 0; pps 253 samples/bpf/xdp_monitor_user.c pps = packets / period; pps 255 samples/bpf/xdp_monitor_user.c return pps; pps 261 samples/bpf/xdp_monitor_user.c double pps = 0; pps 265 samples/bpf/xdp_monitor_user.c pps = packets / period; pps 267 samples/bpf/xdp_monitor_user.c return pps; pps 273 samples/bpf/xdp_monitor_user.c double pps = 0; pps 277 samples/bpf/xdp_monitor_user.c pps = packets / period; pps 279 samples/bpf/xdp_monitor_user.c return pps; pps 285 samples/bpf/xdp_monitor_user.c double pps = 0; pps 289 samples/bpf/xdp_monitor_user.c pps = packets / period; pps 291 samples/bpf/xdp_monitor_user.c return pps; pps 300 samples/bpf/xdp_monitor_user.c double t = 0, pps = 0; pps 323 samples/bpf/xdp_monitor_user.c pps = calc_pps_u64(r, p, t); pps 324 samples/bpf/xdp_monitor_user.c if (pps > 0) pps 326 samples/bpf/xdp_monitor_user.c rec_i ? 0.0: pps, rec_i ? pps : 0.0, pps 329 samples/bpf/xdp_monitor_user.c pps = calc_pps_u64(&rec->total, &prev->total, t); pps 331 samples/bpf/xdp_monitor_user.c rec_i ? 0.0: pps, rec_i ? pps : 0.0, err2str(rec_i)); pps 348 samples/bpf/xdp_monitor_user.c pps = calc_pps_u64(r, p, t); pps 349 samples/bpf/xdp_monitor_user.c if (pps > 0) pps 351 samples/bpf/xdp_monitor_user.c 0.0, pps, action2str(rec_i)); pps 353 samples/bpf/xdp_monitor_user.c pps = calc_pps_u64(&rec->total, &prev->total, t); pps 354 samples/bpf/xdp_monitor_user.c if (pps > 0) pps 356 samples/bpf/xdp_monitor_user.c 0.0, pps, action2str(rec_i)); pps 374 samples/bpf/xdp_monitor_user.c pps = calc_pps(r, p, t); pps 379 samples/bpf/xdp_monitor_user.c info = pps / info; /* calc average bulk size */ pps 381 samples/bpf/xdp_monitor_user.c if (pps > 0) pps 383 samples/bpf/xdp_monitor_user.c i, to_cpu, pps, drop, info, info_str); pps 385 samples/bpf/xdp_monitor_user.c pps = calc_pps(&rec->total, &prev->total, t); pps 386 samples/bpf/xdp_monitor_user.c if (pps > 0) { pps 391 samples/bpf/xdp_monitor_user.c info = pps / info; /* calc average bulk size */ pps 394 samples/bpf/xdp_monitor_user.c "sum", to_cpu, pps, drop, info, info_str); pps 413 samples/bpf/xdp_monitor_user.c pps = calc_pps(r, p, t); pps 418 samples/bpf/xdp_monitor_user.c if (pps > 0 || drop > 0) pps 420 samples/bpf/xdp_monitor_user.c i, pps, drop, info, i_str); pps 422 samples/bpf/xdp_monitor_user.c pps = calc_pps(&rec->total, &prev->total, t); pps 427 samples/bpf/xdp_monitor_user.c printf(fmt2, "cpumap-kthread", "total", pps, drop, info, i_str); pps 446 samples/bpf/xdp_monitor_user.c pps = calc_pps(r, p, t); pps 452 samples/bpf/xdp_monitor_user.c info = (pps+drop) / info; /* calc avg bulk */ pps 456 samples/bpf/xdp_monitor_user.c if (pps > 0 || drop > 0) pps 458 samples/bpf/xdp_monitor_user.c i, pps, drop, info, i_str, err_str); pps 460 samples/bpf/xdp_monitor_user.c pps = calc_pps(&rec->total, &prev->total, t); pps 466 samples/bpf/xdp_monitor_user.c info = (pps+drop) / info; /* calc avg bulk */ pps 470 samples/bpf/xdp_monitor_user.c printf(fmt2, "devmap-xmit", "total", pps, drop, pps 274 samples/bpf/xdp_redirect_cpu_user.c __u64 pps = 0; pps 278 samples/bpf/xdp_redirect_cpu_user.c pps = packets / period_; pps 280 samples/bpf/xdp_redirect_cpu_user.c return pps; pps 286 samples/bpf/xdp_redirect_cpu_user.c __u64 pps = 0; pps 290 samples/bpf/xdp_redirect_cpu_user.c pps = packets / period_; pps 292 samples/bpf/xdp_redirect_cpu_user.c return pps; pps 299 samples/bpf/xdp_redirect_cpu_user.c __u64 pps = 0; pps 303 samples/bpf/xdp_redirect_cpu_user.c pps = packets / period_; pps 305 samples/bpf/xdp_redirect_cpu_user.c return pps; pps 313 samples/bpf/xdp_redirect_cpu_user.c double pps = 0, drop = 0, err = 0; pps 337 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(r, p, t); pps 342 samples/bpf/xdp_redirect_cpu_user.c if (pps > 0) pps 344 samples/bpf/xdp_redirect_cpu_user.c i, pps, drop, err, errstr); pps 346 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(&rec->total, &prev->total, t); pps 349 samples/bpf/xdp_redirect_cpu_user.c printf(fm2_rx, "XDP-RX", "total", pps, drop); pps 365 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(r, p, t); pps 370 samples/bpf/xdp_redirect_cpu_user.c err = pps / err; /* calc average bulk size */ pps 372 samples/bpf/xdp_redirect_cpu_user.c if (pps > 0) pps 374 samples/bpf/xdp_redirect_cpu_user.c i, to_cpu, pps, drop, err, errstr); pps 376 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(&rec->total, &prev->total, t); pps 377 samples/bpf/xdp_redirect_cpu_user.c if (pps > 0) { pps 382 samples/bpf/xdp_redirect_cpu_user.c err = pps / err; /* calc average bulk size */ pps 385 samples/bpf/xdp_redirect_cpu_user.c "sum", to_cpu, pps, drop, err, errstr); pps 402 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(r, p, t); pps 407 samples/bpf/xdp_redirect_cpu_user.c if (pps > 0) pps 409 samples/bpf/xdp_redirect_cpu_user.c i, pps, drop, err, e_str); pps 411 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(&rec->total, &prev->total, t); pps 416 samples/bpf/xdp_redirect_cpu_user.c printf(fm2_k, "cpumap_kthread", "total", pps, drop, err, e_str); pps 431 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(r, p, t); pps 433 samples/bpf/xdp_redirect_cpu_user.c if (pps > 0) pps 434 samples/bpf/xdp_redirect_cpu_user.c printf(fmt_err, "redirect_err", i, pps, drop); pps 436 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(&rec->total, &prev->total, t); pps 438 samples/bpf/xdp_redirect_cpu_user.c printf(fm2_err, "redirect_err", "total", pps, drop); pps 453 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(r, p, t); pps 455 samples/bpf/xdp_redirect_cpu_user.c if (pps > 0) pps 456 samples/bpf/xdp_redirect_cpu_user.c printf(fmt_err, "xdp_exception", i, pps, drop); pps 458 samples/bpf/xdp_redirect_cpu_user.c pps = calc_pps(&rec->total, &prev->total, t); pps 460 samples/bpf/xdp_redirect_cpu_user.c printf(fm2_err, "xdp_exception", "total", pps, drop); pps 319 samples/bpf/xdp_rxq_info_user.c __u64 pps = 0; pps 323 samples/bpf/xdp_rxq_info_user.c pps = packets / period_; pps 325 samples/bpf/xdp_rxq_info_user.c return pps; pps 332 samples/bpf/xdp_rxq_info_user.c __u64 pps = 0; pps 336 samples/bpf/xdp_rxq_info_user.c pps = packets / period_; pps 338 samples/bpf/xdp_rxq_info_user.c return pps; pps 347 samples/bpf/xdp_rxq_info_user.c double pps = 0, err = 0; pps 373 samples/bpf/xdp_rxq_info_user.c pps = calc_pps (r, p, t); pps 377 samples/bpf/xdp_rxq_info_user.c if (pps > 0) pps 379 samples/bpf/xdp_rxq_info_user.c i, pps, err, errstr); pps 381 samples/bpf/xdp_rxq_info_user.c pps = calc_pps (&rec->total, &prev->total, t); pps 383 samples/bpf/xdp_rxq_info_user.c printf(fm2_rx, "XDP-RX CPU", "total", pps, err); pps 407 samples/bpf/xdp_rxq_info_user.c pps = calc_pps (r, p, t); pps 415 samples/bpf/xdp_rxq_info_user.c if (pps > 0) pps 417 samples/bpf/xdp_rxq_info_user.c rxq_, i, pps, err, errstr); pps 419 samples/bpf/xdp_rxq_info_user.c pps = calc_pps (&rec->total, &prev->total, t); pps 421 samples/bpf/xdp_rxq_info_user.c if (pps || err) pps 422 samples/bpf/xdp_rxq_info_user.c printf(fm2_rx, "rx_queue_index", rxq_, "sum", pps, err); pps 40 tools/include/uapi/linux/pkt_sched.h __u32 pps; /* Current flow packet rate */ pps 174 tools/testing/selftests/ptp/testptp.c int pps = -1; pps 221 tools/testing/selftests/ptp/testptp.c pps = atoi(optarg); pps 277 tools/testing/selftests/ptp/testptp.c caps.pps, pps 422 tools/testing/selftests/ptp/testptp.c if (pps != -1) { pps 423 tools/testing/selftests/ptp/testptp.c int enable = pps ? 1 : 0;