ppll_ref_div 878 drivers/gpu/drm/radeon/radeon_legacy_tv.c uint32_t *htotal_cntl, uint32_t *ppll_ref_div, ppll_ref_div 890 drivers/gpu/drm/radeon/radeon_legacy_tv.c *ppll_ref_div = const_ptr->crtcPLL_M; ppll_ref_div 961 drivers/gpu/drm/radeon/radeon_mode.h uint32_t *htotal_cntl, uint32_t *ppll_ref_div, ppll_ref_div 1352 drivers/video/fbdev/aty/radeon_base.c save->ppll_ref_div = INPLL(PPLL_REF_DIV); ppll_ref_div 1371 drivers/video/fbdev/aty/radeon_base.c if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && ppll_ref_div 1406 drivers/video/fbdev/aty/radeon_base.c if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { ppll_ref_div 1410 drivers/video/fbdev/aty/radeon_base.c OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); ppll_ref_div 1414 drivers/video/fbdev/aty/radeon_base.c (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), ppll_ref_div 1418 drivers/video/fbdev/aty/radeon_base.c OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); ppll_ref_div 1639 drivers/video/fbdev/aty/radeon_base.c regs->ppll_ref_div = rinfo->pll.ref_div; ppll_ref_div 1710 drivers/video/fbdev/aty/radeon_base.c newmode->ppll_ref_div = rinfo->panel_info.ref_divider; ppll_ref_div 237 drivers/video/fbdev/aty/radeonfb.h u32 ppll_ref_div;