pp_on            2067 drivers/gpu/drm/gma500/cdv_intel_dp.c                 u32 pp_on, pp_off, pp_div;
pp_on            2070 drivers/gpu/drm/gma500/cdv_intel_dp.c 		pp_on = REG_READ(PP_CONTROL);
pp_on            2071 drivers/gpu/drm/gma500/cdv_intel_dp.c 		pp_on &= ~PANEL_UNLOCK_MASK;
pp_on            2072 drivers/gpu/drm/gma500/cdv_intel_dp.c 	        pp_on |= PANEL_UNLOCK_REGS;
pp_on            2074 drivers/gpu/drm/gma500/cdv_intel_dp.c 		REG_WRITE(PP_CONTROL, pp_on);
pp_on            2080 drivers/gpu/drm/gma500/cdv_intel_dp.c                 pp_on = REG_READ(PP_ON_DELAYS);
pp_on            2085 drivers/gpu/drm/gma500/cdv_intel_dp.c                 cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
pp_on            2088 drivers/gpu/drm/gma500/cdv_intel_dp.c                 cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
pp_on            1016 drivers/gpu/drm/i915/display/intel_dp.c 	i915_reg_t pp_on;
pp_on            1036 drivers/gpu/drm/i915/display/intel_dp.c 	regs->pp_on = PP_ON_DELAYS(pps_idx);
pp_on            6381 drivers/gpu/drm/i915/display/intel_dp.c 	u32 pp_on, pp_off, pp_ctl;
pp_on            6392 drivers/gpu/drm/i915/display/intel_dp.c 	pp_on = I915_READ(regs.pp_on);
pp_on            6396 drivers/gpu/drm/i915/display/intel_dp.c 	seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on);
pp_on            6397 drivers/gpu/drm/i915/display/intel_dp.c 	seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on);
pp_on            6533 drivers/gpu/drm/i915/display/intel_dp.c 	u32 pp_on, pp_off, port_sel = 0;
pp_on            6568 drivers/gpu/drm/i915/display/intel_dp.c 	pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) |
pp_on            6594 drivers/gpu/drm/i915/display/intel_dp.c 	pp_on |= port_sel;
pp_on            6596 drivers/gpu/drm/i915/display/intel_dp.c 	I915_WRITE(regs.pp_on, pp_on);
pp_on            6616 drivers/gpu/drm/i915/display/intel_dp.c 		      I915_READ(regs.pp_on),